Computer Architecture
CS F342
CA-LECT3
Instructions:
Language of the Computer
BITS Pilani, Hyderabad Campus
Instruction Set
• The repertoire of instructions of a computer
• Different computers have different instruction
sets
– But with many aspects in common
• Early computers had very simple instruction
sets
– Simplified implementation
• Many modern computers also have simple
instruction sets
BITS Pilani, Hyderabad Campus
The MIPS Instruction Set
• Used as the example throughout the book
• Stanford MIPS commercialized by MIPS Technologies
Large share of embedded core market
– Applications in consumer electronics, network/storage
equipment, cameras, printers, …
• Typical of many modern ISAs
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Arithmetic Operations
• Add and subtract, three operands
– Two sources and one destination
add a, b, c # a gets b + c
• All arithmetic operations have this form
• Design Principle 1: Simplicity favours regularity
– Regularity makes implementation simpler
– Simplicity enables higher performance at lower
cost
BITS Pilani, Hyderabad Campus
Arithmetic Example
• C code:
f = (g + h) - (i + j);
• Compiled MIPS code:
add t0, g, h # temp t0 = g + h
add t1, i, j # temp t1 = i + j
sub f, t0, t1 # f = t0 - t1
BITS Pilani, Hyderabad Campus
Register Operands
• Arithmetic instructions use register
operands
• MIPS has a 32 × 32-bit register file
– Use for frequently accessed data
– Numbered 0 to 31
– 32-bit data called a “word”
• Assembler names
– $t0, $t1, …, $t9 for temporary values
– $s0, $s1, …, $s7 for saved variables
• Design Principle 2: Smaller is faster
– c.f. main memory: millions of locations
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Register Operand Example
• C code:
f = (g + h) - (i + j);
– f, …, j in $s0, …, $s4
• Compiled MIPS code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
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Memory Operands
• Main memory used for composite data
– Arrays, structures, dynamic data
• To apply arithmetic operations
– Load values from memory into registers
– Store result from register to memory
• Memory is byte addressed
– Each address identifies an 8-bit byte
• Words are aligned in memory
– Address must be a multiple of 4
• MIPS is Big Endian
– Most-significant byte at least address of a word
– c.f. Little Endian: least-significant byte at least address
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Memory Operand Example 1
• C code:
g = h + A[8];
– g in $s1, h in $s2, base address of A in $s3
• Compiled MIPS code:
– Index 8 requires offset of 32
• 4 bytes per word
lw $t0, 32($s3) # load word
add $s1,
offset
$s2, $t0
base register
BITS Pilani, Hyderabad Campus
Memory Operand Example 2
• C code:
A[12] = h + A[8];
– h in $s2, base address of A in $s3
• Compiled MIPS code:
– Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word
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Registers vs. Memory
• Registers are faster to access than memory
• Operating on memory data requires loads and
stores
– More instructions to be executed
• Compiler must use registers for variables as
much as possible
– Only spill to memory for less frequently used
variables
– Register optimization is important!
BITS Pilani, Hyderabad Campus
Immediate Operands
• Constant data specified in an instruction
addi $s3, $s3, 4
• No subtract immediate instruction
– Just use a negative constant
addi $s2, $s1, -1
• Design Principle 3: Make the common case
fast
– Small constants are common
– Immediate operand avoids a load instruction
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The Constant Zero
• MIPS register 0 ($zero) is the constant 0
– Cannot be overwritten
• Useful for common operations
– E.g., move between registers
add $t2, $s1, $zero
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Unsigned Binary Integers
• Given an n-bit number
x xn12n1 xn2 2n2 x121 x0 20
• Range: 0 to +2n – 1
• Example
– 0000 0000 0000 0000 0000 0000 0000 10112
= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
• Using 32 bits
– 0 to +4,294,967,295
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2s-Complement Signed Integers
• Given an n-bit number
x xn12n1 xn2 2n2 x121 x0 20
• Range: –2n – 1 to +2n – 1 – 1
• Example
– 1111 1111 1111 1111 1111 1111 1111 11002
= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
• Using 32 bits
– –2,147,483,648 to +2,147,483,647
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2s-Complement Signed Integers
• Bit 31 is sign bit
– 1 for negative numbers
– 0 for non-negative numbers
• –(–2n – 1) can’t be represented
• Non-negative numbers have the same unsigned and
2s-complement representation
• Some specific numbers
– 0: 0000 0000 … 0000
– –1: 1111 1111 … 1111
– Most-negative: 1000 0000 … 0000
– Most-positive: 0111 1111 … 1111
BITS Pilani, Hyderabad Campus
Signed Negation
• Complement and add 1
– Complement means 1 → 0, 0 → 1
x x 1111...1112 1
x 1 x
• Example: negate +2
– +2 = 0000 0000 … 00102
– –2 = 1111 1111 … 11012 + 1
= 1111 1111 … 11102
BITS Pilani, Hyderabad Campus
Sign Extension
• Representing a number using more bits
– Preserve the numeric value
• In MIPS instruction set
– addi: extend immediate value
– lb, lh: extend loaded byte/halfword
– beq, bne: extend the displacement
• Replicate the sign bit to the left
– c.f. unsigned values: extend with 0s
• Examples: 8-bit to 16-bit
– +2: 0000 0010 => 0000 0000 0000 0010
– –2: 1111 1110 => 1111 1111 1111 1110
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Representing Instructions
• Instructions are encoded in binary
– Called machine code
• MIPS instructions
– Encoded as 32-bit instruction words
– Small number of formats encoding operation code
(opcode), register numbers, …
– Regularity!
• Register numbers
– $t0 – $t7 are reg’s 8 – 15
– $t8 – $t9 are reg’s 24 – 25
– $s0 – $s7 are reg’s 16 – 23
BITS Pilani, Hyderabad Campus
MIPS R-format Instructions
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• Instruction fields
– op: operation code (opcode)
– rs: first source register number
– rt: second source register number
– rd: destination register number
– shamt: shift amount (00000 for now)
– funct: function code (extends opcode)
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R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
add $t0, $s1, $s2
special $s1 $s2 $t0 0 add
0 17 18 8 0 32
000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
BITS Pilani, Hyderabad Campus
Hexadecimal
• Base 16
– Compact representation of bit strings
– 4 bits per hex digit
0 0000 4 0100 8 1000 c 1100
1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111
• Example: eca8 6420
– 1110 1100 1010 1000 0110 0100 0010 0000
BITS Pilani, Hyderabad Campus
MIPS I-format Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits
• Immediate arithmetic and load/store instructions
– rt: destination or source register number
– Constant: –215 to +215 – 1
– Address: offset added to base address in rs
• Design Principle 4: Good design demands good
compromises
– Different formats complicate decoding, but allow 32-bit
instructions uniformly
– Keep formats as similar as possible
BITS Pilani, Hyderabad Campus
