FUNCTIONAL UNITS ; +A computer consists of 5 functionally independent main parts: 1)inpat, 2)memory,3)arithmetic & logic, 4)ourput and S)control units. Input Unit +The computer accepts the information in the form of program & data through an input- device, Eg: keyboard + Whenever a key is pressed, the corresponding letter/digit is automatically translated into its corresponding binary-cod= and transmitted over a cable to cither the memory or the processor, Memory Unit + This unit is used to store programs & data, + There are 2 classes of storage: 1) Primary-storage is a fast-memory that operates at elecironic-speed, Programs must be stored in the memory while they are being executed. 2) Secondary-storage is used when large amounts of data & many programs have to be stored, Eg: magnetic disks and optical disks(CD-ROMSs), +The memory contains a large number of semiconductor storage cells(ie. fi ‘capable of storing one bit of information, + The memory is organized so that the contents of one word can be stored oF retrieved in one basic operation. a COMPUTERORGANISATION Page | flops), each * Memory in which any location can be reached in a short and fixed amount of time after specifying its address is called RAM (Random Access Memory). ALU (Arithmetic & Logie Unit) + This unit is used for performi * Any arithmetic operation is i (ie. registers), where the operator arithmetic & logical operations. ted by bringing the required operand into the processor s performed by the ALU. Output Unit * This unit is used to send processed-resulis to the outside world. Eg: displays etc. * This unit is used for controlling the activities of the other units (such as memory, VO device), + This unit sends condrol-signals (read/write) to other units and senses their states, * Data transfers between processor and memory are also controlled by the control-anit through timing-signals. * Timing-signals are signals that determine when a given action is to take place. ewe. oc incon ut fo compaBASIC OPERATIONAL CONCEPTS: + The processor contains ALU, control-circuitry and many registers. + The instraction-register(IR) holds the instruction that is currently being executed. * The instruction is then passed to the control-unit, which generates the timing-signals that determine when a given action is to take place : +The PC(Program Counter) contains the memory-address of the nextinstruction to be fetched & executed. + During the execution of an instruction, the contents of PC are updated to point to next instruction. *# The processor also contains ..n” general-purpose registers RO through Ra- |. + The MSI (Memory Address Register) holds the address of the memory-location to be accessed. * The MDR (Memory Data Register) contains the data to be written into or read out of the addressed location. Following are the steps that take place to execute an instruction * The address of first instruction(to be executed) gets loaded into PC. +The contents of PC(i.e. address) are transferred to the MAR & control-unit issues Read signal to memory. * Afier certain smount of elapsed time, che first instruction is read out of memory and placed into MDR. + Nest, the contents of MDR are ransferred to IR. At this point, the instruction can be decoded & executed. + To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a result, the operand is transferred from memory into MDR, and then it is transferred from MDR to ALU. + Likewise required number cf operands is fetched into processor. + Finally, ALU performs the desired operation. + If the result of this operation is to be stored in the memory, then the result is sent to the MDR. + The address of the location where the result is to be stored is sent to the MAR and a Write cycle is initiated. ‘+ At some point during execution, contents of PC are incremented to point to next instruction in the program. [The instruction is a combination ef opcode and operand]. ews 1.2 Conactons bewees the proce and ts mteory,BUS STRUCTURE + A bus is a group of lines that serves as a connecting path for several devices. + Bus must have lines for data transfer, address & contro} purposes. + Because the bus can be used for only one tcansfer at a time, only 2 units can actively use the bus at any given time. * Bus control lines are used to arbitrate multiple requests for use of the bus. + Main advantage of single bus: Low cost and flexibility for attaching peripheral devices. + Systems that contain multiple buses achieve more concurrency in operations by allowing 2 or more transfers to be carried out at the same time. Advantage: better performance. Disadvantage: increased cost. + The devices connected to a bus vary widely in their speed of operation. To synchronize their operational speed, the approach is to include buffer registers with the devices to hold the information during transfers. Buffer registers prevent a high-speed processor from being locked to a slow I/O device during a sequence of data transfers. PLit igre 3 Soglebes sructore. PRnACEenND MmacrPERFORMANCE MEASUREMENT * SPEC(System Performance Evaluation Corporation) selects & publishes the standard programs along wich their tes! results for different application domains The SPEG rating is computed as follows * If SPEC roting=50 means that the computer under test is SOtimes as fast as reference compater, * The test is epeated for all the programs in the SPEC suite, and the geometric mean of the results is computed, Let SPEC; be the rating for program i in the suite. The overall SPEC rating for the computer is given by =i) where n=number of programs in the suiteCOMPUTER ORGANIZATION MECHANISMS USED FOR INTERFACING /O DEVICES 1) Program Controlled 1/0 « Processor repeatedly checks a status-flag to achieve required synchronization between grocessor & input/output device. (We say that the processor polls the device}, * Main drawback: The processor wastes its time in checking the status of the device before actual data transfer takes place. 2) Interrupt VO * Synchronization is achieved by having YO device send a special Signa) over bus whenever it is ready for a data transfer operation, 3} Direct Memory Access (OMA) *This involves having the device-interface transfer data directly to or fram the memary without tontinuous involvement by the processor. WwresouersINTERRUPTS + 1/0 device initiates the action instead of the processor, This is done by sending a special hardware signa/ to the processor called as interrupt(INTR), on the interrupt-request line. « The processor can be performing its cwn task without the need to continuously check the 1/0 device, + When device gets ready, it will “alert” the processor by sending an interrupt-signal (Figure 4.5). + The routine executed in response to an interrupt-request is catied ISR(|nterrupt Service Routine). * Once the Intetrupt-request signal comes from the device, the processor has to inform the device that its request has been recognizes and will be serviced soon. This is indicated by a special control signal on the bus called interrupt-acknowiedge{INtA), .INTERRUPTOHARDWARE + An I/O device requests an interrupt by activating a bus-line called Interrupt-reque 4 J Assingle IR line can be used to serve .n” devices (Figure 4.6). 31/16 alld ‘onriected bo IR line via switches to ground. sto reques:an interrupt, 'a device clases its associated switch. Thus, if ali IR signals are inactive(i-e. #4 all sy. ‘are open}, the voltage on the IR line will be equal to Vea. ; s When a device requests an interrupt By elesing its switch, the voltage on the line dropa to €, causing the INT} received by the processor to goto 1. . «The value of INTRis the logical OR of the requests from individual devices INTR=INTRi+ IMTR2+.---. +INTRe «A special gate know as open-collector or open-drain are used to drive the INTR line. « Retistor R is called a pull-up resistor because it pulls the line voltage up to the high-voltage state when the switches aré open. Va Figs Ae equicint cicuit bor tn opardeain be caedt implasent c eta aera int ENABLING & DISABLING INTERRUPTS = Ta prevent the system from entering into an infinite-leop because of interrupt, there are 3 possibilities: 1) The first possibilty is to have the protessor-hardware ignore the interrupt-request fine until tf execution of the first instruction of the 15K nas been completed. 2) The gecend option is te have the pracessor automatically disable interrupts before startog tf ‘execution of the ISR. 43) Jn the third option, the Processor has @ special interrupt-request line for which the interrupt-handll circuit resronds only to the leading edge of the signal. Such a line is said to be edge-triggered. * Sequence of events involved in handling an interrupt-request from a single device is as follows: 3) The device raises an interrupt-request. 2) The program currently being executed iS interrupted. 3) Ali internupts are disabled(ty changing tne control bits in the PS). 4) The device is informed that its request has been recognized, and 30 respanse, the device deactvates the interrupt-request signal. 5) The action réquésted by the irterrupt is pectormed by the ISR. 6) Interrupts are enabled again and execution of the interrupted program is resumed.COMPUTER ORGANIZATION EXCEPTIONS ————— + An interrupt is an event that causes — execution of one program to be suspended & > execution of another program to begin. + Exception refers to any event that causes an interruption, V/O interrupts are one example of an exception, ‘trom Errors herdware-components are operating property, For e.g, -memory which allows detection of errors in stored-data, ¢ If an error oceurs, control-hardware detects It & : + When exception processing is initiated (as @ result of errors), processor — Suspends program being executed & eres an ESRIException Service Routine). This routine takes appropriate action to recover from the error to inform user about it. Debugging + Debugger — helps programmer find errors in a program and uses exceptions to provide 2 important facilities: 1) Trace & 2) Breakpoints Selien 2 processor is operating in trace-mode. an exception occurs after execution of every instruction (using debugging-pragram as ESR). 7 Bebugaina-program enables user to examine contents of registers (AX, BX), memory-tocations and so-on, + On retum from debugging-program, ‘ext instruction in program being debugged is executed, then debugging-program is activated again. Jelccied pits Provide a similar facility except that program being debugged is internuptea only at specific points peated Dy user. An instruction called Trapfer Software interrupt) is usually provided for this purpose: Privilege Exception mua, Protect OS of computer from being corrupted by user-programs, certain instructions can be executed only while pracessor is in supervisor-mode. These are called privileged instructions. 3 Fer £:9- when the processor is running in user-mode, it will Not execute an instruction that changes priority-ievel of processor. 7 Aa akemot to execute such an instruction will produce 8 privdege-exception. As a result, processor switches to Supervisor- mode & begins to execute an appropriate routine in OS.COMPUTER ORCAS aoT RT car nat races ent any emer ne SE Ce ee Tn anand a nate be ont gue process by which nest Gece to PEO smaster in selected COMPUTER ORGANIZATION, ‘igraroures ARaITRATION Mfamce petcpate ne cocton of nat bur mater (Pure 6.22) 1 Ea dcadzon tare sesigat 08 ereteaton nator CD) ‘iter Torre devees gue bu, *Soeree Star Aestrton eon Gace this be 1B noes on for oper-ccor Ses AT tg iS 4 Aweur i ened aa reat of onerction onan signs Want ve Ehxe Hwy by ol corer maroerMapping functions: Mapping functions determine how memory blocks are placed in the cache. A simple processor example: ® Cache consisting of 128 blocks of 16 words each. ® Total size of cache is 2048 (2K) words. ® Main memory is addressable by a 16-bit address. * Main memory has 64K words. * Main memory has 4K blocks of 16 words each. Three mapping functions can be used. J. Direct mapping 2. Associative mapping 3. Set-associative mapping.Buck ofthe main memey maps te models 128 of ‘ecache-omeps to, 1297maps to ‘tore than ene memary beck mapped onto the some ‘oy ead to Ee Ai esi fall buelTak <= words ina beck Tato vo oct ner lacks placedin, 32 block cutenty present inthe cache These Sipe toumplement but not very flee ‘ain memory tock ca be placed mto any cache postion, si dooce nt to felts. der bts ey the ward wth a Block er 3 bis a9 Bs deny amen Fenble and eis coche space effet ‘Replacement ogenthns con be sed trelac on ‘ensting Beck the cece when the ache s fl higher than vet mapped are grouped ne set, toveste any Bock of aspect cache nau ses, sh two locks ger set Memory Bock 6,128 te mapto black and ey ‘aneccupy ether ef the tw poston. lemony adores duided io tree fla {tf detesnes te set umber High oder bt fetds re compared ta the tag feof the we chs sec assacawe mapping contination of ret er of sper st. devon ‘One extreme to havea the! requiag no set its ly or Other extreme to have ne blockAddressing Modes I ja) Koso (o > The deffercnd ways tm hich the Lote bin a | =— = er open 95 spestard th an thotec chen oT 9 ax mefied ty as Adbirciting Medes l > The Types of addicssty modes ghen Vege eile | calle, 2. Phsotule (Dired) mde 3. Tenmectiak mode | Mm L. Thdtvect mode 5. Trdex mode ) 3) Temes: S. Ralahe mole ! tie Fe Addhtomel’ — aclavesstg meter -) The (C1 Pate ncremend mod i ne Ct pad ecormernd mode. 2 5 tor 9 Register violet \ nd 6 dhe Contech of reaper phe ie , = ck > The caddies or name ef He deqistr 4 1S gwen Ae mshredtion - | | EF Rasiskrs ave Ved as Jemporary i 4) Indie Storege focadtrny shee the’ clade | _ RK peqibker are accessed . oe de gr 37 [Moe @ @R\ y capy tte todd 8 . [Mor Ba 7 cay Seo aoe 4 apa, BRR wumvchong® JJ.) Absotuk (Drect » Mo de nist of / = ! Th. operand ig mow memory ~ toad on 6 > The t gken exp hictty adders ef memory > Poco dh the, Hetrechew | ~~ Tor cron ple eo oe eae Tt eye memory Loch Lec ito ae 3) Tramedtiak Mode. 4 the operend her explicitly & he 9 Jngtruction i le > Tor exarple, Mra snsteuce [eee tote: glow The value BOO Regie Ro | resyter sy sker 2 Clearly) the Jnmedick, rode Tn Used to Spotty Xe valve : Source — operand . 2 4) Indiv mode Ly Trstrucim clon nol qye the opera address © Nutty + 7 > Tstesd te wstvucken — prvide Re rin drop dem coktdh Ae new cad dey el be operand San bE deveined), OY Hs> 7 The requsley a we Ths addes 'F tailed — Effeehe Arts (en) ef Ae opsand ER of tte ad % register, fl Tn Trdacck mode Abe eperend ts le contend deat emnrans, Ty aliey | on chad ig led Roink denole fle Bdrm PE same of Be ge 2 mw addess Gh weds Rarvetns F fq Add (Ri), Re, The Opernrd 9 4 emerson - Rogier a | gies He, fire adivn ef de “opal t te gah ve mneed on helm | ard added to cone’ of eqs | Re. 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