Exercice : implémentation

PIPELINE
Chemin de données de Pipeline et Contrôle
 Un exemple de séquence d'exécution
• Voici un exemple de séquence d'instructions à exécuter qui ne présente aucun HAZARD

1000: lw $8, 4($29)

1004: sub $2, $4, $5
addresses 1008: and $9, $10, $11
en décimal 1012: or $16, $17, $18
1016: add $13, $14, $0

• Nous allons faire quelques hypothèses, juste pour pouvoir montrer les valeurs réelles des
données.
1. Chaque registre contient son numéro plus 100. Par exemple, le registre 8 $ contient 108, le
registre 29 $ contient 129, etc.
2. Chaque emplacement de mémoire de données contient 99.
• Nos diagrammes de pipeline suivront certaines conventions:
1. Un X indique des valeurs qui ne sont pas importantes, comme le champ constant d'une
instruction de type R.
2. Points d'interrogation ??? indiquent des valeurs que nous ne connaissons pas, résultant
généralement d'instructions avant et après celles de notre exemple.
Travail Demandé : Compléter les champs manquants en couleur ROUGE pour chaque cycle
d’horloge
 IF: lw $8, 4($29)
Cycle 1 (remplissage)
ID: ??? EX: ??? MEM: ??? WB: ???

0 ID/EX
WB EX/MEM
PCSrc : 0 Control M WB MEM/WB
IF/ID EX M WB

4 Add
P 1004
Add
C Shift
RegWrite (?) left 2

??? ??? ???

1000 Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction ??? ??? Zero
Read Read ??? ???
address [31-0] 0
register 2 data 2 Result Address
??? Write ??? MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (???)
Write
???
data ALUSrc (?) ??? Write Read
1
data data
??? Sign ???
RegDst (?)
extend MemRead (?) ???
0
??? ???
0 ??? ??? ???
??? ???
1

???

4
 IF: sub $2, $4, $5 ID: lw $8, 4($29)
Cycle 2 EX: ??? MEM: ??? WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P 1008 Add
C Shift
RegWrite (?) left 2

29 129 ???
1004 Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction 8 Zero
Read Read 108 ???
???
address [31-0] 0
register 2 data 2 Result Address
? Write ??? MemToReg
1 Data
Instruction register (?)
memory
memory ? Registers ALUOp (???)
Write ???
data ALUSrc (?) ??? Write Read
1
data data
4 Sign ???
RegDst (?) ???
extend MemRead (?)
0
8 ???
0 ??? ??? ???
X ???
1

???

5
 IF: and $9, $10, $11 ID: sub $2, $4, $5
Cycle 3 EX: lw $8, 4($29) MEM: ??? WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P 1012
Add
C Shift
RegWrite (?) left 2

4 104 129
1008 Read Read
register 1 data 1 MemWrite (?)
ALU
Read Instruction 5 Zero
Read Read 105 108 ???
address [31-0] 0
register 2 data 2 Result Address
__
??? Write 133 MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (100)
Write
??? Write ???
data ALUSrc (1) Read
1
data data
X Sign 4
RegDst (0)
extend MemRead (?) ???
0
X 8
0 8 ??? ???
2 X
1

???

6
 IF: or $16, $17, $18 ID: and $9, $10, $11
Cycle 4 EX: sub $2, $4, $5 MEM: lw $8, 4($29) WB: ???

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P 1016
Add
C Shift
RegWrite (?) left 2

10 110 104
1012 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction 11 105 Zero
Read Read 111 133
address [31-0] 0
register 2 data 2 Result Address
–1
??? Write MemToReg
1 Data
Instruction register (?)
memory
memory ??? Registers ALUOp (sub)
Write
99_ ???
data ALUSrc (0) __ Write Read
1
data data
X Sign X
RegDst (1)
extend MemRead (1) ???
0
X X
0 2 8 ???
9 2
1

???

7
 IF: add $13, $14, $0
Cycle 5 (Pipeline)
ID: or $16, $17, $18 EX: and $9, $10, $11 MEM: sub $2, $4, $5 WB:
lw $8, 4($29)
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P 1020 Add
C Shift
RegWrite (1) left 2

17 117 110
1016 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction 18 111 Zero
Read Read 118 -1
address [31-0] 0
register 2 data 2 Result Address
8 Write 110 MemToReg
1 Data
Instruction register (1)
memory
memory 99 Write Registers ALUOp (and)
X 99
___
data ALUSrc (0) 105 Write Read
1
data data
X Sign X
RegDst (1)
extend MemRead (0) 133
0
X X
0 9 2 8
16 9
1

99

8
 IF: ???
Cycle 6 (Vidage)
ID: add $13, $14, $0 EX: or $16, $17, $18 MEM: and $9, $10, $11 WB: sub
$2, $4, $5
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P ???
Add
C Shift
RegWrite (1) left 2

14 114 117
1020 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction 0 0 118 Zero
Read Read 110
address [31-0] 0
register 2 data 2 Result Address
2 Write 119 MemToReg
1 Data
Instruction register (0)
memory
memory -1 Registers ALUOp (or)
Write X
111 X
data ALUSrc (0) Write Read
1
data data -1
X Sign X
RegDst (1) -1
extend MemRead (0)
0
0 X
0 16 9
13 16
1 2

9
 IF: ??? ID: ???
Cycle 7 EX: add $13, $14, $0 MEM: or $16, $17, $18 WB: and
$9, $10, $11
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P ???
Add
C Shift
RegWrite (1) left 2

??? ??? 114

1020 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction ??? ??? 0 Zero
Read Read 119
address [31-0] 0
register 2 data 2 Result Address
9 Write 114 MemToReg
1 Data
Instruction register (0)
memory
memory 110 Registers ALUOp (add)
Write X
118 X
data ALUSrc (0) Write Read
1
data data 110
??? Sign X
RegDst (1) 110
extend MemRead (0)
0
??? 0
0 13 16
??? 13
1 9

10
 IF: ??? ID: ???
Cycle 8 EX: ??? MEM: add $13, $14, $0 WB: or $16,
$17, $18
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P ???
Add
C Shift
RegWrite (1) left 2

??? ??? ???

1020 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction ??? ??? ??? Zero
Read Read 114
address [31-0] 0
register 2 data 2 Result Address
16 Write ??? MemToReg
1 Data
Instruction register (0)
memory
memory 119 Registers ALUOp (???)
Write X
0 X
data ALUSrc (0) Write Read
1
data data 119
??? Sign ???
RegDst (1) 119
extend MemRead (0)
0
??? ???
0 ??? 13
??? ???
1 16

11
 IF: ??? ID: ???
Cycle 9 EX: ??? MEM: ??? WB: add
$13, $14, $0
1

0 ID/EX
WB EX/MEM
PCSrc Control M WB MEM/WB
IF/ID EX M WB

4 Add
P ???
Add
C Shift
RegWrite (1) left 2

??? ??? ???

1020 Read Read
register 1 data 1 MemWrite (0)
ALU
Read Instruction ??? ??? ??? Zero
Read Read ???
address [31-0] 0
register 2 data 2 Result Address
13 Write ??? MemToReg
1 Data
Instruction register (0)
memory
memory 114 Registers ALUOp (???)
Write X
??? ???
data ALUSrc (0) Write Read
1
data data 114
??? Sign __ 114
RegDst (1)
extend MemRead (0)
0
??? __
0 __ __
??? __
1 13

12