MICROCHIP dsPIC30F3014/4013 Data Sheet High-Performance, 16-bit Digital Signal Controllers 08701386Note the following de + Microchip products mest the specifcaton contained in their particular Microchip Data Shoot, of the code protection feature on Microchip devices: + Miceoenip believes that its family of producs is one of the most secure famies ois kind onthe market foday, when used in the intended manner and under normal conditions. + There are dishonest and possibly itegal methods used to breach the code protection fealue, Al ofthese methods, to our knowledge, require using the Microch products in a manner ousige the operating specications contained in Microchip's Data ‘Shoots. Most Ikely, the person doing so is engaged in theft of inteloctal property + Microchips ling to work with the customer who is concemed about the Integy of thle code. + Neither Microchip nor any other semiconductor manufacturer can guarantee the securiy oftheir code. Code protection does nat ‘mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are commited to continuously improving the cade protection features of our products. Attempts to break Microchip's code protection feature may be a Wolaton of he Dial Milonnium Copyright Act. such acts alow unauthorized access to your software or ether copyrighted war, you may ha right to sus fr rllf under that Ac. Information contained in this publication regarding device appleations andthe Ike is provided ony for your convenience. ‘and may be superseded by updates. tis your responsibilty to fensure that your application meets with your specications, MICROCHIP MAKES NO REPRESENTATIONS OR. WARRANTIES OF ANY KINO WHETHER EXPRESS OR. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING UT NOT LIMITED TO ITS CONDITION. QUALITY, PERFORMANCE, MERCHANTABILITY OR. FITNESS FOR PURPOSE. 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QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV ==1SO/TS 16949:2002 = Trademarks ‘The Microchip name and logo, the Microchip logo, dsPIC, KerLoa, KEEL0G logo, MPLAB, PIC, PICmicro, PICSTART, PIC® log9, fPIC and UNUO are registered tradomarks of Microchip Technology Incorporated in the U.S.A. and other counties FiterLab, Hampshire, H-TECH ©, Linear Active Theemstor, MXOEY, MXLAB, SEEVAL ané The Embedded Control Solutions Company are registered trademarks of Microchip, Technology Incorporated in the U.S.A Analog-or-he-Digtal Age, Application Maesto, CodeGurd {sPICDEM, dsPICOEM net, dsPICworks, d8SPEAK, ECAN, ECONOMONITOR, FanSensa, HL-TIDE, ImCircut Serial Programming, IGS, Mine, Mi, MPASM, MPLAB Certified loge, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM. net, PICKI, Pictal, REAL ICE, fLAB, Select Mode, Total Endurance, ‘TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incerporated inthe USA and olver countries SQTP sa service mark of Microchip Technology Incorporated inthe USA, [Nother trademarks mentioned herein are property oftheir respective companies. {© 2010, Microchip Technology Incorporated, Printed inthe USA, AllRights Reserved £2 Pied on rocyte paper. ISBN: 976-1-60952.666-1 -Merocnp received SOTS-16049-2002ceieaton ort worse hadrons desig and water labreaton lies n Cheer an Temps, Arron Sanam Oregon and design contre n Caltemis. anaindia"The Company® quality eystem processes atd procedures Sr forte PIG*MICLs and aaPtOs BS, KerLoc ed Hoping Govces, Sena! EEPROMs, mevoperghers, ron/lle memory ard Snatg pout n acto Meron quay system or the design Sa manufacture of development systems is 80 8007 2000 cred 108701386-page 2 (© 2010 Merochip Technology Ine.Mc vee dsPIC30F3014/4013 High-Performance, 16-Bit Digital Signal Controllers This dala sheet summarizes features off this group of dsPIC3OF devices and is not intended to be @ complete reference ‘source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the "dsPICI0F Family Reference Manual" (0870046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Pro- ‘grammer's. Reference. Manual" (0870157), High-Performance Modified RISC CPU: + Modified Harvard Architecture + © Compiler Optimized Instruction Set Architecture + Flexible Addressing modes + 83 Base Instructions + 24-Bit Wide Instructions, 16-Bit Wide Data Path + Up to 48 Kbytes On-Chip Flash Program Space + 2Kbytes of On-Chip Data RAM + 1 Kbyte of Nonvolaile Data EEPROM + 16x 16-Bit Working Register Array + Up to 30 MIPS Operation: = DC to 40 MHz External Clock Input ~ 4 MHz-10 MHz Oscillator Input with PLL Active (4x, 8x, 16x) + Upto 33 Interrupt Sources: = [Link]-selectable priority levels = 3 external interrupt sources = 4 processor traps DSP Features: + Dual Data Fetch + Modulo and BitReversed modes + Two 40-Bit Wide Accumulators with Optional saturation Logic + 17-Bit x 17-Bit Single-Cycle Hardware Fractional/integer Multiplier + All DSP instructions are Single Cycle ~ Multiply-Accumulate (MAC) Operation + Single-Cycle £16 Shift Peripheral Features: + High-Current Sink/Source YO Pins: 25 mA/25 mA + Upto Five 16-Bit TimersiCounters; Optionally Pair up 16-Bit Timers into $2-Bit Timer modules + Up to Four 16-Bit Capture Input Functions + Up to Four 16-Bit Compare/PWM Output Functions + Data Converter Interface (DC!) Supports Common ‘Audio Codec Protacals, Including I°S and AC'S7 + 3-Wire SPI module (supports 4 Frame modes) + FC™ module Supports Multi Master/Slave mode and 7-Bit10-Bit Addressing + Up to Two Addressable UART modules with FIFO Buffers + CAN bus module Compliant with CAN 2.08, Standara Analog Feature: + 12-Bit Analog-to-Digital Converter (ADC) with = 200 ksps conversion rate = Upto 13 input channels = Conversion available during Sleep and Idle + Programmable Low-Voltage Detection (PLVD) + Programmable Brown-out Reset Special Microcontroller Features: + Enhanced Flash Program Memory = 10,000 orase/write cycle (min.) for industrial temperature range, 100K (typical) + Data EEPROM Memory ~ 100,000 erasefwte cycle (min. for industrial temperature range, 1M (typical) + Sel Reprogrammable under Software Control + Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Startup Timer (OST) + Flexible Watchdog Timer (WOT) with On-Chip Low-Power RC Oseilator for Relable Operation + Fail-Safe Clock Monitor Operation: = Detects clock failure and switches to on-chip low-power RC oscilator + Programmable Code Protection + In-Circit Serial Programming™ (I6SP™) + Selectable Power Management modes: ~ Sleep, ldle and Alternate Clock modes {© 2010 Mierachip Technology Ine 18701386-page 3dsPIC30F3014/4013 CMOS Technology: + Low-Power, High-Speed Flash Technology + Wide Operating Voltage Range (2.5V to 5.5V) + Industrial and Extended Temperature Ranges + Low-Power Consumption dsPIC30F3014/4013 Controller Fat ly covce [ine OMIM MEME seam EEPROM | tiner| input] WP | Coase [woz E |g Ez ytos|innirvcsone Bvt | Byles” | 1ebit ap | COP, |imertace n00Kepe | =| 2S wera [ao] aK | aKa] To | P| a TO ascaoraors [aoa] ax | vex [ae | toes) 8 «| 4 [acer PS| tae 2 3 Diagrams 40-Pin PDIP. EEE 5 Gh ano soveenonan sha ‘aoNecehns 3B sarae avasvprcnanss Ht SB Ato vascuenes He LB Avene Mivctene: i MB SNe vege 8 3B gscuci #s&8B EMUDI/SOSCI/TZCKIUIATICNTIRC'S Cis * 2B UIRXSDINSDARED ewer eran EB cueasouines redone SB enn te de EB ue in PDIP ‘gonmersenaea? SB ASicscxnes wsaitvonicnares He 2B amocconete aensrgs Hf SB Asoo, saulrenies HS SB Atiscorensts Metcwcwnes Hyg Sees roceyutianwoctunes qe SSB emisaocanot ‘anaes ie s sD vss vegs 8 spel ewososcurzacoraiwenncns = SB Ue Aee NeHSOSCOMICRN Saat Hi? 2B emuoascxines vodnai SB elmtusoy ocainos BS EB vo 08701386-page 4 (© 2010 Merochip Technology Ine.dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin TOFP YiSOSCOmTICKUTARKICNORC 2 2 |SOSCIT2CKIUTATICNTIRCTS SB 34 CLKOC fe aa KI euuoziocamo! =r 4 Zaft PCDEMUDANTRGT Euezioctmbo =a 25H PCCIEMUCIANGIOC>AES rm Ne antonio {© 2010 Mierochip Technology Ine. 18701386-page 5dsPIC30F3014/4013 Pin iagrams (Continued) 44-Pin QFN!) SSCOmTICKIUTARKICNOIRCY if ewupisoscrrzcKuraTaen mers rventarRes | 2 2 ueentrnee F3 st vss 5 dsPIC30F3014. 2 veo | 7 Zr ANSE veo f 6 25 | PobIeMUOVAN emuozocaro1 Js 5 i avrerare | a arensnas 422 0870138G-page 6 © 2010 Microchip Technology Ine.dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin TOFP SIRS? SE ANTSICSOORBN Sra 1 aR antoresouRat ‘ss it ANOIVREF+1CN2IRBO! {© 2010 Mierochip Technology Ine. 108701386-page 7dsPIC30F3014/4013 Pin Diagrams (Continued) 44-Pin QFN uireaonsonnee [1 s Uomccntonre PS n owes Ls dsPlcsorsots 22 vo Pe S| Pebemonvrna? sees: = ANiHics00 RBH Note 1: The meta plane at the botom ofthe dee i ot camecte os ns ss recommendes to be canected to Vs extemal 0870138G-page 8 © 2010 Microchip Technology Ine.dsPIC30F3014/4013 Table of Contents 1.0 Device Overviow " 20. CPU Architecture Overview. 15 3.0. Memory Organization 25 4.0 Address Generator Unis, a7 5.0 Flash Program Memory 3 50 Data EEPROM Memory 4 70 WO Pons 53 2.0 Interupte 59 8.0 Timert Module 87 10.0 Timer2/3 Module n 11.0. Timerd5 Module 7 12.0 Input Capture Module at 13.0 Output Compare Module. 85 140 126% Module et 15.0 SPIModule. 99 16.9. Universal Asynchronous Recelver Transmitter (UART) Module ‘03 17.0 CAN Module. m 480 Data Converter Interface (OCi) Module 121 180. 12-bit Analog-to-Digtal Converter (ADC) Module 131 20.0. System Integration 1a 21.0 Inetruction Set Summary. 189 22.0. Development Support 17 230 Electrical Characteristics m 24.9. Packaging Information at Index 219 The Microchip Wed Site. 225 Customer Change Notification Service 225 Customer Support 228 Reader Response 205 Product Mentieation System er TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensue sucessful use of your Microchip produits. To this end, we wil continue to improve our publeatone fo etter suit your needs, Our publications wil be refined and [enhanced as new volumes and updates are introduced Ifyou have any questions ar comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@[Link] or fax the Reader Response Form inthe back ofthis data shest lo (480) 792-4150. We welcome your feedback, Most Current Data Sheet Ta obtain the most up-o-ca [Link] version ofthis data sheet, please register at cur Worldwide Web sit at: You can detormine the version of a data shoet by examining Is Iteature number found on the bottom outside comer of any page. The last character ofthe Iierature number isthe varsion number, (2.9, OS30000A is version A of document DS30000), Errata [An erata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devies, As doviceldocumentation sues become known t0 Us, we wil publsh an erata sheet, The errata will spect the revision of ‘silcon and revision of dacument to which it apples, To determine fan erata sheotexss fora parcular device, please check with one ofthe folowing + Microchip's Wortdwide Web site; htp:l'[Link] + Your local Microchp sale office (se9 lst page) ‘when contacting a sales ofc, please speciy which device, revision of silicon and data sheet (inch Irature number) you a using Customer Notification System Rogistor on ourwob sie at [Link] to recov the most curont information onal of our products {© 2010 Mierochip Technology Ine. 108701386-page 9dsPIC30F3014/4013 NOTES: 10870138G-page 10 {© 2010 Microchip Technology Ine.dsPIC30F3014/4013 1.0 Note: DEVICE OVERVIEW This data sheet summarizes features off this group of dsPIC3OF devices and is not intended to be @ complete reference ‘source, For more information on the CPU, peripherals, register descriptions and {general device functionality, refer to the “dsPIC30F Family Reference Manual" (0870046). For more information on the device instruction set and programming, rafer to the “16-bit MCU and DSC Pro- ‘grammer's. Reference. — Manual" (0870157), This document contains specific information for the ‘dsPIC30F3014/4013 Digital Signal Controller (OSC) devices. The dsPIC30F3014/4013 devices contain ‘extensive Digital Signal Processor (DSP) functionality within @ high-performance, 16-bit_microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and is always clear. W165 is inialzed to Ox0800 during @ Reset. The user may reprogram the SP during iniialzation to any location within data space. W14 has been dedicated as a Stack Frame Pointer, as defined by the 11K and ULNK instructions, However, W14 can be referenced by any instruction in the same manner as all other W registers 222 STATUSREGISTER The dsPIC DSC core has a 16-bit STATUS register (SR), the Least Significant Byte (LSB) of which is referred to as the SR Low byte (SRL) and the Most Significant Byte (MSB) as the SR High byte (SRH), See Figure 2-1 for SR layout. ‘SRL contains all the MCU ALU operation status flags (including the Z bit), as well as the CPU Interrupt Prior ity Level Status bits, IPL<2:0> and the Repeat Active Status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a ‘complete word value which is then stacked. ‘The upper byte of the STATUS register contains the DSP adder/subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (OC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is aways clear, Therefore, the PC can address up to 4M instruction words, 10870138G-page 16 (© 2010 Merochip Technology Ine.dsPIC30F3014/4013 FIGURE 2-1: PROGRAMMER’S MODEL ots WOWREG DSP Operand we Rogistors, Working Registers we 19 Reg we DSP Address Registers wi) wit Wi2i0SP Ofset WiaDSP wre Back WidiFrame Pointer WisiStack Pointer ‘SPL ‘Stack Pointer Limit Register A039 A031 ADIs D0 Reo sp “Acc ‘Accumulators poze Poo 2] Program Counter TBLPAG, Data Tablo Pago Addross PSVPAG Program Space Visibilty Page Addross 6 © RCOUNT [Link] Loop Counter 16 o DCOUNT bo Loop Counter 22 ° DOSTART bo Loop Start Adress 2 DOEND bo Loop End Aderess CORCON Core Configuration Register ‘OA [08 | SA] $8 [OAS] SAB] DA [00 JiPLZ PLITIPLO] RAN | OV STATUS Register << s§ > 1© 2010 Mierochip Technology Ine. 0870138¢-page 17dsPIC30F3014/4013 23 Divide Support ‘The dsPIC DSC devices feature a 16/76-bit signed fractional divide operation, as well as 32/16-bit and 16/ ‘-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 4. DIvP— 16/16 signed fractional divide 2, DIV, sd~ 92/16 signed divide 3, [Link] ~ 92/16 unsigned divide 4. DIV.s~ 16)16 signed divide 5, DIV.u~ 16/76 unsigned divide ‘The 16/16 divides are similar to the 32/16 (same number of iterations), but the dividend is either zero-extended or sigrrextended during the first iteration The divide instructions must be executed within a REPEAT loop. Any other form of execution (2.9., & series of discrete divide instructions) will not function correctly because the instruction flow depends on COUNT. The divide instruction does not automatically set up the RCOUNT value and it must, therefore, be explicitly and correctly specified in the R=P=xT instruc tion, as shown in Table 2-1 (REPEAT will execute the target instruction (operand value+t} times). The REPEAT loop count must be setup for 18 iterations of the DIv/D1VE instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow i Interruptible. However, the user needs to save the context as appropriate. TABLE 2. DIVIDE INSTRUCTIONS Instruction | Function TE ‘Signed fractional divide: WmiWn —> WO; Rem — W1 DIV ad ‘Signed divide: (Wm-+1:Wmy/Wn —> WO; Rem > W1 DIV.s [Signed divide: Wm/Wn — WO; Rem —> Wi DIV ad Unsigned divide: (Wm+1:Wmy/Wn > WO; Rem -> Wi pIv.w [Unsigned divide: WmiWn > WO; Rem > Wt 10870138G-page 18 (© 2010 Merochip Technology Ine.dsPIC30F3014/4013 24 DSP Engine The DSP engine consists of a high-speed, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder! subiracter (with two target accumulators, round and saturation logic) The DSP engine also has the capabilly to perform inherent accumulator-to-accumulator operations, ‘which require no additional data. These instructions are ADD, SUB and NEG The dsPIC3OF is a single-cycle instruction flow arch tecture, therefore, concurrent operation of the OSP. engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources may be used concurrently by the same instruction (e.g, 1, BDAC), (See Table 2-2 for DSP instructions.) ‘The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multioly (IF) ‘Signed oF unsigned DSP multiply (US). Conventional or convergent rounding (RND). ‘Automatic saturation on/off for AccA (SATA). ‘Automatic saturation on/off for AceB (SATB). Automatic saturation onvoff for writes to data ‘memory (SATDW), 7. Accumulator Saturation mode selection (acesar}. Note: For CORCON layout, see Table 33. A Block diagram of the DSP engine Is shown in Figure 2-2 TABLE 22: DSP INSTRUCTION SUMMARY Instruction | Algebraic | acc wer [CLR i A=0 Yes ED A= t-yP No [ppac [a=4-@-y No ac A= Avery) | Yes [wac [azar No NOVERE No change in [Yes [wer | aexty No Mer aaay No [ys [ananx, Yes 1© 2010 Mierochip Technology Ine. 0 70138¢-page 19dsPIC30F3014/4013 FIGURE22: __DSP ENGINE BLOCK DIAGRAM s “0 ES GOB RecamuarA 40 | round) 8 r- ats hemi ound ___ 7 bogie canyioTaH Out : __ / Carry/Borrow In. { Adder \ Z /N \ eae fo feo (i ~ Barrel _J”) shiter 78 XY 40 3 4| Sign Extend g A / a g 2 ‘6 é Zero Backfill | > 2 33, 3 ‘7a MutiperScater r fis hte 4 TorFrom Waray 10870138G-page 20 {© 2010 Microchip Technology Ine.dsPIC30F3014/4013 244 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or Unsigned operation and can multiplex ts output using a scaler to support elther 1.31 fractional (31) or 32-bit, integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed ‘operands are sign-extended into the 17th bit of the ‘multiplier input value. The output of the 17-bit x 17-bit, ‘mutipier/scaler is @ 33-bit value, which is sign- extended to 40 bits. Integer data is inherently represented as a signed two's complement value, where the MSB is defined as a sign bit. Generally speaking, the range of an N-bit two's complement inte- ger is 2°"! to 2°"! - 1. For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (Ox7FFF) including ‘For a 32-bit integer, the data range is - 2,147,483,648 (0x8000 0000) to 2,147,483,645 (Ox7FFF FFFF), ‘When the multiplier is configured for fractional multit- cation, the data is represented as a two's complement {raction, where the MSB is defined as a sign bit and the radix pointis implied to ie just after the sign bit (QX for mat). The range of an N-bit two's complement fraction with this implied radix point is -1.0 to (1 - 2"), For a 1G-it fraction, the Q15 data range Is -1.0 (0x8000) to 0.999960482 (0x7FFF) including ‘0’ and has a prec sion of 3.01518x10". In Fractional mode, the 16x16 multiply operation generates a 1.31 product, which has a precision of 4.65661 x 10", The same multiplier is used to support the MCU mul ply instructions, which includes integer 16-bit signed, Unsigned and mixed sign multiplies. The wun instruction can be directed to use byte or word-sized operands. Byte operands direct a 16-bit result, and word operands direct a 32-bit result to the specified register(s) in the W array. 2.42 DATAACCUMULATORS AND ADDER/SUBTRACTER. The data accumulator consists of a 40-bit adder! subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its pre- accumulation source and —_post-accumulation destination, For the ADD and Lac instructions, the data to be accumulated or loaded can be optionally scaled Via the barrel shitter prior to accumulation. [Link] Adder/Subtracter, Overflow and Saturation ‘The adder/subtracter is a 40-bit adder with an optional zer0 input into one side and either true or complement, data into the other input. In the case of addition, the carryiborrow input is active-high and the other input is true data (not complemented), whereas in the case of subtraction, the carrylporrew input is active-low and the ‘other input is complemented. The adder/subtracter generates overflow Status bits, SSB and OA‘OB, Which are latched and reflected in the STATUS register: Overflow from bit 39: this is @ catastrophic ‘overflow in which the sigh of the accumulator is destroyed, Overflow into guard bits 32 through 38: this is a recoverable overflow. Ths bit is set whenever all the guard bits are not identical to each other. ‘The adder has an additional saturation block which controls accumulator data saturation ifselected, uses the result of the adder, the overflow Stalus bits described above, and the SATA/B (CORCON«7:6>) ‘and ACCSAT (CORCON<4>) mode control bits to determine when and to what value to saturate ‘Sik STATUS register bits have been provided to ‘support saturation and overflow. They are: 1. On: Acc overflowed into guard bits 2. 0B: ‘AceB overflowed into guard bits 3. SA Acc saturated (bit 31 overflow and saturation) or AccA overflowed into guard bits and saturated (bit 39 overfiow and saturation) 4. $B: ‘AccB saturated (bit 31 overflow and saturation) AccB overflowed into guard bits and saturated (bit 39 overflow and saturation) 5, OAB: Logical OR of OA and OB 6 SAB: Logical OR of SA and SB The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (oits 32 through 39). ‘The OA and OB bits can also optionally generate an arithmetic warning trap when set and the correspond- ing overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 8.0 “Inter- rupts”) is set, This allows the user to take immediate action, for example, to correct system gain. {© 2010 Mierochip Technology Ine. 08701886-page 21dsPIC30F3014/4013 ‘The SA and SB bits are modified each time data passes through the adderisubtracter but can only be Cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 ‘or 32-bit saturation orbit 39 for 40-bit saturation) and will be saturated if saturation is enabled, When saturation is not enabled, SA and SB default to bit 39, ‘overflow and, thus, indicate that a catastrophic over flow has occurred. If the COVTE bit in the INTCONt register is set, SA and SB bits generate an arithmetic, warning trap when saturation is disabled. ‘The overflow and saturation Status bits can optionally be viewed in the STATUS register (SR) as the logical ‘OR of OA and OB (in bit OAB) and the logical OR of SA, ‘and SB (in bit SAB), This allows programmers to check. fone bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This would be useful for complex number arithmetic which typically uses both the accumulators. The device supports three saturation and overfow modes: 1, Bit 39 Overtow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positve 9.31 (Ox7FFFFFFFFF), or maximally negative 9.31 value (08000000000) into the target accumula- lor. The SA or SB bitis set and remains set unt eared by the user. This is refered to as ‘super saturation’ and provides protection against erro- neous data or unexpected algorithm problems (@3g., gain calculations). 2. Bit31 Overflow and Saturation: When bit 31 overfiow and saturation occurs, the saturation logic then loads the maximally posi- tive 1.31 value (0x007FFFFFFF), or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set unl cleared by the user, When this Saturation mode is in effect, the guard bits are not used, £0 the OA, OB or OAB bits are never set 3. Bit39 Catastrophic Overtiow: The bit 39 overflow Status bit from the adder is Used fo set the SA or $B bit which remain set Until cleared by the user. No saturation operation is performed and the accumulator is alowed to overflow (destroying its sign. Ifthe COVTE bitin the INTCONt register is set, @ catastrophic overflow can inate a trap exception. [Link] Accumulator Write-Back’ The »21c class of instructions (with the exception of MPY, MPY.N, =D and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of he accumulator that isnot argeted by the instruction into data space memory. The writes performed across, the X bus into combined X and Y address space, The following addressing modes are supported: 1. W13, Register Direct: The rounded contents of the nontarget accumulator are written into W13 as a 4.18 fraction 2. W13}+=2, Register Indirect with Post-Increment: ‘The rounded contents ofthe non-target accumu- lator are writen into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). [Link] Round Logic ‘The round logic is @ combinational block which performs. ‘a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round ‘mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value, which is passed to the data space write saturation logic. IFrounding s not indicated by the instruction, a truncated 41.15 data value is stored and the least significant word (sw) is simply discarded. Conventional rounding takes bit 15 of the accumulator, zero-extends it and adds it to the ACCxH word (bits 16 through 31 of the accumulator). If the ACCxL word (bits 0 through 15 of the accumulator) is between (0x8000 and OxFFFF (0x8000 included), ACC#H is incremented. I ACCxL is between 0x0000 and Ox7FFF, ACCxH is let unchanged. A consequence of this algo- rithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the ‘Same manner as conventional rounding, excapt when ACCxL equals [Link] isthe case, the Least Sig- nificant bit (Lb) (bit 16 of the accumulator) of ACCxH is examined, itis :', ACCxH is incremented, itis ‘0 ACCxH ig not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate, The SAC and sac. instructions store elther a trun- cated (sic) oF rounded (sac.R) version ofthe contents of the target accumulator to data memary via the X bus. (subject to data saturation, see Section [Link] “Data, ‘Space Write Saturation”). Note that for the MAC class. of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this, class of instructions, the data is always subject to rounding 10870138G-page 22 (© 2010 Merochip Technology Ine.dsPIC30F3014/4013 [Link] Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16+it, 1.15 fractional value from the round logic block as its Input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. Ifthe SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly. For input data greater than OXOO7FFF, data writen to memory is forced to the maximum positive 1.18 value, Ox7FFF, For input data less than OxFFB000, data written to memory is forced to the maximum negative 1.18 value, 0x8000. The ‘Most Significant bit (MSb) ofthe source (bit 39) is used to determine the sign of the operand being tested. Ifthe SATOW bitin the CORCON register isnot set, the input data is aways passed through unmodified under all conditions. 24.3 BARREL SHIFTER The barrel shitter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators, or the X ous (to support multi-bit shifts of register or memory data). ‘The shifter requires a signed binary value to determine both the magnitude (number of bts) and direction of the shift operation. A postive value shifts the operand right ‘A negative value shifts tne operand left. A value of ‘0 does not modify the operand. ‘The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is, presented to the barrel shifter between bit positions 16 to 31 for right shifts, and bit positions 0 to 16 for left shits, {© 2010 Mierochip Technology Ine. 108 701386-page 23dsPIC30F3014/4013 NOTES: 10870138G-page 24 {© 2010 Microchip Technology Ine.dsPIC30F3014/4013 3.0 MEMORY ORGANIZATION This data sheet summarizes features off this group of dsPIC30F devices and is not intended to be @ complete reference ‘source, For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the ‘dsPIC3OF Family Reference Manual User program space access is restricted to the lower 4M. instruction word address range (0x000000 to OX7FFFFE) for all accesses other than Ti5LRD/ LW Which use TBLPAG<7> to determine user or configura: tion space access. In Table 3-1, bit 2 allows access to the Device ID, the User ID and the Configuration bits, ‘otherwise, bit 23 is always clear. FIGURE 3.2: dsPIC30F4013 PROGRAM Given necucon sot and Programming, SPACE MEMORY MAP reer to the “16-bl MCU and DSC Pro: oon grammer's Reference Manual") eset = Target Adaress ——] 000002 (070157). |o00004 3.1 Program Address Space cooore | The program address space ie 4M instruction words. Reena ote | is addressable by 2 2b value rom ether the 23- conse |B PG, table mstructon Effective Address (EA) or data 3, | | monte vc toe Space EA, when program space 's mapped into data if coor space as defined by Table 2-1. Note that te program 3° oot space adaress is incementod by two between succes- 3 User Fn tive program words In order to provide compattity raganWeroy with data space addressing. (6K structions) corre FIGURE 34: dsPIC30F2014 PROGRAM == ‘SPACE MEMORY MAP_ " eae re ost: Reserved }000080 | 5 soose . ‘Mena Vet Tale 3 uum seit) | cape it eoore5 2. s00800 33 1 Flash 5a evened }004000 8 bee rn Tavis Cogaaion — roma eons (Key) Reena cos ceva me : UND zt) i eoxsre e er Recen _[eanooe 3 Feore rene evo oat {© 2010 Mierochip Technology Ine. 108 70138¢-page 25dsPIC30F3014/4013 TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION ‘Access Program Space Address ‘Access Typo yp Space a> | eate> [ | <> Instruction Access User ° PG<221> a BLRD/TBLAT User TBLPAG<7:0> Data EAC15:0> (TALPAG<7> = 0) TOLRD/TBLNT Configuration TBLPAG<7:0> Data EAZ15:0> (TBLPAGE7> = 2) Program Space Visibity [User 2 PSVPAG&7:0> Data EACT&:0> FIGURE 3-3: DATA AGCESS FROM PROGRAM SPACE ADDRESS GENERATION ' 23 bits ' Using i ~ Program = [a] Program Counter Te Counter i | ' I i Select x Using t a Program [>| PSVPAG Reg Space J Visibiity apis rie S bits - \ \ 1 it I I Using j z Using i/o] TBLPAG Reg i Instruction Sis 1 “ébits I V1 / user A | 1 4 Configuration | Byt 2Abit EA ye Space \ ‘ Select Select Note: Program space visibility cannot be used to access bits<23:16> ofa word in program memory. 10870138G-page 26 © 2010 Microchip Technology Ine.dsPIC30F3014/4013 3.1.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS, This architecture fetches 24-bit wide program memory. Consequently, Instructions are always aligned. However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, of through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2 "Data Access from Program Memory Using Program Space Visibility”). The TELRDL and TBLi7L instruc tions offer a direct method of reading or writing the Isw of any address within program space, without going through data space. The 7SLRDE and TELWTH instruc- tions are the only method whereby the upper 8 bits of program space word can be accessed as data, The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word-wide address spaces, residing side by side, each with the same address range. 7SLRDL, and TSLWTL access the space which contains the least significa data word, and 72LRD# and T2LWTH access the space which contains the MS Data Byte. Figure 3-3 shows how the EA is created for table oper- ations and daia space accesses (PSV = 1). Here, P<23:0> refers to @ program space word, whereas D<15:0> refers to a data space word, AA set of table instructions are provided to move byte or word-sized data to and from program space, (See Figure 3-4 and Figure 3-5.) 1. TSLRDL: Table Read Low Word: Read the Isw of the program address; P<15:0> maps to D<15:0>. Byte: Read one of the LSBs of the program address: P<7:0> maps to the destination byte when byte select = 0; P<15:8> maps to the destination byte when byte select = 2. TaLWTL: Table Write Low (refer to Section 5.0 “Flash Program Memory” for details on Flash programming) 3. TRLRDH: Table Read High Word: Read the most significant word (msw) of the program address; P<23:16> maps to D<7:0>; D<18:8> will always be = 0. Byte: Read one of the MSBs of the program address: P<23:16> maps to the destination byte when byte select = 0; The destination byte will always be = 0 when byte select = 1 4. TBLasi: Table Write High (refer to Section 5.0 “Flash Program Memory” for details on Flash Programming) FIGURE 34: _ PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD) PC Address 2 8 0 000000 [E=BaoBDeD 0.000002 | -eo0w00e oxo0000¢ [09000000 oxo0000s 499000000 x Program Memory Phantom’ Byte (read as‘) ‘ BLRDL.B (Wn<0> ~ 0 TBIRDL.B (WncO> = 1) {© 2010 Mierochip Technology Ine. 0870138¢-page 27dsPIC30F3014/4013 FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) BLE PC Adress 2 16 8 ° 000000 [ipananaoer 000002 [~ 0000000 xo0000s [grpoogouon: oncoone JE soO NEE m Program Memory Phantom’ Byte (read as‘0’) TBLRDA.B ineo> = 1) 3.1.2 DATAACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY ‘The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page. This provides transparent access of stored constant data, from X data space without the need to use special Instructions (Le., 7SLRD:/E, 7BLINT/# instructions). Program space access through the data space occurs if the MSb of the data space, EA, is set and program ‘space visibility is enabled by setting the PSV bitin the Core Control register (CORCON). The functions of CORON are discussed in Section 2.4 “DSP Engine”. Data accesses to this area add an additional cycle to the instruction being executed, since two program ‘memory fetches are required Note that the upper hatf of addressable data space is ‘always part of the X data space. Therefore, when a DSP operation uses program space mapping to access this memory region, ¥ data space should typically con- tain state (variable) data for DSP operations, whereas. X data space should typically contain coefficient (constant) data, ‘Although each data space address, 0x8000 and higher, maps directly into @ corresponding program memory address (see Figure 3-6), only the lower 16 bits of the 24-bit program word are used to contain the data. The Upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “[Link] MCU and DSC Programmer's Reference ‘Manuat" (0S70187) for details on instruction encoding NNote that by incrementing the PC by 2 for each program memory word, the 15 LSbs of data space addresses directly map to the 15 LSbs in the corre- sponding program space addresses. The remaining bits are provided by the Program Space Visiilty Page register, PSVPAG«7:0>, as shown in Figure 3-6, PSV access is temporarily disabled during table readsiwrites, For instructions that use PSV which are executed outside @ REPEAT loop: + The following instructions require one instruction cycle in addition to the specified execution time: ~ NAC class of instructions with data operand prefetch = Nov instructions = Nov. D instructions + All other instructions require two instruction cycles in adcition to the specified execution time of the instruction For instructions that use PSV which are executed inside a REPEAT loop. + The following instances require two instruction ‘cles in addition to the specified execution time of the instruction: = Execution in the first iteration = Execution in the last iteration = Execution prior to exiting the loop due to an interrupt ~ Execution upon re-entering the loop after an interuptis serviced + Any other iteration ofthe R=PEAT loop allows the instruction accessing data, using PSV, to execute ina single cycle. 10870138G-page 28 (© 2010 Merochip Technology Ine.dsPIC30F3014/4013 FIGURE 3-6: _DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space Program Space 10000 000100 ' 45 psveact” ' EAcis>=0 Cor) | 5 \ i 18000 ee naarss oI a pans ' Unper Hal of Data | Space i Mapped «| —— into Program Space \ osFeFr oxoo7rr ¥0x00, "x0 ox8200, Data Read Note: PSVPAG is an &-bit register, containing bts<22:15> of the program space address (i... it defines the page in program space to which the upper half of data space is being mapped). ‘The memory map shown here Is for a dsPIC30F4013 device 1© 2010 Mierochip Technology Ine. 108 70138¢-page 29dsPIC30F3014/4013 32 Data Address Space ‘The core has two data spaces, The data spaces can be ‘considered either separate (for some DSP instructions), ‘ras one unified linear address range (for MCU instruc tions). The data spaces are accessed using two Address, Generation Units (AGUs) and separate data paths 3.2.1 DATA SPACE MEMORY MAP The data space memory is splt into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent Linear ‘Addressing space, X and Y spaces have contiguous addresses. When executing any instructon other than one of the tn class of instructions, the X block consis of the 64-Kbyte data address space (Including all Y addresses). When executing one of the 4c dass of instructions, the X block consists of the 64-Kbyte data address space ‘excluding the Y address block (for data reads only) In ‘ther words, all other instructions regard the entice data memory as one composite address space. The Mac class instructions extract the ¥ address space from data Space and address it using EAS sourced from W10 and W11. The remaining X data space is addressed using W8 ‘and WS. Both address spaces are concurrently accessed only with the sac class instructions. The data space memory map is shown in Figure 3-7, FIGURE 3-7: __dsPIC20F2014/dsPIC30F4013 DATA SPACE MEMORY MAP MsB LsB Minvss 18 ts Adress Se SE Te 010001 0000 ~ 2K SFR Space SFR Space Ox07FF OxO7FE = prose 0800 x Data RAM axons axoyte | Ox0BFF ovaare Nee 2k | Sent os0c00 ba pace Y Data RAM (Y) L oorer oxoere oxso0t oxto00 ore one croxsoot fT 0x8000, ptinaty Mapped Unimplemeted I Prog emery Ox FFF OxFFFE 10870138G-page 20 {© 2010 Microchip Technology Ine.dsPIC30F3014/4013 FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE I 1] SFR SPACE . I I Qo | UNUSED | = I I * (space) wo Y SPACE uNuseo 8 & x \ \ \ ' w | unuseo g I ! o I \ * I I Non-inc Class Ops (Read/Write) un Class Ops (Read) unc Class Ops (Write) Indirect EA using any W Indirect EA using W8, W® Indirect EA using W10, Wt 1010 Mlerachip Technology Ine. s70138¢-page 31dsPIC30F3014/4013 3.22 DATASPACES The X data space is used by all instructions and sup- ports all addressing modes, There are separate read ‘and write data buses. The X read data bus is the return data path for all instructions that view data space as, ‘combined X and Y address space. It is also the X address space data path for the dual operand read instructions (vac class). The X write data bus is the only write path to data space forall instructions. ‘The X data space also supports Modulo Addressing for all instructions, subject to addressing mode restric~ tions. BitReversed Addressing is only supported for rites to X data space, ‘The Y data space is used in concert with the X data, space by the MAC class of instructions (CLR, ED, EDAG, MAC, MOVSAC, MPY, MPY.N and WSC) to provide two ‘concurrent data read paths. No writes ‘occur across the Y bus. This class of instructions dedi- cates two W register pointers, WW10 and W11, to always, address Y data space, independent of X data space, Whereas W8 and W9 always address X data space. Note that during accumulator wrte-back, the data ‘address space is considered a combination of X and Y data spaces, so the write occurs across the X bus. Consequently, the write can be to any address in the entire data space. The Y data space can only be used for the data prefetch operation associated with the wAc class of instructions. It also supports Modulo Addressing for automated circular buffers. OF course, all other instruc- tions can access the Y data address space through the X data path as part of the composite linear space. ‘The boundary between the X and Y data spaces is defined as shown in Figure 3-7 and is not user programmable. Should an EA point to data outside its ‘own assigned address space, or to a location outside physical memory, an all zero wordlbyte is returned, For ‘example, although Y address space is visible by all nnon-vAc instructions using any addressing mode, an attempt by a MAC instruction to fetch data from that space using W8 or W9 (X Space Pointers) retums 0x0000, TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES Attempted Operation Data Returned EA=[Link] address | Ox0000 W8 or W9 used to access Y data | 0x0000 space in a MAC instruction W10 or Wt used to access X 0x0000 data space in a NAC instruction Al effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words, 3.23 DATASPACE WIDTH The core data width is 16 bits. All internal registers are organized as 16-bit wide words. Data space memory is organized in byte addressable, 16-bit wide blocks. 3.24 DATAALIGNMENT To help maintain backward compatbilty with PIC® MCU devices and improve data space memory usage efficiency, the dsPIC3OF instruction set supports bath word and byte operations. Data is aligned in data mem- ory and registers as words, but all data space EAS resolve to bytes. Data byte reads read the complete ‘word which contains the byt, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the X data path (no byte Accasses ate possible from the ¥ data pathas the NAc class of instruction can only fetch words). That i, data memory and registers are organized as two parallel byle-wide entities witn shared (word) address decode bit separate write lines. Data byte writes only wrt to the corresponding side ofthe array or rogister which matches the byte address. ‘Asa consequence ofthis byte accessibility, al effective address calculations (Including those generated by the DSP operations which are restricted to word-sized data) are internally scaled to step through word-aligned memory. For example, the core would recognize that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte ‘operations and Ws + 2 for word operations, All word accesses must be aligned to an even address. Misaligned word data fetches are not supported so ccare must be taken when mixing byte and word ‘operations, or translating from 8-bit MCU code. Should ‘a misaligned read or write be attempted, an address. error trap is generated, Ifthe error occurred on a read, the instruction underway is completed, whereas If it ‘occurred on a write, the instruction is executed but the ‘write does not occur. In either case, a trap is then exe- cuted, allowing the system and/or user to examine the machine state prior to execution ofthe address Faull, FIGURE 3-9: DATA ALIGNMENT 1 SB og, LSB Og 0001 [Byte t Byteo |] 0000 0003 | Bytes Byte2 | 0002 00s |_ Bytes Byte4 | 0004 10870138G-page 32 (© 2010 Merochip Technology Ine.dsPIC30F3014/4013 Al byte loads into any W register are loaded into the LSB, The MSB is not modified, A Sign-Extend (sz) instruction is provided to allow users to transiate &-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a Zero-Extend (8) instruction on the appropriate address, ‘Athough most instructions are capable of operating on ‘word or byte data sizes, it should be noted that some Instructions, including the DSP instructions, operate only on words. 3.25 NEAR DATA SPACE ‘An 8-Kbyte ‘near’ data space is reserved in X address ‘memory space between 0x0000 and Ox1 FFF, which is directly addressable via a 13-bit absolute address field within all memory direct instructions, The remaining X address space and all of the Y address space is addressable indirectly. Additionally the whole of X data space is addressable using “ov instructions, which support memory direct addressing with @ 16-bit address field 3.2.6 SOFTWARE STACK The dsPIC DSC devices contain a software stack. W15 is used as the Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower addresses towards higher addresses. It pre-decrements for stack pops and [Link] for stack pushes as shown in Figure 3-10, Note that for a PC push during any CALL instruction, the MSB of the PC Is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing cconcatenates the SRL register to the MSB of the PC prior to the push. ‘There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer, SPLIM is uninitialized at Reset. As isthe case for the Stack Pointer, SPLIM is forced to '0’ because all stack operations must be word-aligned. Whenever an Effective Address (EA) is, generated, using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM. Ifthe contents ofthe Stack Pointer (W15) and the SPLIM register are equal and a push ‘operation is performed, a stack error trap does not ‘occur. The stack error trap occurs on a subsequent push operation. Thus, for example, if it is desirable to ‘cause a stack error trap when the stack grows beyond, ‘address 0x2000 in RAM, initialize the SPLIM with the value, OXIFFE. Similarly, a Stack Pointer underflow (stack error) trap is {generated when the Stack Pointer address is found to be less than 0x0800, thus preventing the stack from interfering with the Special Function Register (SFR) space, ‘Avwrite to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 3-10: CALL STACK FRAME 030000 45 ° POSTEO ]-- wis (below cans) ioeeano] PET | Free Wore tia wis (ator cn g 6. {© 2010 Mierochip Technology Ine. 08 70138¢-page 33dsPIC30F3014/4013 aa EEE ESE ie re oT SSE ss (AV UBLSIOIN HOD —“e-2 TTAVL © 2010 Microchip Technology Ine. 08701986-page 34dsPIC30F3014/4013 sto fo suoyduo89p 10} (@roaus) Jen (GaNNIINOD) ydVW WSLSIOIN TUOD EE TVA 10870138G-page 25 © 2010 Microchip Technology Ine.dsPIC30F3014/4013 NOTES: 10870138G-page 26 {© 2010 Microchip Technology Ine.dsPIC30F3014/4013 4.0 ADDRESS GENERATOR UNITS This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source, For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual" (0870046). For more information on the device instruction set and programming, refer to the “16-bit MCU and DSC Pro. grammers Reference. Manual" (0870157), The dsPIC DSC core contains two independent address generator units: the X AGU and Y AGU. The Y AGU supports word-sized data reads for the DSP Mac lass of instructions only. The dsPIC DSC AGUs support three types of data addressing + Linear Addressing + Modulo (Circular) Addressing + BitReversed Addressing Linear and Modulo Data Addressing modes can be applied to data space or program space. BitReversed ‘Addressing is only applicable to data space addresses, 4.1 Instruction Addressing Modes The addressing modes in Table 4-1 form the basis of the addressing modes optimized to support the specific features of individual instructions, The addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types. TABLE 4-1: 44.4 FILE REGISTER INSTRUCTIONS. Most file register instructions use a 13-bit address field () to directly address data present in the first 18192 bytes of data memory (near data space). Most file register instructions employ a working register, WO, which is denoted as WREG in these instructions, The destination is typically either the same file register or WREG (with the exception of the Mul. instruction), hich writes the result to a register or register pair. The MOY instruction allows additional flexibiity and can ‘access the entire data space during file register ‘operation, 4.1.2 MCU INSTRUCTIONS ‘The three-operand MCU instructions are ofthe form: Operand 3 = Operand 1 Operand 2 where Operand 1 is always a working register (ie., the ‘addressing mode can only be Register Direct), whichis, referred to as Wb, Operand 2 can be a W register, fotched from data memory ot a 6-bit Iteral, The result location can be either a W register or an address location. The following addressing modes are ‘supported by MCU instructions: + Register Direct + Register Indirect + Register Indirect Post-Moditied + Register Indirect Pre-Modifiea + S:bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes, FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct [The address of the File register is speciied explicit. Register Direct The contents ofa register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post Modified Register Indirect Pre-Modified to form the EA, The contents of Won forms the EA. Wn is post-modified (incremented or |decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value Register Indirect with Register Offset [The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset [The sum of Wn and a literal forms the EA, {© 2010 Mierochip Technology Ine. 0870138¢-page 37dsPIC30F3014/4013 41.3. MOVE AND ACCUMULATOR INSTRUCTIONS, Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibilty than other instructions, In addition to the ‘addressing modes supported by most MCU instruc tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode, For the Mov instustions, the addressing ‘mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (register offset) field is shared between both source and destination (out typically only used by one). In summary, the following addressing modes are supported by move and accumulator instructions: + Register Direct, + Register Indirect + Register Indirect Post-Modified + Register Indirect Pre-Modified + Register Indirect with Register Offsat (Indexed) + Register Indirect with Literal Offset + Bit Literal + 16-bit Literal Note: Not all instructions support all_ the: addressing modes given above, Individual instructions may support different subsets of these adaressing modes, 4.1.4 wac INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, BDAC, NAC, MPY, MEY.N, MOVSAC and Sc), also roferrad [Link] Mac instructions, utlize a simplified set of addressing modes to allow the user to effectively ‘manipulate the Data Pointers through register indirect, tables, The two source operand prefetch registers must be a member of the set (WS, W9, W10, W'1}. For data, reads, W8 and WS is always directed to the X RAGU, ‘and W10 and W1t are always directed to the Y AGU. The Effective Addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 ‘and WI Note: Register Indirect wih Register offset addressing is only available for WS (in X| space) and WI (In Y space). In summary, the following addressing modes are supported by the tinc class of instructions: + Register Indirect + Register Indirect Post-Modifed by 2 + Register Indirect Post-Moditfied by 4 + Register Indirect Post-Maaiied by + Register Indirect with Register Ofset (Indexed) 4.1.8 OTHER INSTRUCTIONS Besides the various addressing modes outlined above, some instructions use Iteral constants of various sizes, For example, BRA (branch) instructions use 16-bit signed iterals to speci the branch destination directly, whereas the DTS? instruction uses a 14-bit unsigned literal fiald, In some instructions, such as ADD Ace, the source of an operand ar results implied by the opcode itself. Certain operations, such as No?, do not have any operands. 4.2 Modulo Addressing Modulo Addressing is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks: ‘when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can bbe supported in each of the X (which also provides the: pointers into program space) and Y dala spaces. Modulo Addressing can operate on any W register pointer. However, tis not advisable to use W'14 or W15, for Modulo Addressing since these two registers are Used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can only be configured to operate in one directon, as there are certain restrictions on the buffer start address (for incre menting buffers), or end address (for decrementing buffers) based upon the direction ofthe buffer, The only exception to the usage restrictions is for buffers that have a power-of-2 longth. As these buffers, satisfy the start and end address criteria, they may ‘operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries), 10870138G-page 28 (© 2010 Merochip Technology Ine.