DALLAS 402-+&=S SEMICONDUCTOR DS1287 Real Time Clock a FEATURES «© Drop-in replacement for IBM AT computer clock/ca~ Tendar ‘* Pin compatible with the MC146818A «* Totally nonvolatile with over 10 yéars of operation in the absence of power ¢ Setf-contained subsystem includes lithium, quar, land support circuitry ‘* Counts seconds, minutes, hours, days, day of the week, data, month, and year with leap year compan sation ‘* Binary or BCD representation of time, calendar, and alarm * 12-01 24-hour elock with AM and PMin 12-hour mode '* Daylight Savings Time option '* Selectable between Motorola and Intel bus timing ‘© Muttiplex bus for pin efficioncy «+ Interfaced with software as 64 RAM locations = 14 bytes of clock and control registers. 1 50 bytes of general purpose R. * Programmable square wave output signal «= Bus-compatibe interrupt signals (TQ) ‘* Three interrupts are separately software-maskable and testable - Time-of-day alarm once/second to onca/day 2 Periodic rates from 122 ps to 500 ms © End of clock update cycle DESCRIPTION ‘The DS1287 Real Time Clock is designed to be adirac replacement for the MC145818A. A lithium energy ‘source, quartz crystal, and write-protection circuitry are ‘contained within a 24-pin dual in-fine package. As such, the DS1287 isa complete subsystem replacing 16 com- ponents in a typical application, The functions inciude a PIN ASSIGNMENT PIN DESCRIPTION ‘ADO-ADT | ~ Multiplexed address/data bus Ne © No connection MOT - Bus type selection cs > Chip select AS = Address strobe Rw + Read/write input ps > Data strobe ESET + Reset input Ro 1 Interrupt roquest output saw > Square wave out Vee 2 45 vol supply GND + Ground nonvolatile time-ol-day dock, an alam, a one-hundred-year calendar, programmable interrupt square wave generator, and 50 bytes of nonvolatile st jc RAM. The real time clock is distinctive in that time-of-day and memory are maintained even in the ab- sence of power. 020582 17 ee Rsie OPERATION ‘The block diagram in Figure 1 shows the pin connec tions with the major internal functions of the 0S1287. ‘The following paragraphs describe the function of each pin, owen vee | Semen | Yee Nes) sere Nee PERIODIC WTERRUPTSQUARE WAVE | paar eae SucTon Vaart PROTECT iE | a i waeour a = necistens ABCD ‘CLOCK CALENOAA, 5G BAN USER RAM ‘aves POWER-DOWN/POWER-UP CONSIDERATIONS. The Real Time Clock function will continue to operato, and al of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of tha level of the Vec input. When Voc is applied to the DS1287 and reaches alevel of greater than 4.25 volts, the davies be- comes accessible after 100 ms, provided that the osci- latoris running and the oscillator countdown chain is not in reset (s0 Register A). This time period allows the systom to stabilize after power is applied. When Voc. falls Below 4.25 vote, the chip select inputs teraly forcad to an inactive lavel regardless ofthe value of at the input pin, The OS1287 is, therofors, wrte-pro- tected. When the 0S1287 is in a write-pratected state, allinptts are ignored andall outputs are in ahighimped- ance state. When Voc falls below a level of approx mately 2 vats, the extornal Voc supply is switched off and an internal fthium energy source supplies powerto the Real Time Clock and the RAM memorySIGNAL DESCRIPTIONS GND, Veg OC powers provided tothe device on these pins, Voc is the ~Svot input, When 5 volts ara applied ithin normal limits, the device is fully accessible and Gata can be written and read. When Voc is below 4.25 wrlts typical, reads_and writes are inhibited, However, the timekeeping function continues unaffected by the tower input veltage. As Vcc falls balow 3 vets typical, the RAM and timekeeper are switched over to an inter tral lithium energy source. The timekeeping function maintains an accuracy of =1 minute par month at 25°C regardless of the voltage input on the Vc Fin. MOT (Mode Select) - The MOT pin offars the flexibility to choose between two bus types. When connected to Vee, Moterela bus timing is selected. When conn to GNO orlettdisconnected, Intal bus timing is selected. The pin has aninternal pull-down resistance of approxi- mately 20 KO. ‘SQW (Square Wave Output) - The SQW pin can output 2 signal rom one of 13 taps provided by the 15 internal divider stages of the Real Time Clock. The frequency ‘of tho SQW pin can be changed by programming Regis- ter A as shown in Table 1. The SQW signal can be tumed on and off using the SQWEDit in Register. The ‘SQW signal is net available whan Voc is less than 4.25 volts typical. Bre aie reagan keer a eka deken ba dddeeebiasnienl ISTER A tp PERIODIC SQW OUTPUT RSt RSO INTERRUPT RATE FREQUENCY a eceoras on aO ie a es Theses re aH a tela sae aaa Ee eee aun zea cata on cane ‘ean em soa aabees Tae oe a a ee ee ea rae Ta oe ea oe wate ee] oe fasta a ADO-ADT (Multiplexed Bidlrectional Address/Data Bus) - Miltiplaxed buses save pins because address information and data information time share the samo signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths aro used for data in the sacond portion of the Cyclo. Address/data muttiplexing does net slow the ac ‘cass time of the DS1287 since the bus change from ad- dross to data occurs during the internal RAM access time, Addresses must be valid prior to the faling edge ‘of AS/ALE, at which time the 0S1287 latches the ad- dress from ADO to ADS. Valid write data must ba pres- cent and held stable during the latter portion of the DS or GR pulses, In a road cyclo the OS1287 outputs 8 bits Gf data during he later portion ofthe OS or RD pulses. The read cydo is terminated and the bus ratums to a igh impedance stata as OS transtions low inthe caso Of Motorola timing or as AD transitions high inthe case of Intel timing. [AS (Addreaa Strobe Input) - A positive going address Grobe pulse serves to domuitiplax the bus. The falling Ségect ASIAL # causesthe address tobe latched within the 051287. ‘o20582 37 639st DS (Mata Strobe or Read Inptt)- The DS/RD pin has ‘pwo modes of operation depending én the level of the MOT pin. When the MOT pin is connected to Vcc, Mo- torala bus timing is selected, In this mode DS is @ post tive pulse during the latter portion of the bus cycle and ig called Data Strobe. During read cycles, DS signifies tho time thatthe DS1267 isto drive the bidirectional bus. in wite cycles the trailing edge of DS causes the 51287 to latch the written data. When the MOT connected to GNO, intel bus timing is selected. In this mode the DS pin is called Read(RO). RO identifies the time period when the DS1287 érives the bus with read data. The RD signalis the same definition as the Output Enable (OE) signal on a typical memory. RAW (Read/Write Input)-The AAW pin also has two modes of operation. When the MOT pin is connected to Voge for Motorola timing, F/Wis at a lovel which inci cates whether the current cycleis aread orwrite. Aread cyclo is indicated with a high level on FAW while DS is high. A wite cycle is indicated when FAW is low during Ds. When the MOT pin is connected to GND for intel timing, the AW signals an active low signal called WR. In this ode tho FAW pin has the same meaning as the Wrte Enable signal (WE) on generic RAMs. ‘TS (Chip Select Input) - The Chip Select signal must bbe asserted low for a bus cyclo in the DS1287 tobe ac cessed. CS must be kept in the active state during DS ‘and AS for Motorela timing and during FD and WR for Intel timing. Bus cycles which take place without as- sorting CS will latch addresses but no access will occur. When Vec is below 4.25 valts, the 0S1287 internally in- hibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outag: TAG (Interrupt Request Output) -The TAG pinis an ac tive low output of the DS1287 that can be used as an in- terrupt input to a processor. The IFG output remains owas long as the status bit causing the interrupts pras- entand the corresponding intarrupt-enable bit is sat. To clear the IAG pin the processor program normally reads the register, The RESET pir also clears pending in- tempts. When ne interrupt conditions are present, the TRC level isinthe high impodance state. Mulipl interrupting do- vices can be connected to an JRC bus. The IRC bus is anopen drain output and requires an external pull-up ro- sistor. FESET (Reset Input) - The RESET pin has no offct on the clock, calertar, or RAM. On power-up the RE- 20582 417 a 6-90 SET pin can be held low for a time in order to allow the power supply to stabilize, The amount of time that FE> SET is held low is dependent on the application, How- ever. f RESET is used on power-up, the time RESET is, low should exceed 200 ms to make sure that the intornal timer that controls the 0S1287 on power-up has timed out. When RESET is low and Voc is above 4.25 votts, the follow ing occurs: A. Periodic interrupt Enabio (PIE) bits cleared to ere. B, Alarm Interrupt Enable (AIE) bitis cleared to zero. ©. Update Ended Interrupt Flag (UF) bits cloarod tozere. D. Interrupt Request Status Fiag (iRGF bit is cleared to 2070. E. Periodic Interrupt Flag (PF) bit is cleared to zero, F.. The dovice is not accessible until RESET is re- tumed high. G. Alarm Intorupt Flag (AF) bit is cleared to z0r0. H. TH@pinisin tho high impedance stats. ‘Square Wave Output Enable (SWE) bit is cleared to zero, Update Ended Interrupt Enable (UIE) is cleared to zero. In a typical application RESET can be connected to Vee: This connection will allow the DS1287 togo in and out of power fail without affecting any of the control reg- istors. ADDRESS MAP The address map of the DS1287 is shown in Figure 2. ‘The addrass map consists of 50 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and four bytes which are used for control and status. All 64 bytes can be cirectly written or read ‘except for the fellowing: i 2 3. Registers C and D aro read-only. Bit 7 of Register A is read-only. ‘Tho high order bit of the seconds byte is read-only. The contents of four registers (A,B,C, and D) are de- seribed in the “Registers” section.saves F SECONDS SECONDS ALARM MINUTES HOURS HOURS ALARM DAY OF THE WEEK BINARY Of BCO INPUTS DAY OF THE MONTH — — MONTH yearn 10 REGSTERA ” REGISTERS 2 REGISTER C 2 REGISTER O TIME, CALENDAR AND ALARM LOCATIONS ‘The time and calendar information is obtained by read- ing the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAMbytes. The contents of the ten time, calendar, and alarm bytes can be either Binary or Binary-Coded Deci- mal (BCD) format. Before writing the internal time, cal- ‘endar, and alarm registers, the SET bit in Register B should be written to a logic one to prevent updates from ‘occurring while access is being attempted. In addition to writing the ten time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (OM) of Register 8 must be set to the appropriate logic level. Allten time, calendar, and alarm bytes must use the same data mode. The Set bit in Register B shoukt be cleared attar the data mode bit has been written to allow the real ime clock to update the time and calendar bytes. Ones initialized, the real time clock makes all up~ dates in the selacted mode, The data mode cannot be changed without reinitializing the ten data byte Table 2 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The 24-12bit can- not be changed without reinitializing the hour locations. When the 12-hour formatis selected, the high orderbit of the hours byte represents PM when it is a logic one. “The time, calendar, and alarm bytes are always acces sible because thay are double buffered. Once per sec- ond the ten bytes ato advanced by one second and checked for an alarm condition. Ifa read ofthe time and ‘calendar data occurs during an update, aproblem exists where seconds, minutes, hours, ete. may not correlate, ‘The probability of reading incorrect time and calendar data is low. Several methods cf avoiding any possibie incorrea time and calendar reads are covered later in this text, ‘The three alarm bytes can be used in two ways. First, when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm inter- ruptis initiated at the specifiedtime each day ifthe alarm enable bitis high . The second use condition is to insert ‘a “don’t care” state in one or more of the thrae alarm by- tes, The “don’t care” code is any hexadecimal value from CO to FE The two mest significant bts of each byte set tha “don't cara” condition when at logic 1. An alarm will be generated each hour when the “don't care” bits are set in the hours byte. Similarly, an alarm is gener ated every minute with “don’t care” codes in the hours ‘and minute alarm bytes. The “don’t care” codes in all three alarm bytes create an interrupt every second. ' 5, % 020582 $17osias pooness | runction | “Range” [SnARYONAMGDE | 0D OATANODE @ Seconds oe | 0038 00-38 1 Seconds Alam ose | 0038 30-89 2 inate ose | 0038 00-58 3 Winwtes Alar ose | 0038 00-89 ¢ Tannin Nede | ita | Orca eTEC PM | O1-T2AMer-S2PM Hours-24-hr Mode 0-23 00-17, 00-23 E FousAermizn | aa | ore aware Pm | or-reAMar-s2PMd Hours Mam-2ehr [| 02 _| 80.17 coe ¢ Day ofthe Week v7 | oar O17 Sunday = 7 Dato ofthe Month Tai [oe ora Month ria | 0100 ot 3 Year ose | 00 00-89 NONVOLATILE RAM ‘When an interrupt event occurs, the relating flag bitis “The 50 general purpose nonvolatile RAM bytes are net dedicated to any special function within the DS1287. ‘They canbe used by the processor program as nenvek atle memory and are fully available during the update eyes. INTERRUPTS sotto logic tin Register C. These flag bits ara sat inde- pendent of the state of the corresponding enable bitin Register 8. Tho flag bit can be used in a polling mode without enabling the corresponding enable bits. The in- torruptfag bitis a status bit which software can intorro- gata as necessary. When a flags set, an indication is Given to software that an interrupt event has occurred Sines the flag bit was lastroad; however, care should be “The ATC plus RAM includes thraa separate, fully auto-___taken when using the Rag bis a6 they are cleared each atic sources of interrupt for aprocessor. The alarm in- terrupt can be programmed to occur at rates from onea por second to once per day. The periodic interrupt can Bo selected for rates from 500 ms to 122 us. The up- date-ended interrupt can be used to indicate to the pro- gram that an update cycle is complete. Each of these Fadependentinterrupt conditions is described in greater detail in other sections of this text. “The processor program can select which interrupts, any, are going tobe used. Three bas in Register 8 ot blo the interrupts. Writing a logic 1 to an interrupt-en- able bit permits that interrupt to be initiated when the event occurs. Azero in an interrupt-snable bit prohibits the IHG pin from being assarted from that interrupt con- dition, fan interrupt lagis already set when an interrupt is enabled, [FG is immediately sat at an active level, al- though the interrupt initiating the event may have oc- curred much earfier, Asa resuk, there are cases where the program should dear such earliar initiated interrepts before first enabling new interrupts. ab onoss2 61794 time Register C is read. Double latching isincluced with Register C so that bis which are set remain stable throughout the read cycie, Allbits which are set (high) fre cleared when read and new interrupts which are ponding during the read cycle aro held until after the Fyele is compioted. One, two, or three bits can be set hen reading Register C. Each utlized flag bit should bbe examined when read to ensure that no interrupts ar@ lest, “The second flag bit usage method is with fully enabled itomupts, When an intorruptfiag bitis sat and the core- ‘sponding interrugt erable bit is also set, the TRG pin is srSoned iow. IRC is assarted as long as at least one of tho theo intorupt soureas has fs flag and enable bis both set. The IROF bit in Register C is a one whenever the IAG pin s being drivan low, Detormination that the FIC inated an interrupt is accamplished by reading __ Ragistac€. A logic one in bt 7 (|RQFbit indicates that bas or more interrupts have beon inated by the SSta87. The act of reading Register C clears lacie flag bis and the IROF bit 6-92estes? OSCILLATOR CONTROL BITS When the 0S1267 is shipped from the factory. the inter- nal oscillators turned off. This feature prevents the lithi- um energy cell from being used until its installed in a system, A patter of 010 in bits 4 through 6 of Register ‘A will turn the oscillator on and enable the countdown chain, A patter of 11X will tum the oscillator on, but holds the countdown chain of the oscillator in reset, All other combinations of bits 4 through 6 keep the oscilla tor of. SQUARE WAVE OUTPUT SELECTION ‘Thirteen of the 15 divider taps are made available to a j-of-15 selector, as shown in the block diagram of Figure 1. The first purpase of selecting a divider tap is to generate a square wave output signal on the SOW pin, The RSO-RSQ bits in Register A establish the Equare wave output frequency. These frequencies aro [ited in Table 1. The SQW frequency selection shares its 1-0f-15 selector with the periodic interrupt generator. Once the frequency is selected, the output of the SAW pin can be tumed on and off under program control with the square wave enable bit (SQWE). PERIODIC INTERRUPT SELECTION ‘The periodic interrupt will use the TRG pin to go to an active stato from once every 500 ms to once every {22 us. This function is separate from the alarm inter- rupt which ean be output from once per second to once por day. The periocicinterrupt rate is selected using the Pome Hagister A bits which select the square wave fro- Guency (see Table 1). Changing the Register A bits al- fects both the square wave frequency and the periodic intorruptoutput, However, each function has separate enable bit in Register B. The SQWE bit controls the square wave output. Similarly, the periodic interrupt is Shabled by the PIE bitin Register B. The periodic intor- nupt canbe used with software counters to measur in- puts, create output intervals, or await the next needed software function. UPDATE CYCLE ‘The DS1287 executes an update cycle onceper second regardless of the SET bit in Register 8. When the SET bitin Register is setto one, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time increments. However, the time countdown chain continues to update the internal copy of the butter. This feature allows time to maintain ‘accuracy indepandent of reading or writing the time, cal- fendar, and alarm buffers and also guarantees that time and calendar information is consistent. The update @yele also compares each alarm byte with the corre- sponding time byte and issues an alarm if a match orif 2 "don’t care” cada is present in all three positions. There are three methods that can handle aceass of tho realtime clock that avoid any possibilty of accessing in- consistent time and calendar data. The first method Uses the update-ended interrupt. if enabled, an inter- rupt occurs after every update cycle that indicates that Over 889 ms are available to read validtime and dato in- formation. ithis interruptis used, the IROF bitin Regis tor should be cleared before leaving the interrupt rou- tine. ‘Asecond method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in prog- tess. The UIP bit will pulse once per second. After tho UIPbitgoes high, the update transfer occurs 244 45 lat- ‘or. if a low is read on the UIP bit, the user has at least ~ 244 us before the time/calendar data will be changed. Therefore, the user should avoid interrupt service rou- tines that would cause the time needed to read valid timelcalendar data to exceed 244 1s. ‘The third method uses a periodic interrupt to determine # an update cycle is in progress. The UIP bitin Register ‘Ais set high botween the sotting of the PF bitin Register C (see Figure 3). Periodic interrupts that occur ata rato of greater than tayc allow valid time and date informa tonto ba reached at each occurrence of the periodic in- tempt. The reads should be complete within 1 (tqy,¢ ou) 19 ensure that data not read during the update cycio. SUES Seda seb a aor a ee) lee EEE ae — ol | a 2 Ht toy = Pate Imtamupt tem interval par Tabla 1 uc c Delay Sve Dolre Update cycle = 204 8. wer 220562 707 693REGISTERS ‘The DS1287 has four contro! registers which are accas- sible at all times, even during the update cycia, REGISTER A sa fe ar? [aire [ars [ars [ara [ar [art [are ue [ove | ov | ove | RS | Ase | AS | FSO uIP ‘The Update In Progress (UIP) bisa status flag that can be monitored, When the UIP bit is a one, the update transfer will soon occur, When UIP is a zar0, tha update transfer will net occur for at least 2¢4 ps. The time, cal endar, and alarm information in RAM is fully available for access when the UIP bits zero. The UIP bitis road only and is net affocted by RESET. Writing the SET bit in Register 8 to a one inhibits any update transfer and clears the UIP status bit Vo, DV1, DV2 ‘These thrae bits ara used to tum the oscillator on or off and to reset the countdown chain. A pattem of 010 is, the only combination ofits that will turn the oscillator on and allow the RTC to keep time. A pattern of 11Xwillen- able the oscillator but holds the countdown chain in re- set, The next update will eccur at 500 ms aftar apattem of 010 is written to DVO, DV1, and DV2. RS3, RS2, RS1, RSO “These four rate-solaction bits select one of the 13 taps on the 15-stage divider er disable the divider output, ‘The tap selected can be used to generate an output square wave (SQW pin) anc/or aperiodicinterrupt. The user can do one of the following: 1. Enable the interrupt with the PIE bi; Enable the SQW output pin with the SQWE bit; Enable both at the sama time and the same rate; or Enable ni er, 0 1 lists the periodic interrupt rates and the square wave frequencies that can be chesan with the AS bits. ‘These four road/writa bits are not afactad by RESET. SET When the SET bitis a zero, the update transter functions normally by advancing the counts once per second, ‘When the SET bitis writtento acne, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycies can be executed in a similar manner. SET is a read/write bit that is not modified by RESET or internal functions of the 0S1287. PIE ‘The periodic interrupt enable PIE bitis a read/write bit which allows the Pariodic Interrupt Flag (PF) bit in Reg- istorC to drive the IR pin low. When the PIE itis sat to one, periodic interupts are generated by driving the TRG pin low at a rate specified by the RS3-ASO bits of Rogister A. A zero in the PIE bit blocks the TFG output frombeing driven by a periodic interrupt, butthe Pariod- ic Flag (PF) bitis stil sot at the poriedic rato. PIE is nat modified by any internal 0S1287 functions, but is cleared to zero on AIE ‘The Alarm Interrupt Enable (AIE) bit is a readiwrite bit ‘which, when set to a one, permits the Alarm Fiag (AF) bitin ragister Cto assert RQ. An alarminterrupt occurs foreach second thatthe three time bytes equal the three alarmbytesinclucing a“don'tcare” alarm code ofbinary 11XXOXX, When the AIE bit is set to zero, the AF bi does rot initiate tho IRQ signal. The RESET pin clears temal functions of the DS1287 donot The Update Ended interrupt Enable (UIE) bts a read write bit that enables the Update Ended Flag (UF) bitin Ragister C to assart i, The RESET pin going low or the SET bit going high cloars to UIE bit SQWE ‘When the Square Wave Enable (SQWE) bitis satto a one, a square wave signal at the frequency set by the rate-solection bits RSS through RSO is driven out on a SQW pin. When the SQWE bitis set to zero, tha SAW Bins held low; the state of SOWE is cleared by the AE SET pin, SQWE is a readhwrite bi DM ‘The Data Mode (OM) bit indicates whathertime and cal- cendar information is in binary or BCD format. The DM Bit is set by the program to the appropriate format and canbe read as required. Thisbitis not modified by inter- nal functions or RESET. A one in OM signifies binary data while a zero in OM species Binary Coded Decimal (BCO) data, REGISTER B visa ss a7 [ate [ars [aa] FT [aE | wT [are Ser [PE | AE | WE [Save | ow eae [OSE caossa an u eo24/12 ‘The 24/12 controlbit establishes the format of the hours tyne. Aone indicates the 24-hour mode and a zero inci orgs the 12-hour moda, Thisbitis read/write and is not GHocted by internal functions ot RESET. DSE The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to one, On the first Sunday in Aprilthe time increments from 1.58:59 AM to [Link] AM. On the last Sunday in ‘Octobar when the time first reaches [Link] AM it changes to [Link] AM. These special updates do net ‘gecur when the DSE bits a zero. This bitisnot affected by internal functions or REGISTER C sa 153 any [are [ars [ava [ars [en [sri [ere mop pe pepe tet e |e IRQF ‘The Interrupt Request Flag (IROF) bit is set to a one when one of more of the following are true: Tate, ROF'= (PF + PIE) + (AF + ANE) + (UF + UIE). Any time the IRF bitis a one, the [RG pin is driven low. All flag bits aro cleared aftor Register C is read by the program of when the RESET pin is low, PF The Periodic Interrupt Flag (PF) is a read-only bit whieh ig setto a one when an edge is detected on the selected tap of the divider chain. The RSS through RSO bits es- tablish the periodic rate, PF is set to a one independent of the stata of the PIE bit, When both PF and PIE aro ones, the TRG signal is active and will set the IROF bit She BE otis cleared by a RESET ova software read of Rogister C AF ‘Acne in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time. Ifthe AIE bit is also a one, the IG pin will go low and a one will appear in the IROF bit. ‘A RESET or a oad of Register CC will clear AF. UF “The Update Ended Interrupt Flag (UF) bit is set after each updato cyeie. When the UIE it is set to one, the ono in UF causes the [RGF bittobe a ona which will as Sort the TRG pin. UF is cleared by reading Register C ora RESET. : BIT 0 THROUGH BIT 3 ‘These are unused bits of the status Register C. These bits always read zero and cannot be written. REGISTER D mse 18 aT are [ers [ate [airs [ora | ars [are wpe yetere tered ® VAT “The Valid RAM and Time (VAT) bitis settothe one state by Dallas Semiconductor prior to shipment. This bits rat wttable and should always be a one when read. If zero is ever present, an exhausted internal thium en- ‘source is indicated and both the contents of tho Fire data and RAM data are questionable. This bit is Unaffected by RESET. BIT 6 THROUGH BIT 0 ‘The remaining bits of Register D are net usable. They cannotbe written and, when read, they will always read 2010. : z0sse 97 6-95csiz7 ABSOLUTE MAXIMUM RATINGS" VOLTAGE ON ANY PIN RELATIVETO GROUND = 0.3 T0+7.0V OPERATING TEMPERATURE 0°C TO 70°C STORAGE TEMPERATURE 40°C TO +70°C SOLDERING TEMPERATURE 280°C FOR 10 SECONDS “Thisis a stross rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may atfect reliability. (RECOMMENDED DC OPERATING CONDITIONS (0°C TO 70°C} PARAMETER symeot | MIN TP max | UNITS | NOTES Power Supply Vokage Vee 45 50 35 v 5 Input Logie t Von 22 Veoa |v 1 Input Logi 0 Ve 22 +08 v 1 DC ELECTRICAL CHARACTERISTICS (0°C TO 70°C, Veo=4.5T0 5.5V) PARAMETER: SYMBOL | MIN TYP max | units [ NOTES Power Supply Currant Toot 7 15 mA 2 Input Leakage hi, “1.0 +10 HA 3 UO Leakage ho “1.0 +10 A 4 Input Current wor 1.0) +500 vA 3 Output @ 2.4V on 1.0) mA 15 Output @ 0.4V lo. 40 mA 1 PARAMETER, SyMBOL | MIN TYP Max | UNITS | NOTES Input Capacitance Cin 5 PF Output Capacitance: Cour I Fi pF exasse 108g 2 e396SYMBOL, NOTES Gyele Time eye 385, oe as Pulse Wisth, DS/E Low or PWe | 150 ns ROIWA High Pulse Wisth, DS/E High or PWen | 125 ns ROIWR Low Input Rise and Fall Time tate 30 ns RWI Hold Time Tawi 10 ns RW Setup Time Before DSIE. taws 50 ns Chip Select Setup Time Before ‘es 20 ns! 8, WA, or AO ‘Chip Select Hold Time ten ° ns Read Data Hol Time ton 10 Ey ns ‘Wiita Data Held Time tonw ° rs Muxed Address Valid Time to tase 30 ns ASVALE Fall Muxed Address Holi Timo Tait 10 ns Delay Time DS/Eto AS/ALE Rise | tasd | 25 ns Pulse Width AS/ALE High PWas | _ 60 7s Delay Time, AS/ALEIC DS/EFise | taseo | 40 ns ‘Output Data Delay Time From toon 20 120 ns 6 DS/E or FD Data Setup Timo toew | 100 ns Reset Pulse Width ta 5 o TAG Release from DS ‘nos 6 TRG Release from RESET RA 2 s aos 7ostas? NOTES 1; All-voitages are referenced to ground 2. Alloutputs are open. 3, The MOT pin has an internal pulldown of 20 Ka. +S VOLTS ° Applies to the AO0-AD7 zins, the TAC pin and tho SQW pin when each is in the high imped= ance stata. The TAG pin is open drain Measured with a load as shown in Figure 4. caonea iat e938599san cd / (eosin) wa We, wv cri ein al Aven? c20ss2 wiz 2 6100(CURRENT suPPLED FROM INTERNAL UTHIUM ENERGY CELL DATA RETENTION ‘er Poiana tom! PARAMETER MIN TYP max | UNITS | NOTES GS at Via before Power-Down ° slew from 4.5V to OV 300 rey Gav Vag slaw rom OV 10 4.5V 100 ro avn) GE at Vip aftr Powor-Up 20 200 ms | PARAMETER ‘SYMBOL units | NOTES Expected Data Retention NOTE The real time clock will keep time to an accuracy of 1 minute per month during data retention time for the period of ton. WARNING Under no circumstancas are negative undarshoois. of any amplitude, allowed when deviesis in battery backup mode, caesea 7 e102 feerepee eee eee eee seca eeree reece eeea ce iti 1 a i eee i : 40} ae Kk ote I-— 4 I 8 ee Eis Soo sero TNA, Pee 2aPN PINS 2 9.16, 20,21 AND 22 ARE MSSING BY om | wm | MAX SescN am | tam | as wnt | 3885 | S350 am | oss | oz00 — ui | 388 | 8 em | ems | x7 sit | aa | Se pin | eso | exe wut | SE? | Soe zm | ns | amo wu | SS | Se FIN, ono | 2740 | fuse | Sa | Se am | ease | ano wit | 28° | Sh min | esse | one uh | $288 | S00 ain, | ogee | ase | wh | Ss" | 8S oy | ae | a ae | 83e° | os e103