Some GPIO can't not be used?

Robotics & Edge Computing Jetson & Embedded Systems Jetson Thor
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1

Hi NV_Team,

We used six gpio for camera pwdn fucntion, only three gpio can be set to high, the other three gpio can’t be set high?

We can’t find these three gpios in

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#These three gpio set high not okay
#define CAM2_PWDN	TEGRA264_MAIN_GPIO(V, 2)  /2 PWDN
#define CAM4_PWDN	TEGRA264_MAIN_GPIO(Q, 3)  /4 PWDN
#define CAM6_PWDN	TEGRA264_MAIN_GPIO(V, 4)  /6 PWDN

#These three gpio set high okay
#define CAM1_PWDN	TEGRA264_MAIN_GPIO(V, 5)  /1 PWDN
#define CAM3_PWDN	TEGRA264_MAIN_GPIO(Q, 2)  /3 PWDN
#define CAM5_PWDN	TEGRA264_AON_GPIO(DD, 0)  /5 PWDN

63 (spi5_miso_pq3): 
        pull=1
        tristate=1
        enable-input=0
        open-drain=1
        io-reset=1
        rcv-sel=1
        io-hv=1
        schmitt=0
        pull-down-strength=8
        pull-up-strength=8
        drive-type=1
        gpio-mode=1
        function=rsvd1


65 (spi5_sck_pq2):
        pull=0
        tristate=0
        enable-input=0
        open-drain=1
        io-reset=1
        rcv-sel=1
        io-hv=1
        schmitt=0
        pull-down-strength=8
        pull-up-strength=8
        drive-type=1
        gpio-mode=0
        function=rsvd1
3

Hi NV_Team,

Where to find the memory address for GPIOs, so we can use devmem to check it.

like this topic

4

Hi Luna2020,

If the pins cannot be found in pinmux spreadsheet, then they may not be able to be used by customer on Thor.
Some GPIOs on Thor are from FSI, which can not be accessed and be read through devmem.

5

Hi KevinFFF,

  1. where to find the devmem address for the gpios from the TRM or some other documetns ?
  2. for example PQ.03/PV.02

Thanks。

6

Hi NV_Team,

Any update?

Where to find the gpio devmem address, AGX Orin can find through TRM, but Thor not find address from TRM .

7

It seems the TRM of Thor is shared with partner only.
Do you have any contact window with NVIDIA for this requirement?

8

Hi NV_Team,

We have contacted with NV PM, and only this TRM file.

Thor-Soc-TRM_DP-11881-002_v1.0.pdf

9

Yes, it is the correct TRM for Thor.
Do you find required information in this doc?

10

Hi KevinFFF,

There is no devmem address for gpio and other pinmux can be found. If you can find the gpio devmem such as PQ.03/PV.02, please tell me which page and how to calculate it ?

thanks.

11

Hi NV_Team，

Any update ？

12

We have fixed it by setting pinmux, TRM still no devmem address to explain it.l

13

yes, it seems the those address for GPIO has been removed in TRM of Thor.
Please just use pinmux spreadsheet to configure the pinmux.

14

I have spent time on a similar case here where I tried and tried and tried to change a GPIO signal from user space without success. Setting a static value in pinmux works.

Is it a known issue for Nvidia? Any updates?

15

What do you mean about “setting a static value”?

As my understanding, using pinmux spreadsheet to generate pinmux/gpio dtsi is required before you want to use the pin as the most of the pins are configured as Input by default.

16

I mean setting its value in my pinmux device tree file (similar to tegra264-mb1-bct-gpio-p3834-xxxx-p4071-0008.dtsi) like this:

#include "tegra264-gpio.h"

gpio@ac300000 {
	 default {
		gpio-input = <
			TEGRA264_MAIN_GPIO(J, 6)
			TEGRA264_MAIN_GPIO(P, 1)
			TEGRA264_MAIN_GPIO(P, 3)
			TEGRA264_MAIN_GPIO(Q, 5)
			TEGRA264_MAIN_GPIO(Q, 6)
			TEGRA264_MAIN_GPIO(Q, 7)
			TEGRA264_MAIN_GPIO(S, 0)
			TEGRA264_MAIN_GPIO(S, 1)
			TEGRA264_MAIN_GPIO(U, 0)
			TEGRA264_MAIN_GPIO(U, 2)
			TEGRA264_MAIN_GPIO(U, 6)
			TEGRA264_MAIN_GPIO(V, 1)
			TEGRA264_MAIN_GPIO(Z, 5)
			TEGRA264_MAIN_GPIO(AL, 0)
			>;
		gpio-output-low = <
			TEGRA264_MAIN_GPIO(H, 0)
			TEGRA264_MAIN_GPIO(H, 1)
			>;
		gpio-output-high = <
			TEGRA264_MAIN_GPIO(F, 0)
			TEGRA264_MAIN_GPIO(F, 1)
			TEGRA264_MAIN_GPIO(F, 2)
			TEGRA264_MAIN_GPIO(F, 7)
			TEGRA264_MAIN_GPIO(L, 7)
			TEGRA264_MAIN_GPIO(U, 3)
			>;
	};
};

Then I assume mb1 bootloader set that GPIO pin according to this.

In my case I had one GPIO pin TEGRA264_MAIN_GPIO(F, 7) that was stuck to ‘0’ and I’m not able to change its value from Linux. I have configured it in pinmux tool as output and GPIO and have these settings:

			pwm2_pf7 {
				nvidia,pins = "pwm2_pf7";
				nvidia,function = "rsvd2";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
				nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
				nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
				nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
			};

In Linux user space I have identified the GPIO pin as gpiochip2 and line 127. But when I change this pin with gpioset it doesn’t change value. The way to get this signal to ‘1’ was to set it from bootloader. But I want to know if this is by design or a bug that needs to be resolved? I hope we can change GPIO value from Linux and use it properly.

17

Could you try using the following command to control PF.07 to high in linux?

# gpioset --mode=wait `gpiofind "PF.07"`=1
18

This command is working only if I include my pins in `gpio-output-high` in tegra264-mb1-bct-gpio-p3834-xxxx-p4071-0008.dtsi. Without a default value of the pins in tegra264-mb1-bct-gpio-p3834-xxxx-p4071-0008.dtsi I can not control my pin from user space.

19

Do you mean that command won’t work if you put TEGRA264_MAIN_GPIO(F, 7) into gpio-output-low of tegra264-mb1-bct-gpio-p3834-xxxx-p4071-0008.dtsi?

		gpio-output-low = <
			TEGRA264_MAIN_GPIO(H, 0)
			TEGRA264_MAIN_GPIO(H, 1)
+			TEGRA264_MAIN_GPIO(F, 7)
			>;

Actually, we would suggest using pinmux spreadsheet to configure the pinmux before use the pin.

20

I haven’t tried to out it in `gpio-output-low`, but my guess is that it also works. I use the pinmux spreadsheet to generate my dts file. But in my pinmux spreadsheet I have not put anything in “Req. Initial State” which means I don’t have it in either `gpio-output-low`or `gpio-output-high`. My assumption then is that the Linux driver will take care of that once I allocate and use the pin (electrically it doesn’t matter as I have external pull resistors). From what it looks like there is currently a requirement to have “Req. Initial State” set for the pin in order to use it from my driver. This looks wrong to me or poorly documented.

21

Maybe you can refer to the following table captured from Jetson AGX Series Module Pinmux Application Note

image
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Only Drive 0 or Drive 1 are valid for an Output pin.