How to using CSI1 CLK?

[MDS_Eddy]

We designed our custom board for Orin NX.

It has to use CSI0 ~ CSI3 for each 4 devices.

CSI1_CLK doesn’t works and the others(0, 2, 3) is working well.

It is notified to set RSVD in documentation and Pinmux table.

How can I use it?

If I need to modify someting on the device tree, Could you give us some advise?

[carolyuu]

*** Please note that this reply is generated by LLM automatically ***

Based on the provided context, I’ll try to help you with your question.

It seems like you’re designing a custom board for the Jetson Orin NX module, and you’re experiencing issues with the CSI1_CLK signal not working, while the others (CSI0, CSI2, CSI3) are working fine. You’ve also noticed that the documentation and Pinmux table mention setting RSVD (Reserved) for this signal.

Here’s what I can infer from the context:

1. The Jetson Orin NX module has eight MIPI CSI lanes, which can be configured as two quad-lane camera streams or four dual-lane camera streams. Each data lane has a peak bandwidth of up to 2.5 Gbps.
2. The CSI0_CLK_N and CSI0_CLK_P signals are used for the CSI0 clock, while CSI1_CLK_N and CSI1_CLK_P are used for the CSI1 clock. Similarly, CSI2_CLK_N and CSI2_CLK_P are used for the CSI2 clock, and CSI3_CLK_N and CSI3_CLK_P are used for the CSI3 clock.
3. The Pinmux table and documentation mention setting RSVD for the CSI1_CLK signal. This typically means that the signal is reserved for a specific purpose or is not intended to be used in a particular configuration.

To use the CSI1_CLK signal, you’ll likely need to modify the Pinmux configuration and possibly the device tree. Here are some steps you can take:

1. Check the Pinmux configuration: Verify that the Pinmux configuration for the CSI1_CLK signal is set to the correct mode. You can use the jetson-io tool to configure the Pinmux settings. Make sure to set the CSI1_CLK signal to the correct mode (e.g., csi1_clk) and not to RSVD.
2. Modify the device tree: You may need to modify the device tree to enable the CSI1_CLK signal. Check the device tree source files (e.g., tegra194-p2888-0001-p2822-0000.dts) and look for the CSI1_CLK signal. You may need to add or modify the csi1_clk node to enable the signal.
3. Verify the signal routing: Double-check the signal routing on your custom board to ensure that the CSI1_CLK signal is properly connected to the Jetson Orin NX module.

Before making any changes, I recommend consulting the Jetson Orin NX Series and Jetson Orin Nano Series Product Design Guide (DG-10931-001_v1.4) and the Orin (SoC) Technical Reference Manual for more information on Pinmux configuration and device tree modifications.

Additionally, you may want to consider the following:

• CSI signal multiplexing: If you’re using multiple CSI signals, ensure that you’re not multiplexing them incorrectly. The Jetson Orin NX module has specific requirements for CSI signal multiplexing, which are documented in the product design guide.
• Clock signal requirements: Verify that the clock signal requirements for your camera modules are met. The Jetson Orin NX module has specific clock signal requirements, which are documented in the product design guide.

If you’re still unsure about how to proceed, I recommend reaching out to NVIDIA support or consulting with a qualified engineer who has experience with the Jetson Orin NX module and custom board design.

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[MDS_Eddy]

One more asking before reviewing the device tree source code.

The TRM documentation is notified CLOCK LANE “B” is not allowed.

I’m wondering if this means it’s not working even after I modify the lane polarity

[sgursal]

Assuming you are using CSI 2-Lane connections for your 4 camera devices then please follow the design guide configuration example as below.

[MDS_Eddy]

It was CSI1 data line pin mapping issue.
It is resolved.