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Chih-ming Hung

University of Florida, ECE, Alumnus

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Texas Instruments

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UAE University

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Papers by Chih-ming Hung

A 1 . 8 dB NF Receiver front-end for GSM / GPRS in a 90 nm Digital CMOS

An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90nm digital CMOS technology is... more An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90nm digital CMOS technology is presented. The circuit consisting of low noise amplifier, transconductance amplifier, switching mixer and local oscillator, offers 32.5dB dynamic range of gain control that is digitally configurable. Even under the digital spurious noise, the noise figure in the 40dB maximum gain is 1.8dB and +50dBm IIP2 in 34dB gain. The variation of the input matching versus multiple gains is less than 1dB. The local oscillator to drive the mixer fulfills the stringent phase noise requirement of -153.5 dBc/Hz at 3-MHz. The circuit occupies 1.62mm. The LNA, TA and mixer consume less than 15.3mA at a supply voltage of 1.4V.

F3: Radio architectures and circuits towards 5G

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016

In the last two decades data-rates in wireless communication systems have been increasing exponen... more In the last two decades data-rates in wireless communication systems have been increasing exponentially. This trend is continuing with the fifth generation of wireless systems (5G) that will require peak rates in excess of Gb/s for many users, several hundred thousands of simultaneous connections for massive sensor deployments, and substantially improved spectral efficiency, coverage and signaling. How will the wireless technology deliver these promises? This forum will focus on current state-of-the-art and future directions of the key circuit techniques and system architectures that will enable the 5G revolution, including advanced MIMO, carrier aggregation, mm-Wave radios, large phased-array transceivers, and in-band full duplex operation. Compact low-loss front-end modules for future 5G systems will also be addressed.

A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

TDC-based frequency synthesizer for wireless applications

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers

Abslmef-We analyze phase noise performance and fnrther discuss details of an all-digital PLL that... more Abslmef-We analyze phase noise performance and fnrther discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally-controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phasdfreqnency detector. When implemented in a deep submicron CMOS, the presented architecture appears more advantageous over conventional charge-pump-based PLL's, since it contains only two intrinsic phase noise sources and it does not rely on the fine voltage resolution of analog circuits. The measured close-in phase noise of-862 dBe/Hz and the rms phase ermr of 0.9' are adequate also for CSM applications.

Session 21 overview: Frequency generation techniques: RF subcommittee

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014

VCOs and PLLs are at the heart of communication systems. They are critical for almost all RF syst... more VCOs and PLLs are at the heart of communication systems. They are critical for almost all RF systems such as receivers, transmitters, imagers, and radars. This session starts with three highly digitized frequency synthesizers, including multiplying DLL/PLLs with fractional-N operation and a direct-digital frequency synthesizer. The fourth paper demonstrates a mm-Wave PLL based on a subsampling technique. Interference-tolerant VCOs and PLLs are presented next, followed by a multichannel receiver whose LO frequencies are generated from a single stable FBAR oscillator without a PLL.

Digital RF Processor Serves Plethora Of Cellular Systems

Given the need to cover multiple frequency bands in wireless handsets, the digital RF processor (... more

Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver

Radio Frequency Integrated Circuits IEEE Symposium, 2004

Direct RF sampling has recently been presented (K. Muhammad et al., Proc. IEEE Solid-State Circ. ... more Direct RF sampling has recently been presented (K. Muhammad et al., Proc. IEEE Solid-State Circ. Conf, sec. 15.1, pp. 268-269, 527, 2004; K. Muhammad and R.B. Staszewski, Proc. IEEE Intl. Symp. on Circ. and Sys., sec. ASP-L29.5, 2004) in which an input RF signal is converted to current waveform, down-converted and integrated on a sampling capacitor. A rotating capacitor shares

17.5 All-Digital PLL and GSM/EDGE Transmitter in 90nm CMOS

The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital... more The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, but compli-cates implementation and integration of traditional RF and ana-log circuits. The explosive growth of cellular radios makes it imperative to find digital architectural solutions to these inte-gration problems. A fully-digital frequency synthesizer and GFSK transmitter for a single-chip Bluetooth radio is proposed in [1]. In this paper, a second generation of the digital radio processor (DRP) targeting GSM/EDGE cellular radios is presented. The all-digital PLL (ADPLL) phase-noise performance is significantly improved through architectural and circuit enhancements, and its wideband frequency modulation capability is extended to accommodate wide frequency deviations for EDGE. To complete the polar TX modulation path, a fully digital amplitude modula-tion circuit is added.

RF/analog and digital faceoff — friends or enemies in an RF SoC

International Symposium on VLSI Technology, Systems and Applications, 2010

With the ever-increasing functionalities of cellular smart phones and other communication systems... more With the ever-increasing functionalities of cellular smart phones and other communication systems, RF circuits at multi-GHz frequencies have recently migrated to the state-of-the-art low-cost digital CMOS processes despite their unfriendly analog design environment. The use of digital techniques to assist RF performance is becoming a common practice. However, there is a general fear that a fully integrated RF SoC containing

All-digital PLL and transmitter for mobile phones

by Mitch Entezari, John Wallberg, Kenneth Maggio, Chih-ming Hung, and Oren E Eliezer

IEEE Journal of Solid-State Circuits, 2000

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a ... more We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5 rms phase error, 165 dBc/Hz phase noise at 20 MHz offset, and 10 s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm 2 and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power. Patrick Cruise was born in Dublin, Ireland, and graduated with a first class honors degree in electronic engineering from University College Dublin, Dublin, in 1999. In 1999, he joined the RF division of Parthus Technologies, Dublin, and completed RF-CMOS developments for Bluetooth and GPS technologies. In 2002, he joined Silansys Technologies, Dublin, where he worked on CMOS cellular transceiver design and Digital Audio Broadcast receivers. In 2004, he joined Texas Instruments Incorporated, Dallas, TX, where he is currently engaged in cellular transceiver design on sub-100-nm CMOS. Mitch Entezari received the B.S. and M.S. degrees in electrical engineering from the University of Oklahoma, Norman, in 1984 and 1985, respectively. He began his career with AT&T Bell Laboratories and continued at DSC Communications and Marconi Communications, where he was involved with architecting and developing hardware, ASIC, and firmware for telecommunication applications (Transmission, Multiplexing, Digital Cross-Connect, and Digital Loop Carrier systems) for North American and European markets. He holds five patents in area of next-generation digital loop carrier systems. He joined the Wireless Division of Texas Instruments Incorporated, Dallas, TX, in 2003, where he is involved with developing single-chip next-generation cellular products which use innovative digital methodologies in place of traditional RF design. Khurram Muhammad received B.Sc. degree from the University of Engineering and Technology, Lahore, Pakistan, in 1990, M.Eng.Sc. degree from

A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS

by Robert B Staszewski, Chih-ming Hung, Oren E Eliezer, and Irene Deng

2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009

In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process bas... more In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process based on the digital RF Processor (DRPtrade) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly

A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000

A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-μm NMOS transistor... more A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-μm NMOS transistors in a partially scaled CMOS process. The tuning range and output power level are 600 MHz and ~-22 dBm. The phase noise at a 3-MHz offset is -106 dBc/Hz when the VCO core consumes 24 mW from a 1.5-V supply. This VCO uses a MOS varactor with Q&amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;gt;20

A packaged 2.4 GHz LNA in a 0.15µm CMOS process with 2kV HBM ESD protection

This paper presents the first 2.4 GHz LNA with 2kV HBM ESD protection integrated in a 0.15µm CMOS... more This paper presents the first 2.4 GHz LNA with 2kV HBM ESD protection integrated in a 0.15µm CMOS process. The LNA has been packaged in a standard TQFP48 package and achieves the best overall performance reported to date in a CMOS process at low power. The LNA has a NF of 2.77 dB, an S 21 of 12.1 dB and an IIP3 of +2.4 dBm at a current consumption of 3 mA from a 1.5V supply. A comparison of this LNA with another LNA having a similar schematic and pinout but without ESD protection demonstrates performance degradation due to the ESD structures at high frequencies. The LNA without ESD protection has a NF of 2.36 dB, an S 21 of 14 dB and an IIP3 of -2.2 dBm at the same bias condition.

A low-cost SAW-less GSM/GPRS SoC with integrated connectivity and 32-kHz crystal removal in 55nm

A single-chip SoC integrates GSM/GPRS, connectivity, application processors and peripheral functi... more A single-chip SoC integrates GSM/GPRS, connectivity, application processors and peripheral functions. The SoC requires no external SAW filter and TX output matching for cellular, and 32 kHz crystal is removed. Using a proposed algorithm, the Real-Time Clock (RTC) dissipates 32 μA at 1.1 V. With a 96-dB DR ADC for RX, direct frequency modulation in PLL for TX, and extensive digital assistance, the cellular transceiver size is greatly reduced to 2.2 mm2 in 55nm digital CMOS. -111.4/-110.4 dBm RX LB/HB sensitivity was achieved and TX meets emission requirements. All radios can operate concurrently and meet their specifications.

Chip-package-PCB co-design for optimization of wireless receiver performance

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012

ABSTRACT The co-design of chip-package-PCB is imperative for a modern wireless receiver to achiev... more ABSTRACT The co-design of chip-package-PCB is imperative for a modern wireless receiver to achieve the best circuit performance. This paper proposes simulation-based co-design methodologies which can accurately predict the package and PCB parasitic effects on the low noise amplifier (LNA). To begin with, a chip-package co-design methodology is put forth for the LNA circuit to design its inductive degeneration in package. Then the PCB parasitic effects are included in the circuit simulation as well. The favorable topology of impedance matching network is thus evaluated and the associated SMT values can be determined methodically. By applying the proposed co-design methodologies, the receiver performance is able to be optimized in the circuit design phase.

Transplantation of autologous cultured melanocytes for treatment of large segmental vitiligo

1. J Am Acad Dermatol. 2001 Mar;44(3):543-5. Transplantation of autologous cultured melanocytes f... more

A 15-GHz wireless interconnect implemented in a 0.18-μm CMOS technology using integrated transmitters, receivers, and antennas

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001

Using a 6-meta1, copper 0.18-pm CMOS technology, a 15-GHz on-chip wireless interconnect system ha... more Using a 6-meta1, copper 0.18-pm CMOS technology, a 15-GHz on-chip wireless interconnect system has been demonstrated. The transmission frequency and distance (5.6 mm) of on-chip wireless interconnection have been almost doubled compared to the previously reported system. In addition, an integrated transmitter for on-chip wireless interconnection has been demonstrated. Lastly, the RF potential of CMOS technology for > 10 GHz is assessed.

Drastic population fluctuations explain the rapid extinction of the passenger pigeon

Proceedings of the National Academy of Sciences of the United States of America, Jan 22, 2014

To assess the role of human disturbances in species' extinction requires an understanding of ... more To assess the role of human disturbances in species' extinction requires an understanding of the species population history before human impact. The passenger pigeon was once the most abundant bird in the world, with a population size estimated at 3-5 billion in the 1800s; its abrupt extinction in 1914 raises the question of how such an abundant bird could have been driven to extinction in mere decades. Although human exploitation is often blamed, the role of natural population dynamics in the passenger pigeon's extinction remains unexplored. Applying high-throughput sequencing technologies to obtain sequences from most of the genome, we calculated that the passenger pigeon's effective population size throughout the last million years was persistently about 1/10,000 of the 1800's estimated number of individuals, a ratio 1,000-times lower than typically found. This result suggests that the passenger pigeon was not always super abundant but experienced dramatic populat...

On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process

2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software, 2008

In this paper, we examine several proposed power combining topologies for RF power amplifiers (PA... more In this paper, we examine several proposed power combining topologies for RF power amplifiers (PA). These structures are simulated in a generic 45 nm CMOS process to allow for comparison of their process portability distinguishing necessary adaptations for reasonable performance. The power combining structures are compared and explored by means of electromagnetic (EM) simulations to help establish an attainable baseline

The de novo assembly of mitochondrial genomes of the extinct passenger pigeon (Ectopistes migratorius) with next generation sequencing

PloS one, 2013

The information from ancient DNA (aDNA) provides an unparalleled opportunity to infer phylogeneti... more The information from ancient DNA (aDNA) provides an unparalleled opportunity to infer phylogenetic relationships and population history of extinct species and to investigate genetic evolution directly. However, the degraded and fragmented nature of aDNA has posed technical challenges for studies based on conventional PCR amplification. In this study, we present an approach based on next generation sequencing to efficiently sequence the complete mitochondrial genome (mitogenome) of two extinct passenger pigeons (Ectopistes migratorius) using de novo assembly of massive short (90 bp), paired-end or single-end reads. Although varying levels of human contamination and low levels of postmortem nucleotide lesion were observed, they did not impact sequencing accuracy. Our results demonstrated that the de novo assembly of shotgun sequence reads could be a potent approach to sequence mitogenomes, and offered an efficient way to infer evolutionary history of extinct species.

A 1 . 8 dB NF Receiver front-end for GSM / GPRS in a 90 nm Digital CMOS

An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90nm digital CMOS technology is... more An RF receiver front-end for a GSM/GPRS radio system-on-chip in a 90nm digital CMOS technology is presented. The circuit consisting of low noise amplifier, transconductance amplifier, switching mixer and local oscillator, offers 32.5dB dynamic range of gain control that is digitally configurable. Even under the digital spurious noise, the noise figure in the 40dB maximum gain is 1.8dB and +50dBm IIP2 in 34dB gain. The variation of the input matching versus multiple gains is less than 1dB. The local oscillator to drive the mixer fulfills the stringent phase noise requirement of -153.5 dBc/Hz at 3-MHz. The circuit occupies 1.62mm. The LNA, TA and mixer consume less than 15.3mA at a supply voltage of 1.4V.

F3: Radio architectures and circuits towards 5G

2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016

In the last two decades data-rates in wireless communication systems have been increasing exponen... more In the last two decades data-rates in wireless communication systems have been increasing exponentially. This trend is continuing with the fifth generation of wireless systems (5G) that will require peak rates in excess of Gb/s for many users, several hundred thousands of simultaneous connections for massive sensor deployments, and substantially improved spectral efficiency, coverage and signaling. How will the wireless technology deliver these promises? This forum will focus on current state-of-the-art and future directions of the key circuit techniques and system architectures that will enable the 5G revolution, including advanced MIMO, carrier aggregation, mm-Wave radios, large phased-array transceivers, and in-band full duplex operation. Compact low-loss front-end modules for future 5G systems will also be addressed.

A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

TDC-based frequency synthesizer for wireless applications

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers

Abslmef-We analyze phase noise performance and fnrther discuss details of an all-digital PLL that... more Abslmef-We analyze phase noise performance and fnrther discuss details of an all-digital PLL that is used in a commercial 130 nm CMOS single-chip Bluetooth radio. The frequency synthesizer uses a digitally-controlled oscillator with a digital loop filter and a time-to-digital converter that acts as a phasdfreqnency detector. When implemented in a deep submicron CMOS, the presented architecture appears more advantageous over conventional charge-pump-based PLL's, since it contains only two intrinsic phase noise sources and it does not rely on the fine voltage resolution of analog circuits. The measured close-in phase noise of-862 dBe/Hz and the rms phase ermr of 0.9' are adequate also for CSM applications.

Session 21 overview: Frequency generation techniques: RF subcommittee

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014

VCOs and PLLs are at the heart of communication systems. They are critical for almost all RF syst... more VCOs and PLLs are at the heart of communication systems. They are critical for almost all RF systems such as receivers, transmitters, imagers, and radars. This session starts with three highly digitized frequency synthesizers, including multiplying DLL/PLLs with fractional-N operation and a direct-digital frequency synthesizer. The fourth paper demonstrates a mm-Wave PLL based on a subsampling technique. Interference-tolerant VCOs and PLLs are presented next, followed by a multichannel receiver whose LO frequencies are generated from a single stable FBAR oscillator without a PLL.

Digital RF Processor Serves Plethora Of Cellular Systems

Given the need to cover multiple frequency bands in wireless handsets, the digital RF processor (... more

Joint common mode voltage and differential offset voltage control scheme in a low-IF receiver

Radio Frequency Integrated Circuits IEEE Symposium, 2004

Direct RF sampling has recently been presented (K. Muhammad et al., Proc. IEEE Solid-State Circ. ... more Direct RF sampling has recently been presented (K. Muhammad et al., Proc. IEEE Solid-State Circ. Conf, sec. 15.1, pp. 268-269, 527, 2004; K. Muhammad and R.B. Staszewski, Proc. IEEE Intl. Symp. on Circ. and Sys., sec. ASP-L29.5, 2004) in which an input RF signal is converted to current waveform, down-converted and integrated on a sampling capacitor. A rotating capacitor shares

17.5 All-Digital PLL and GSM/EDGE Transmitter in 90nm CMOS

The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital... more The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, but compli-cates implementation and integration of traditional RF and ana-log circuits. The explosive growth of cellular radios makes it imperative to find digital architectural solutions to these inte-gration problems. A fully-digital frequency synthesizer and GFSK transmitter for a single-chip Bluetooth radio is proposed in [1]. In this paper, a second generation of the digital radio processor (DRP) targeting GSM/EDGE cellular radios is presented. The all-digital PLL (ADPLL) phase-noise performance is significantly improved through architectural and circuit enhancements, and its wideband frequency modulation capability is extended to accommodate wide frequency deviations for EDGE. To complete the polar TX modulation path, a fully digital amplitude modula-tion circuit is added.

RF/analog and digital faceoff — friends or enemies in an RF SoC

International Symposium on VLSI Technology, Systems and Applications, 2010

With the ever-increasing functionalities of cellular smart phones and other communication systems... more With the ever-increasing functionalities of cellular smart phones and other communication systems, RF circuits at multi-GHz frequencies have recently migrated to the state-of-the-art low-cost digital CMOS processes despite their unfriendly analog design environment. The use of digital techniques to assist RF performance is becoming a common practice. However, there is a general fear that a fully integrated RF SoC containing

All-digital PLL and transmitter for mobile phones

by Mitch Entezari, John Wallberg, Kenneth Maggio, Chih-ming Hung, and Oren E Eliezer

IEEE Journal of Solid-State Circuits, 2000

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a ... more We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5 rms phase error, 165 dBc/Hz phase noise at 20 MHz offset, and 10 s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm 2 and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power. Patrick Cruise was born in Dublin, Ireland, and graduated with a first class honors degree in electronic engineering from University College Dublin, Dublin, in 1999. In 1999, he joined the RF division of Parthus Technologies, Dublin, and completed RF-CMOS developments for Bluetooth and GPS technologies. In 2002, he joined Silansys Technologies, Dublin, where he worked on CMOS cellular transceiver design and Digital Audio Broadcast receivers. In 2004, he joined Texas Instruments Incorporated, Dallas, TX, where he is currently engaged in cellular transceiver design on sub-100-nm CMOS. Mitch Entezari received the B.S. and M.S. degrees in electrical engineering from the University of Oklahoma, Norman, in 1984 and 1985, respectively. He began his career with AT&T Bell Laboratories and continued at DSC Communications and Marconi Communications, where he was involved with architecting and developing hardware, ASIC, and firmware for telecommunication applications (Transmission, Multiplexing, Digital Cross-Connect, and Digital Loop Carrier systems) for North American and European markets. He holds five patents in area of next-generation digital loop carrier systems. He joined the Wireless Division of Texas Instruments Incorporated, Dallas, TX, in 2003, where he is involved with developing single-chip next-generation cellular products which use innovative digital methodologies in place of traditional RF design. Khurram Muhammad received B.Sc. degree from the University of Engineering and Technology, Lahore, Pakistan, in 1990, M.Eng.Sc. degree from

A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS

by Robert B Staszewski, Chih-ming Hung, Oren E Eliezer, and Irene Deng

2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009

In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process bas... more In this paper we present a quad-band single-chip GSM/GPRS radio in 90 nm digital CMOS process based on the digital RF Processor (DRPtrade) technology. This chip integrates all functions from physical layer to the protocol stack and peripheral support in a single chip RF SoC. The transmitter uses a low-area small-signal digital polar architecture merging amplitude and phase information directly

A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000

A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-μm NMOS transistor... more A 25.9-GHz voltage-controlled oscillator (VCO) has been demonstrated using 0.1-μm NMOS transistors in a partially scaled CMOS process. The tuning range and output power level are 600 MHz and ~-22 dBm. The phase noise at a 3-MHz offset is -106 dBc/Hz when the VCO core consumes 24 mW from a 1.5-V supply. This VCO uses a MOS varactor with Q&amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;gt;20

A packaged 2.4 GHz LNA in a 0.15µm CMOS process with 2kV HBM ESD protection

This paper presents the first 2.4 GHz LNA with 2kV HBM ESD protection integrated in a 0.15µm CMOS... more This paper presents the first 2.4 GHz LNA with 2kV HBM ESD protection integrated in a 0.15µm CMOS process. The LNA has been packaged in a standard TQFP48 package and achieves the best overall performance reported to date in a CMOS process at low power. The LNA has a NF of 2.77 dB, an S 21 of 12.1 dB and an IIP3 of +2.4 dBm at a current consumption of 3 mA from a 1.5V supply. A comparison of this LNA with another LNA having a similar schematic and pinout but without ESD protection demonstrates performance degradation due to the ESD structures at high frequencies. The LNA without ESD protection has a NF of 2.36 dB, an S 21 of 14 dB and an IIP3 of -2.2 dBm at the same bias condition.

A low-cost SAW-less GSM/GPRS SoC with integrated connectivity and 32-kHz crystal removal in 55nm

A single-chip SoC integrates GSM/GPRS, connectivity, application processors and peripheral functi... more A single-chip SoC integrates GSM/GPRS, connectivity, application processors and peripheral functions. The SoC requires no external SAW filter and TX output matching for cellular, and 32 kHz crystal is removed. Using a proposed algorithm, the Real-Time Clock (RTC) dissipates 32 μA at 1.1 V. With a 96-dB DR ADC for RX, direct frequency modulation in PLL for TX, and extensive digital assistance, the cellular transceiver size is greatly reduced to 2.2 mm2 in 55nm digital CMOS. -111.4/-110.4 dBm RX LB/HB sensitivity was achieved and TX meets emission requirements. All radios can operate concurrently and meet their specifications.

Chip-package-PCB co-design for optimization of wireless receiver performance

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012

ABSTRACT The co-design of chip-package-PCB is imperative for a modern wireless receiver to achiev... more ABSTRACT The co-design of chip-package-PCB is imperative for a modern wireless receiver to achieve the best circuit performance. This paper proposes simulation-based co-design methodologies which can accurately predict the package and PCB parasitic effects on the low noise amplifier (LNA). To begin with, a chip-package co-design methodology is put forth for the LNA circuit to design its inductive degeneration in package. Then the PCB parasitic effects are included in the circuit simulation as well. The favorable topology of impedance matching network is thus evaluated and the associated SMT values can be determined methodically. By applying the proposed co-design methodologies, the receiver performance is able to be optimized in the circuit design phase.

Transplantation of autologous cultured melanocytes for treatment of large segmental vitiligo

1. J Am Acad Dermatol. 2001 Mar;44(3):543-5. Transplantation of autologous cultured melanocytes f... more

A 15-GHz wireless interconnect implemented in a 0.18-μm CMOS technology using integrated transmitters, receivers, and antennas

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185), 2001

Using a 6-meta1, copper 0.18-pm CMOS technology, a 15-GHz on-chip wireless interconnect system ha... more Using a 6-meta1, copper 0.18-pm CMOS technology, a 15-GHz on-chip wireless interconnect system has been demonstrated. The transmission frequency and distance (5.6 mm) of on-chip wireless interconnection have been almost doubled compared to the previously reported system. In addition, an integrated transmitter for on-chip wireless interconnection has been demonstrated. Lastly, the RF potential of CMOS technology for > 10 GHz is assessed.

Drastic population fluctuations explain the rapid extinction of the passenger pigeon

Proceedings of the National Academy of Sciences of the United States of America, Jan 22, 2014

To assess the role of human disturbances in species' extinction requires an understanding of ... more To assess the role of human disturbances in species' extinction requires an understanding of the species population history before human impact. The passenger pigeon was once the most abundant bird in the world, with a population size estimated at 3-5 billion in the 1800s; its abrupt extinction in 1914 raises the question of how such an abundant bird could have been driven to extinction in mere decades. Although human exploitation is often blamed, the role of natural population dynamics in the passenger pigeon's extinction remains unexplored. Applying high-throughput sequencing technologies to obtain sequences from most of the genome, we calculated that the passenger pigeon's effective population size throughout the last million years was persistently about 1/10,000 of the 1800's estimated number of individuals, a ratio 1,000-times lower than typically found. This result suggests that the passenger pigeon was not always super abundant but experienced dramatic populat...

On the portability and performance of fully monolithic transformer structures for RF power amplfiers in standard CMOS process

2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software, 2008

In this paper, we examine several proposed power combining topologies for RF power amplifiers (PA... more In this paper, we examine several proposed power combining topologies for RF power amplifiers (PA). These structures are simulated in a generic 45 nm CMOS process to allow for comparison of their process portability distinguishing necessary adaptations for reasonable performance. The power combining structures are compared and explored by means of electromagnetic (EM) simulations to help establish an attainable baseline

The de novo assembly of mitochondrial genomes of the extinct passenger pigeon (Ectopistes migratorius) with next generation sequencing

PloS one, 2013

The information from ancient DNA (aDNA) provides an unparalleled opportunity to infer phylogeneti... more The information from ancient DNA (aDNA) provides an unparalleled opportunity to infer phylogenetic relationships and population history of extinct species and to investigate genetic evolution directly. However, the degraded and fragmented nature of aDNA has posed technical challenges for studies based on conventional PCR amplification. In this study, we present an approach based on next generation sequencing to efficiently sequence the complete mitochondrial genome (mitogenome) of two extinct passenger pigeons (Ectopistes migratorius) using de novo assembly of massive short (90 bp), paired-end or single-end reads. Although varying levels of human contamination and low levels of postmortem nucleotide lesion were observed, they did not impact sequencing accuracy. Our results demonstrated that the de novo assembly of shotgun sequence reads could be a potent approach to sequence mitogenomes, and offered an efficient way to infer evolutionary history of extinct species.