DSP para el Control de Electrónica de Potencia

Modulo7
Introducción a los Módulos ePWMs de DSCs C2000

G. A. Magallán
Fuentes utilizadas: Teaching Materials F2833x - 2010 TI - Module-07
TMS320F2837xD Microcontroller Workshop Rev2.0 2018

1
2022
 DSP para el Control de Electrónica de Potencia

TEMARIO

• Base de tiempo del modulo ePWM

• sincronización entre módulos
• Modos de cuenta
• Modulación PWM y PhaseShift y PWM Senoidal
• Resolución Efectiva en amplitud
• Modulo de alta resolución HRPWM
• Eventos generadores de interrupción y SOC
• Chopper
• Modulo de Chopper
• Protecciones Trip Zone
• Modulo de Captura
• Modulo de encoder de cuadratura

2
Modulo 7
 DSP para el Control de Electrónica de Potencia

Modulo ePWM - Time Based Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0
3
Modulo 7
 ePWM modos de cuenta
TBCTR

TBPRD
Asymmetrical
Waveform

Count Up Mode
TBCTR

TBPRD
Asymmetrical
Waveform

Count Down Mode

TBCTR

TBPRD

Symmetrical
Waveform

Count Up and Down Mode

4
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 Sincronización de fase entre modulos ePWM
Ext. SyncIn
(optional)

Phase
=0°
En
o o 
SyncIn
EPWM1A
o
CTR=zero o
CTR=CMPB o o EPWM1B
X o
SyncOut
To eCAP1
SyncIn
Phase
=120°
En
o o 
SyncIn
EPWM2A =120°
o
CTR=zero o
CTR=CMPB o o EPWM2B
X o
SyncOut

Phase
=240°
En
o o 
SyncIn
EPWM3A
=120°

o
CTR=zero o
CTR=CMPB o o EPWM3B
X o
SyncOut =240°
5
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Sincronización de fase entre modulos ePWM - F2837xD

6
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Eventos, y Sincronización de fase SYNCI

7
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 Registros de configuración

Name Description Structure

TBCTL Time-Base Control EPwmxRegs.TBCTL.all =
TBSTS Time-Base Status EPwmxRegs.TBSTS.all =
TBPHS Time-Base Phase EPwmxRegs.TBPHS =
TBCTR Time-Base Counter EPwmxRegs.TBCTR =
TBPRD Time-Base Period EPwmxRegs.TBPRD =

8
Modulo 7
 ePWM RegistroTBCTL : Time Base Control

Parte alta del Registro:

Phase Direction
0 = count down after sync
1 = count up after sync TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV)

15 - 14 13 12 - 10 9-7
FREE_SOFT PHSDIR CLKDIV HSPCLKDIV

Emulation Halt Behavior TB Clock Prescale High Speed TB

00 = stop after next CTR inc/dec 000 = /1 (default) Clock Prescale
01 = stop when: 001 = /2 000 = /1
Up Mode; CTR = PRD 010 = /4 001 = /2 (default)
Down Mode; CTR = 0 011 = /8 010 = /4
Up/Down Mode; CTR = 0 100 = /16 011 = /6
1x = free run (do not stop) 101 = /32 100 = /8
110 = /64 101 = /10
111 = /128 110 = /12
111 = /14
9
Modulo 7
 ePWM RegistroTBCTL : Time Base Control

Parte baja del registro:

Counter Mode
00 = count up
Software Force Sync Pulse 01 = count down
0 = no action 10 = count up and down
1 = force one-time sync 11 = stop – freeze (default)

6 5-4 3 2 1-0
SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE

Sync Output Select Period Shadow Load Phase Reg. Enable

(source of EPWMxSYNC0 signal) 0 = load on CTR = 0 0 = disable
00 = EPWMxSYNCI 1 = load immediately 1 = CTR = TBPHS on
01 = CTR = 0 EPWMxSYNCI signal
10 = CTR = CMPB
11 = disable SyncOut

10
Modulo 7
 ePWM RegistroTBSTS: Time Base Status

Proporciona flags del estado del modulo epwm

Counter Max Latched Counter Direction

0 = max value not reached 0 = CTR counting down
1 = CTR = 0xFFFF (write 1 to clear) 1 = CTR counting up

15 - 3 2 1 0
reserved CTRMAX SYNCI CTRDIR

External Input Sync Latched

0 = no sync event occurred
1 = sync has occurred (write 1 to clear)

11
Modulo 7
Proyecto:
Generar una señal de 1kHz ciclo de trabajo del
50% utilizando el modulo ePWM1A (utilizar eventos
de counter=cero y counter=período)

• Registros involucrados:
• TBPRD: define el periodo del PWM
• TBCTL: configura el modo y el prescaler
• AQCTLA: define la forma y polaridad del ePWM1A

Uso de la estructura EPwm1Regs

Calculo del periodo si es UpDown:

1 TPWM
TBPRD = 
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV

12
Modulo 7
Proyecto:
Generar un sistema trifásico con señales cuadradas
de 1kHz , ciclo de trabajo del 50%, utilizando las
salidas ePWM1A, ePWM2A, ePWM3A desfasadas
120° entre si.
• Registros involucrados:
• TBPRD: define el periodo del PWM
• TBCTL: configura el modo y el prescaler
• AQCTLA: define la forma y polaridad
•TBPHS: registro para establecer la fase

Calculo del periodo (si es UpDown):

1 TPWM
TBPRD = 
2 TSYSCLKOUT  CLKDIV  HSPCLKDIV

13
Modulo 7
 Modulación por ancho de pulso

• Frecuencia de portadora fija

• Amplitud de pulso fija
• Ancho de pulso proporcional al valor instantáneo de la
amplitud de señal
• Energía de PWM ≈ energía de la señal a sintetizar

t t
T
Señal original Representación PWM

14
Modulo 7
 ¿Porqué usar PWM en llaves de potencia?

Voltages o corrientes deseados de salida son conocidos

Los dispositivos o llaves de conmutación son transistores (BJTs, MosFets,
Igbts).
Difícil de controlar en su región lineal
Fácil de controlar en corte y saturación
PWM es una señal digital ➔ fácil de hacer con un DSC

DC Supply DC Supply

? PWM
Señal PWM approx.
deseada of desired
signal
Señal de base desconocida Señal conocida en la base usando
PWM
15
Modulo 7
 ePWM Unidad de Comparación

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCI
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0
16
Modulo 7
 ePWM Unidad de Comparación
TBCTR  = los eventos de comparación alimentan al Action Qualifier Module

  
TBPRD
CMPA
CMPB    Asymmetrical
Waveform

Count Up Mode
TBCTR

TBPRD
CMPA
CMPB
   Asymmetrical
Waveform

Count Down Mode

TBCTR

TBPRD
CMPA
CMPB    
   Symmetrical
Waveform

Count Up and Down Mode

17
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ePWM - Registros de la unidad de comparación

Name Description Structure

CMPCTL Compare Control EPwmxRegs.CMPCTL.all =
CMPA Compare A EPwmxRegs.CMPA =
CMPB Compare B EPwmxRegs.CMPB =

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 ePWM Compare Control Register
Control de los registros “shadows”

CMPA and CMPB Shadow Full Flag

(bit automatically clears on load)
0 = shadow not full
1 = shadow full

15 - 10 9 8 7
reserved SHDWBFULL SHDWAFULL reserved

6 5 4 3-2 1-0
SHDWBMODE reserved SHDWAMODE LOADBMODE LOADAMODE

CMPA and CMPB Operating Mode CMPA and CMPB Shadow Load Mode
0 = shadow mode; 00 = load on CTR = 0
double buffer w/ shadow register 01 = load on CTR = PRD
1 = immediate mode; 10 = load on CTR = 0 or PRD
shadow register not used 11 = freeze (no load possible)

Modulo 7
 ePWM Action Qualifier Module
CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0

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 ePWM Action Qualifier Actions
Time-Base Counter equals: EPWM
S/W Output
Force Actions
Zero CMPA CMPB TBPRD

SW Z CA CB P
X X X X X Do Nothing

SW Z CA CB P
     Clear Low

SW Z CA CB P
     Set High

SW Z CA CB P
T T T T T Toggle

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Modulación independiente en EPWMA y B

TBCTR

 
TBPRD

 
Z P CB CA Z CB CA Z P
 X X   X   X

EPWMA

Z P CB CA Z P CB CA Z P
 X  X  X  X  X

EPWMB

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 Pulso móvil en EPWMA

TBCTR

 
TBPRD

 
CA CB CA CB
   

EPWMA

Z Z Z
T T T

EPWMB

Modulo 7
 Modulación independiente simétrica
en EPWMA y B
TBCTR

TBPRD
   
   
CA CA CA CA
   

EPWMA

CB CB CB CB
   

EPWMB

Modulo 7
ePWM – Registros del modulo Action Qualifier

Name Description Structure

AQCTLA AQ Control Output A EPwmxRegs.AQCTLA.all =
AQCTLB AQ Control Output B EPwmxRegs.AQCTLB.all =
AQSFRC AQ S/W Force EPwmxRegs.AQSFRC.all =
AQCSFRC AQ Cont. S/W Force EPwmxRegs.AQCSFRC.all =

Modulo 7
 Registro de control del Action Qualifier
EPwmxRegs.AQCTLy (y = A o B)

Action when Action when

CTR = CMPB CTR = CMPA Action when
on UP Count on UP Count CTR = 0

15 - 12 11 - 10 9-8 7-6 5-4 3-2 1-0

reserved CBD CBU CAD CAU PRD ZRO

Action when Action when Action when

CTR = CMPB CTR = CMPA CTR = PRD
on DOWN Count on DOWN Count

00 = do nothing (action disabled)

01 = clear (low)
10 = set (high)
11 = toggle (low → high; high → low)

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 Action Qualifier- Registro de forzado por software
EPwmxRegs.AQSFRC

One-Time S/W Force on Output B / A

0 = no action
1 = single s/w force event

15 - 8 7-6 5 4-3 2 1-0

reserved RLDCSF OTSFB ACTSFB OTSFA ACTSFA

AQSFRC Shadow Reload Options Action on One-Time S/W Force B / A

00 = load on event CTR = 0 00 = do nothing (action disabled)
01 = load on event CTR = PRD 01 = clear (low)
10 = load on event CTR = 0 or CTR = PRD 10 = set (high)
11 = load immediately (from active reg.) 11 = toggle (low → high; high → low)

Modulo 7
Bits de forzado continuo por software
EPwmxRegs.AQCSFRC

15 - 4 3-2 1-0
reserved CSFB CSFA

Continuous S/W Force on Output B / A

00 = forcing disabled
01 = force continuous low on output
10 = force continuous high on output
11 = forcing disabled

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Resolución efectiva de PWM en función
del período (pizarrón)

Modulo 7
HRPWM - Modulo de alta resolución de PWM
Cuando la resolución cae por debajo de 9 -10bits

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Modulo 7
 MEP: Micro Edge Positioner
Ej. MEPs 180ps (28335) y 100Mhz Sysclock, (Ójo en el 28379 es de 150ps)

Modulo 7
 Lab 7_3: Señal de1 KHz con PWM 0-100% en
ePWM1A

Objetivo:
• Generar una onda señal cuadrada de1 KHz con el modulo ePWM1A
con ciclo de trabajo variable de 0 a 100%
• Verificar con osciloscopio

• Registros involucrados:
• TBPRD: define el periodo de la señal
• TBCTL: modo de operación y prescaler
• CMPA: control del ancho de pulso para ePWM1A
• AQCTLA: define flancos y polaridad de la forma de salida
en ePWM1A

Modulo 7
 Lab 7_4: señales complementarias de 1KHz en
ePWM1A y ePWM1B
Objetivo:
• Generar una señal de onda cuadrada de 1 KHz en ePWM1A con ciclo
de trabajo variable entre 0 y 100%
• Generar una señal complementaria en ePWM1B
• Verificar con osciloscopio

• Registros involucrados:

• TBPRD: define el periodo de la señal

• TBCTL: modo de operación y prescaler
• CMPA: control del ancho de pulso para ePWM1A
• AQCTLA: define flancos y polaridad de la forma de salida
en ePWM1A
•AQCTLB: define flancos y polaridad de la forma de salida en
ePWM1B

Modulo 7
 Lab 7_5: Modulación independiente en ePWMA
y ePWMB
TBCTR

TBPRD
   
   
CA CA CA CA
   

EPWMA

CB CB CB CB
   

EPWMB

Modulo 7
 Inversor fuente de voltage
Upper & lower
devices can not
be turned on
simultaneously
(dead band)
PWM signal is
applied between
gate and source + + +

DC bus
capacitor - - - Three phase
outputs to drive
the motor
terminals

Power
Switching
Devices
Modulo 7
 Necesidad de Dead-Band
Tiempos Muertos
+Vcc

Señales de gates a la carga

PWM complementarias

 En gral los transistores encienden mas rápido de lo que se apagan

turn-on turn-off
 Cortocircuito (Shoot Trough) si las señales de los gates
están simultaneamente encendidas o si es poco el tiempo muerto.

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 ePWM Modulo Dead-Band
CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0

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 ePWM- Diagrama del Módulo de Dead-Band

PWMxA - IN

Rising


0


Edge 0  S1 PWMxA
0 Delay  S2 RED 
 S4  

1
 In
(10-bit
Out
 
1
1

counter)

Falling


Edge 0


0 Delay  S3 FED 1
 S5   S0 PWMxB

1
 In
(10-bit
Out
 
1 
0


counter)
IN-MODE POLSEL OUT-MODE

PWMxB - IN

Modulo 7
 ePWM- Registros del Modulo Dead-Band

Name Description Structure

DBCTL Dead-Band Control EPwmxRegs.DBCTL.all =
DBRED 10-bit Rising Edge Delay EPwmxRegs.DBRED =
DBFED 10-bit Falling Edge Delay EPwmxRegs.DBFED =

Rising Edge Delay = TTBCLK x DBRED

Falling Edge Delay = TTBCLK x DBFED

Modulo 7
 ePWM- Registro de Control de Dead Band

Polarity Select
00 = active high
01 = active low complementary (RED)
10 = active high complementary (FED)
11 = active low

15 - 6 5-4 3-2 1-0

reserved IN_MODE POLSEL OUT_MODE

In-Mode Control Out-Mode Control

00 = PWMxA is source for RED and FED 00 = disabled (DBM bypass)
01 = PWMxA is source for FED 01 = PWMxA = no delay
PWMxB is source for RED PWMxB = FED
10 = PWMxA is source for RED 10 = PWMxA = RED
PWMxB is source for FED PWMxB = no delay
11 = PWMxB is source for RED and FED 11 = RED & FED (DBM fully enabled)

Modulo 7
 Lab 7_6: Uso de Dead-Band para
ePWM1A y ePWM1B
Objetivo:
• Agregar un delay en los flancos ascendentes de un par de
señales complementarias ePWM1A y ePWM1B
• Calificación de salida : Active High Complementary (AHC)
Mode
• La entrada a la unidad de dead-band será ePWM1A
• La unidad de dead-band generará las señales de salida
ePWM1A y ePWM1B

• Registros involucrados:

• DBRED: Dead Band Unit Rising Edge Delay

• DBFED: Dead Band Unit Falling Edge Delay
• DBCTL: Dead Band Unit Control Register
Modulo 7
 ePWM Modulo de Chopper
CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0

Modulo 7
 Propósito de la unidad de chopper en el
modulo ePWM
Permite generar una portadora de alta frecuencia que modula
la señal PWM luego que es entregada por las unidades de
Action Qualifier y Dead-Band.
Ej. Es utilizada para enviar señales a transformadores de pulso que
forman parte de drivers para el disparo de llaves de potencia.

Las funciones claves de este sub-modulo son:

• Frecuencia programable del “chopeado” (portadora)

Ancho del primer pulso programable
• Ciclo de trabajo programmable para el Segundo y
subsecuentes pulsos.
• Puede ser completamente desactivado (bypassed) si no
se necesita.
Modulo 7
Forma de onda PWM con modulación de chopper

EPWMxA

EPWMxB

CHPFREQ

EPWMxA

EPWMxB

Programmable
Pulse Width
OSHT (OSHTWTH)

Sustaining
EPWMxA Pulses

With One-Shot Pulse on EPWMxA and/or EPWMxB

 Registro de la unidad de Chopper

Name Description Structure

PCCTL PWM-Chopper Control EPwmxRegs.PCCTL.all =

Modulo 7
 ePWM Registro de control del chopper
EPwmxRegs.PCCTL

Chopper Clk Duty Cycle Chopper Clk Freq.

000 = 1/8 (12.5%) 000 = SYSCLKOUT/8  1
001 = 2/8 (25.0%) 001 = SYSCLKOUT/8  2
010 = 3/8 (37.5%) 010 = SYSCLKOUT/8  3
011 = 4/8 (50.0%) 011 = SYSCLKOUT/8  4
100 = 5/8 (62.5%) 100 = SYSCLKOUT/8  5 Chopper Enable
101 = 6/8 (75.0%) 101 = SYSCLKOUT/8  6 0 = disable (bypass)
110 = 7/8 (87.5%) 110 = SYSCLKOUT/8  7 1 = enable
111 = reserved 111 = SYSCLKOUT/8  8

15 - 11 10 - 8 7-5 4-1 0
reserved CHPDUTY CHPFREQ OSHTWTH CHPEN

One-Shot Pulse Width

0000 = 8 / SYSCLKOUT 1000 = 72 / SYSCLKOUT
0001 = 16 / SYSCLKOUT 1001 = 80 / SYSCLKOUT
0010 = 24 / SYSCLKOUT 1010 = 88 / SYSCLKOUT
0011 = 32 / SYSCLKOUT 1011 = 96 / SYSCLKOUT
0100 = 40 / SYSCLKOUT 1100 = 104 / SYSCLKOUT
0101 = 48 / SYSCLKOUT 1101 = 112 / SYSCLKOUT
0110 = 56 / SYSCLKOUT 1110 = 120 / SYSCLKOUT
0111 = 64 / SYSCLKOUT 1111 = 128 / SYSCLKOUT
Modulo 7
 ePWM Unidad de Trip-Zone
CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
TBCLK Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0 EPWMxB
PCCTL . 10 - 0
TZy
TZSEL . 15 - 0

Modulo 7
 Características del sub-modulo deTrip-Zone
 El Trip-Zone tiene una lógica rápida e independiente de clock para poner en
un estado particular los pines ePWMxA/B.
 La latencia de interrupciones podría no proteger el hardware cuando la
respuesta a condiciones de sobrecorriente o cortocircuito son programadas
dentro de una ISR.
 Soporta: #1) one-shot trip para grandes cortocircuitos o condiciones de
sobrecorrientes.
#2) cycle-by-cycle trip para operación de limite de corriente.
EPWM1A
Over
Current DSP EPWM1B
EPWM2A
P
Sensors core W
EPWM2B M
EPWM3A
TZ1 EPWMxTZINT EPWM3B O
TZ2 Cycle-by-Cycle U
EPWM4A
TZ3 Mode EPWM4B T
P
TZ4 EPWM5A U
TZ5 One-Shot EPWM5B T
TZ6 Mode EPWM6A S
EPWM6B

Modulo 7
ePWM Registros del sub-modulo deTrip-Zone

Name Description Structure

TZCTL Trip-Zone Control EPwmxRegs.TZCTL.all =
TZSEL Trip-Zone Select EPwmxRegs.TZSEL.all =
TZEINT Enable Interrupt EPwmxRegs.TZEINT.all =
TZFLG Trip-Zone Flag EPwmxRegs.TZFLG.all =
TZCLR Trip-Zone Clear EPwmxRegs.TZCLR.all =
TZFRC Trip-Zone Force EPwmxRegs.TZFRC.all =

Modulo 7
ePWM Registro de Control del Trip-Zone
EPwmxRegs.TZCTL

15 - 4 3-2 1-0
reserved TZB TZA

TZ1 to TZ6 Action on EPWMxB / EPWMxA

00 = high impedance
01 = force high
10 = force low
11 = do nothing (disable)

Modulo 7
ePWM Registro Selector deTrip-Zone
EPwmxRegs.TZSEL

One-Shot Trip Zone

(event only cleared under S/W
control; remains latched)
0 = disable as trip source
1 = enable as trip source

15 - 14 13 12 11 10 9 8
reserved OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1

7-6 5 4 3 2 1 0
reserved CBC6 CBC5 CBC4 CBC3 CBC2 CBC1

Cycle-by-Cycle Trip Zone

(event cleared when CTR = 0;
i.e. cleared every PWM cycle)
0 = disable as trip source
1 = enable as trip source

Modulo 7
ePWM Registro Habilitador de Interrupción
deTrip-Zone

EPwmxRegs.TZEINT

15 - 3 2 1 0
reserved OST CBC reserved

One-Shot Cycle-by-Cycle
Interrupt Enable Interrupt Enable
0 = disable 0 = disable
1 = enable 1 = enable

Modulo 7
Disparo de interrupciones y SOC en
eventos del modulo de ePWM

Modulo 7
 TBCTR

TBPRD
   
CMPB
CMPA    
EPWMA

EPWMB

CTR = 0

CTR = PRD
CTRU = CMPA

CTRD = CMPA
CTRU = CMPB

CTRD = CMPB

Modulo 7
ePWM Registros para el disparo de
eventos

Name Description Structure

ETSEL Event-Trigger Selection EPwmxRegs.ETSEL.all =
ETPS Event-Trigger Pre-Scale EPwmxRegs.ETPS.all =
ETFLG Event-Trigger Flag EPwmxRegs.ETFLG.all =
ETCLR Event-Trigger Clear EPwmxRegs.ETCLR.all =
ETFRC Event-Trigger Force EPwmxRegs.ETFRC.all =

Modulo 7
ePWM Event-Trigger Selection Register
EPwmxRegs.ETSEL

Enable SOCB / A Enable EPWMxINT

0 = disable 0 = disable
1 = enable 1 = enable

15 14 - 12 11 10 - 8 7-4 3 2-0
SOCBEN SOCBSEL SOCAEN SOCASEL reserved INTEN INTSEL

EPWMxSOCB / A Select EPWMxINT Select

000 = reserved 000 = reserved
001 = CTR = 0 001 = CTR = 0
010 = CTR = PRD 010 = CTR = PRD
011 = reserved 011 = reserved
100 = CTRU = CMPA 100 = CTRU = CMPA
101 = CTRD = CMPA 101 = CTRD = CMPA
110 = CTRU = CMPB 110 = CTRU = CMPB
111 = CTRD = CMPB 111 = CTRD = CMPB
Modulo 7
 ePWM Event-Trigger Prescale
Register
EPwmxRegs.ETPS
EPWMxSOCB / A Counter EPWMxINT Counter
(number of events have occurred) (number of events have occurred)
00 = no events 00 = no events
01 = 1 event 01 = 1 event
10 = 2 events 10 = 2 events
11 = 3 events 11 = 3 events

15 - 14 13 - 12 11 - 10 9-8 7-4 2-3 1-0

SOCBCNT SOCBPRD SOCACNT SOCAPRD reserved INTCNT INTPRD

EPWMxSOCB / A Period EPWMxINT Period

(number of events before SOC) (number of events before INT)
00 = disabled 00 = disabled
01 = SOC on first event 01 = INT on first event
10 = SOC on second event 10 = INT on second event
11 = SOC on third event 11 = INT on third event

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Modulos de Captura y de Entrada de
Encoders

Modulo 7
 eCAP Diagrama de bloques – Modo Captura
CAP1POL
CAP1 . 31 - 0 ECCTL . 0

Capture 1 Polarity
Register Select 1
CAP2POL
CAP2 . 31 - 0 ECCTL . 2

TSCTR . 31 - 0 Capture 2 Polarity PRESCALE

Event Logic
Register Select 2 ECCTL . 13 - 9
32-Bit CAP3POL Event
Time-Stamp CAP3 . 31 - 0 ECCTL . 4 Prescale
Counter ECAPx
Capture 3 Polarity pin
Register Select 3
SYSCLKOUT CAP4POL
CAP4 . 31 - 0 ECCTL . 6

Capture 4 Polarity
Register Select 4

Modulo 7
 Unidad de Captura(eCAP)

Timer
Trigger

pin
Timestamp
Values

• El modulo eCAP captura el valor del timer cuando se

produce una transición en el pin de captura.

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 Algunos usos de la unidad de captura
◆ Medición de tiempo del ancho de un pulso
◆ Estimación de velocidad de un encoder incremental
(en bajas velocidades).
Problema: a bajas velocidades, el calculo de de
xk - xk-1
velocidad basado en la medición del cambio de vk 
posición a intervalos fijos de tiempo, produce t
grandes errores.

Alternativa: Estimar la velocidad utilizando la medición de

tiempo a pasos de posición fija.
Señal de un canal
x
vk  De encoder
tk - tk-1
x

◆ Generación auxiliar de PWM

Modulo 7
 eCAP Diagrama de Bloques– APWM Mode

Shadowed
Period CAP3 . 31 - 0
CAP1 . 31 - 0 Period Register shadow
immediate Register (CAP3) mode
mode (CAP1)

TSCTR . 31 - 0

32-Bit PWM
Time-Stamp Compare
Counter Logic ECAP
pin
SYSCLKOUT
CAP2 . 31 - 0 Compare
immediate Register Compare CAP4 . 31 - 0
mode (CAP2) Register shadow
Shadowed (CAP4) mode

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 eCAP Registros
Name Description Structure
ECCTL1 Capture Control 1 ECapxRegs.ECCTL1.all =
ECCTL2 Capture Control 2 ECapxRegs.ECCTL2.all =
TSCTR Time-Stamp Counter ECapxRegs.TSCTR =
CTRPHS Counter Phase Offset ECapxRegs.CTRPHS =
CAP1 Capture 1 ECapxRegs.CAP1 =
CAP2 Capture 2 ECapxRegs.CAP2 =
CAP3 Capture 3 ECapxRegs.CAP3 =
CAP4 Capture 4 ECapxRegs.CAP4 =
ECEINT Enable Interrupt ECapxRegs.ECEINT.all =
ECFLG Interrupt Flag ECapxRegs.ECFLG.all =
ECCLR Interrupt Clear ECapxRegs.ECCLR.all =
ECFRC Interrupt Force ECapxRegs.ECFRC.all =

Modulo 7
 eCAP Control Register 1
ECapxRegs.ECCTL1
Upper Register:
CAP1 – 4 Load
on Capture Event
0 = disable
1 = enable

15 - 14 13 - 9 8
FREE_SOFT PRESCALE CAPLDEN

Emulation Control Event Filter Prescale Counter

00 = TSCTR stops immediately 00000 = divide by 1 (bypass)
01 = TSCTR runs until equals 0 00001 = divide by 2
1X = free run (do not stop) 00010 = divide by 4
00011 = divide by 6
00100 = divide by 8

11110 = divide by 60
11111 = divide by 62
Modulo 7
 eCAP Control Register 1
ECapxRegs.ECCTL1

Lower Register:

Counter Reset on Capture Event

0 = no reset (absolute time stamp mode)
1 = reset after capture (difference mode)

7 6 5 4 3 2 1 0
CTRRST4 CAP4POL CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL

Capture Event Polarity

0 = trigger on rising edge
1 = trigger on falling edge

Modulo 7
 eCAP Control Register 2
ECapxRegs.ECCTL2

Upper Register:

Capture / APWM mode

0 = capture mode
1 = APWM mode

15 - 11 10 9 8
reserved APWMPOL CAP_APWM SWSYNC

APWM Output Polarity Software Force

(valid only in APWM mode) Counter Synchronization
0 = active high output 0 = no effect
1 = active low output 1 = TSCTR load of current
module and other modules
if SYNCO_SEL bits = 00

Modulo 7
 eCAP Registro de Control 2
ECapxRegs.ECCTL2

Lower Register:
Re-arm Continuous/One-Shot
Counter Sync-In (capture mode only) (capture mode only)
0 = disable 0 = no effect 0 = continuous mode
1 = enable 1 = arm sequence 1 = one-shot mode

7-6 5 4 3 2-1 0
SYNCO_SEL SYNCI_EN TSCTRSTOP REARM STOP_WRAP CONT_ONESHT

Sync-Out Select Time Stamp Stop Value for One-Shot Mode/

00 = sync-in to sync-out Counter Stop Wrap Value for Continuous Mode
01 = CTR = PRD event 0 = stop (capture mode only)
generates sync-out 1 = run 00 = stop/wrap after capture event 1
1X = disable 01 = stop/wrap after capture event 2
10 = stop/wrap after capture event 3
11 = stop/wrap after capture event 4

Modulo 7
 eCAP Registro de Habilitación de Interrupción
ECapxRegs.ECEINT

CTR = CMP CTR = Overflow Capture Event 3 Capture Event 1

Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable

15 - 8 7 6 5 4 3 2 1 0
reserved CTR=CMP CTR=PRD CTROVF CEVT4 CEVT3 CEVT2 CEVT1 reserved

CTR = PRD Capture Event 4 Capture Event 2

Interrupt Enable Interrupt Enable Interrupt Enable

0 = disable as interrupt source

1 = enable as interrupt source

Modulo 7
 Encoders de cuadratura (incremental)

Sensor digital de posición (angular)

photo sensors spaced /4 deg. apart

slots spaced  deg. apart /4

light source (LED)


Ch. A

Ch. B
shaft rotation

Incremental Optical Encoder Quadrature Output from Photo Sensors

Modulo 7
 Como se determina la posición a partir de de las
señales en cuadratura

Position resolution is /4 degrees

(00) (11)
increment decrement
(A,B) = counter 10 counter
(10) (01)

Illegal
Ch. A Transitions;
00 generate 11
phase error
interrupt

Ch. B

01

Quadrature Decoder
State Machine
Modulo 7
 eQEP Diagrama de Bloques
Measure the elapsed time
between the unit position events;
used for low speed measurement
Quadrature
Generate periodic
Capture
interrupts for velocity Quadrature - Direction -
calculations clock mode count mode
Monitors the quadrature
clock to indicate proper
operation of the motion EQEPxA/XCLK
control system
32-Bit Unit EQEPxB/XDIR
Time-Base Quadrature
QEP Decoder EQEPxI
Watchdog
EQEPxS
SYSCLKOUT
Position/Counter
Compare
Generate the direction and
clock for the position counter
Generate a sync output in quadrature count mode
and/or interrupt on a
position compare match

eQEP=Enhanced Quadrature Encoder Positioning

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Fin Modulo 7

Modulo 7