Design of
sequential circuits
© Luis Entrena, Celia López,
Mario García, Enrique San Millán
Universidad Carlos III de Madrid
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 1
Outline
⚫ Sequential circuits
• Bistables
• Asynchronous latches
• Synchronous flip-flops
• Synchronous flip-flops with asynchronous inputs
• Synchronous circuits
• Registers
• Counters
⚫ Design of sequential circuits in VHDL
• Flip-flops and registers
• Rules for the design of sequential circuits
• Counters
• Examples and exercises
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 2
Register
⚫ Digital circuit with two basic functions: “storage and transfer of
data” (Floyd)
• It is a collection of two or more D-type flip-flops with common inputs.
• It is used for storing a number of related bits, such as a byte (8 bits).
Data(n)
Q(n)
Enable
Clear Register
• Stores data in the active edge of Clk
Clock • Initializes contents in the active level of
Reset
• It can have other synchronous inputs, such
Reset as Enable and Clear
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 3
Register (1 bit)
Schematic
0
Q
Data 1
Enable
Clear
Clock
Reset
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 4
Register (4 bits)
Parallel input / Parallel output
Schematic
Enable
Clear
Data(1) Data(2) Data(3)
Data(0) Q(3)
Register Register Register Register
1 bit 1 bit 1 bit 1 bit
Reset
Q(2)
Q(1)
Clock
Q(0)
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 5
Shift Register
It is a register for storing and shifting information
Bit 0 Bit 1 Bit 2 Bit 3
• Registers data in active edges of Clk. It also shifts the bits.
• Initializes contents in the active level of Reset
• It can have synchronous Enable and Clear inputs
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 6
Shift Register
Serial input and output
Inputs Output
Bit 0 Bit 1 Bit 2 Bit 3
• One input bit. One output bit. SISO
• Serial load. It shifts the bits.
• 4 Clk cycles for loading complete data.
• 4 Clk cycles for reading complete data.
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 7
Shift Register
Serial input, Parallel output
Input
Bit 0 Bit 1 Bit 2 Bit 3
S(0) S(1) S(2) S(3)
• One input bit. Four output bits.
• Serial load. It Shifts the bits.
SIPO
• Four Clk cycles for loading complete data.
• One Clk cycle for reading complete data.
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 8
Shift Register
Parallel input, Serial output
D(0) D(1) D(2) D(3)
Bit 0 Bit 1 Bit 2 Bit 3 Output
• Four input bits. One output bit.
PISO
• Parallel load. Serial output. It shifts the bits.
• 1 Clk cycle for storing complete data.
• 4 Clk cycles for reading complete data.
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 9
Shift Register
Serial input/ Parallel-Serial Output
Schematic
Enable
Clear
Data Q(3)
Register Register Register Register
1 bit 1 bit 1 bit 1 bit
Reset
Q(2)
Q(1)
Clock
Q(0)
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 10
Shift Register
Serial-parallel input / Serial-parallel output
Schematic
Data(1) Data(2) Data(3)
S/P
Data(0)
S_In S_Out
Enable
Clear
Q(3)
Register Register Register Register
1 bit 1 bit 1 bit 1 bit
Reset
Q(2)
Q(1)
Clock
Q(0)
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 11
Shift Register Schematic
Data(1) Data(2) Data(3) SISO
S/P
Data(0)
S_Out
S_In
Enable
Clear
Q(3)
Register Register Register Register
1 bit 1 bit 1 bit 1 bit
Reset
Q(2)
Q(1)
Clock
Q(0)
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 12
Shift Register Schematic
Data(1) Data(2) Data(3)
PIPO
S/P
Data(0)
S_Out
S_In
Enable
Clear
Q(3)
Register Register Register Register
1 bit 1 bit 1 bit 1 bit
Reset
Q(2)
Q(1)
Clock
Q(0)
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 13
Synchronous counters
Basic counter
Enable Q(n)
Counter
End/Carryout
Clock
Reset
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 14
Synchronous counters
Functional chronogram
Reset
Clk
Enable
Q 0 1 2 3 4 5 6 7 0 1
End
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 15
Synchronous counters
Functional chronogram
Reset
Clk
Enable
Q 0 1 2 3 4 5 6 7 0 1
End
Asynchronous initialisation
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 16
Synchronous counters
Functional chronogram
Reset
Clk
Enable
Q 0 1 2 3 4 5 6 7 0 1
End
Counting disabled
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 17
Synchronous counters
Functional chronogram
Reset
Clk
Enable
Q 0 1 2 3 4 5 6 7 0 1
End
End of counting
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 18
Synchronous counters (Up/Down)
Functional chronogram
Reset
Clk
UpDo
Enable
Q 0 1 2 3 4 5 6 5 4 3
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 19
Synchronous counters (Up/Down)
Functional chronogram
Reset
Clk
UpDo
Enable
Q 0 7 6 5 4 3 2 3 4 5
Down counting
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 20
Synchronous counters (Up/Down)
Functional chronogram
Reset
Clk
UpDo
Enable
Q 0 7 6 5 4 3 2 3 4 5
Up counting
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 21
Synchronous counters
Counter with Load and Syncronous Clear
Clear
Q(n)
Enable
Load
Contador
Data(n)
End/Carryout
Clock
Reset
[Link] [Link]
Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 22
Synchronous counters
Functional chronogram
Reset
Clk
Clear
Enable
Load
Data 9 3
Q 0 1 2 3 4 5 3 0 1 2
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 23
Synchronous counters
Asynchronous initialisation
Reset
Clk
Clear
Enable
Load
Data 9 3
Q 0 1 2 3 4 5 3 0 1 2
[Link] [Link]
Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 24
Synchronous counters
Count enable
Reset
Clk
Clear
Enable
Load
Data 9 3
Q 0 1 2 3 4 5 3 0 1 2
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 25
Synchronous counters
Count-value load
Reset
Clk
Clear
Enable
Load
Data 9 3
Q 0 1 2 3 4 5 3 0 1 2
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 26
Synchronous counters
Synchronous initialisation
Reset
Clk
Clear
Enable
Load
Data 9 3
Q 0 1 2 3 4 5 3 0 1 2
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 27
Outline
⚫ Sequential circuits
• Bistables
• Asynchronous latches
• Synchronous flip-flops
• Synchronous flip-flops with asynchronous inputs
• Synchronous circuits
• Registers
• Counters
⚫ Design of sequential circuits in VHDL
• Flip-flops and registers
• Rules for the design of sequential circuits
• Counters
• Examples and exercises
[Link] [Link]
Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 28
Rules for the design of
synchronous sequential circuits
⚫ “Template” for the design of synchronous sequential
circuits
PROCESS( <clock + reset>)
BEGIN
IF < asynchronous initialization condition> THEN
-- Asynchronous initialization
ELSIF < active clock edge> THEN
-- Synchronous behavior
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 29
A parallel register
⚫ If q is an array, then a register will be generated with
as many flip-flops as the array dimension indicates
-- 8-bit register
SIGNAL q, d: STD_LOGIC_VECTOR (7 DOWNTO 0);
...
PROCESS (clk)
BEGIN
IF reset=‘1’ then
q <= (OTHERS=>’0’);
IF clk’EVENT AND clk = ‘1’ THEN
q <= d;
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 30
Flip-flop with synchronous inputs
⚫ Reset and clear don’t have the same purpose, even
if they produce the same result
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN
q <= (OTHERS=>’0’);
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF clear=‘1’ THEN
q <= (OTHERS=>’0’);
ELSIF enable = ‘1’ THEN
q <= d;
END IF;
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 31
Inference of registers and
flip-flops
⚫ Every signal that is assigned between IF clk’EVENT ... and
END IF infers a flip-flop/register
-- Combinational adder -- Registered adder
PROCESS (a, b) PROCESS (clk)
BEGIN BEGIN
s <= a + b; IF clk’EVENT AND clk = ‘1’ THEN
END PROCESS; s <= a + b;
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 32
Inference of registers and
flip-flops
-- Adder with registered inputs and outputs -- Adder with registered inputs and outputs
-- Input and output registers with reset
PROCESS (clk)
PROCESS (reset, clk)
BEGIN
BEGIN
IF clk’EVENT AND clk = ‘1’ THEN
IF reset = ‘1’ THEN
a1 <= a;
a1 <= (OTHERS => ‘0’);
b1 <= b;
b1 <= (OTHERS => ‘0’);
s <= a1 + b1;
s <= (OTHERS => ‘0’);
END IF;
ELSIF clk’EVENT AND clk = ‘1’ THEN
END PROCESS;
a1 <= a;
b1 <= b;
s <= a1 + b1;
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 33
Inference of registers and
flip-flops
⚫ A register may not have -- Registered Adder
reset, but a reset signal -- Incorrect initialization!
always needs an PROCESS (clk)
associated register!
BEGIN
⚫ Combinational logic must IF reset = ‘1’ THEN
not be purposely a <= (OTHERS => ‘0’);
initialized (it is indirectly b <= (OTHERS => ‘0’);
initialized) s <= (OTHERS => ‘0’);
ELSIF clk’EVENT AND clk = ‘1’ THEN
s <= a + b;
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 34
Exercises
⚫ Design a 4-bit right shift register
ENTITY shift_reg IS
PORT ( reset: IN STD_LOGIC;
clk: IN STD_LOGIC;
si: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END shift_reg;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 35
Solution: shift register
ARCHITECTURE a OF shift_reg IS
SIGNAL qaux: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN
qaux <= "0000";
ELSIF clk’EVENT AND clk = ‘1’ THEN
qaux <= si & qaux (3 DOWNTO 1);
END IF;
END PROCESS;
q <= qaux;
END a;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 36
Counters
⚫ Using a vector of bits (UNSIGNED)
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN
q <= “00000000”;
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF enable = ‘1’ THEN
q <= q + 1;
END IF;
END IF;
END PROCESS;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 37
Counters
⚫ Using an INTEGER
SIGNAL q: UNSIGNED(7 DOWNTO 0);
SIGNAL c: INTEGER RANGE 0 TO 255;
…
PROCESS (reset, clk)
BEGIN Required to avoid
IF reset = ‘1’ THEN overflow
c <= 0;
ELSIF clk’EVENT AND clk = ‘1’ THEN
IF enable = ‘1’ THEN
IF c = 255 THEN
c <= 0;
ELSE
c <= c + 1;
END IF;
END IF;
END IF;
END PROCESS;
q <= TO_UNSIGNED(c,8);
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 38
Exercise
⚫ Design a 4-bit up counter with carry output
ENTITY count4 IS
PORT ( reset: IN STD_LOGIC;
clk: IN STD_LOGIC;
q: OUT UNSIGNED(7 DOWNTO 0);
carry_out: OUT STD_LOGIC);
END cont4 ;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 39
Solution: 4-bit up counter with
carry output
ARCHITECTURE a OF count4 IS
SIGNAL qaux: UNSIGNED (3 DOWNTO 0); BEGIN
PROCESS (reset, clk)
BEGIN
IF reset = '1' THEN
qaux <= "0000";
carry_out <= ‘0’;
ELSIF clk'EVENT AND clk = '1' THEN
qaux <= qaux + 1;
IF qaux = “1111” THEN
carry_out <= ‘1’;
ELSE Carry_out is registered!
carry_out <= ‘0’; (it comes out with 1
END IF; clock cycle delay)
END IF;
END PROCESS;
q <= qaux;
END a;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 40
Solution: 4-bit up counter with
carry output
ARCHITECTURE a OF count4 IS
SIGNAL qaux: UNSIGNED (3 DOWNTO 0);
BEGIN
Carry_out is asserted in
q <= qaux;
the last clock cycle
carry_out <= ‘1’ WHEN q = “1111” ELSE ‘0’; before overflow
PROCESS (reset, clk)
BEGIN
IF reset = '1' THEN
qaux <= "0000";
ELSIF clk'EVENT AND clk = '1' THEN
qaux <= qaux + 1;
END IF;
END PROCESS;
END a;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 41
Exercise
⚫ Design an 8-bit up/down counter with enable and load inputs
ENTITY count_up_down IS
PORT ( reset: IN STD_LOGIC;
clk: IN STD_LOGIC;
load: IN STD_LOGIC;
d: IN UNSIGNED(7 DOWNTO 0);
ud: IN STD_LOGIC;
enable: IN STD_LOGIC;
q: OUT UNSIGNED(7 DOWNTO 0));
END count_up_down;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 42
Solution: up/down counter
ARCHITECTURE a OF count_up_down IS
SIGNAL qaux: UNSIGNED (7 DOWNTO 0);
BEGIN
PROCESS (reset, clk)
BEGIN
IF reset = '1' THEN
qaux <= "00000000";
ELSIF clk'EVENT AND clk = '1' THEN
IF load = '1' THEN
qaux <= d;
ELSIF enable = '1' THEN
IF ud = '1' THEN
qaux <= qaux + 1;
ELSE
qaux <= qaux - 1;
END IF;
END IF;
END IF;
END PROCESS;
q <= qaux;
END a;
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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 43
