1

REGLAS DE DISEÑO Y ESTANDARES

INDUSTRIALES
[email protected] TEMA 5
 2
Reglas de diseño PCB
¨  Del diseño de la PCB puede depender el funcionamiento correcto de nuestro circuito (Las pistas tienen
resistencia, inductancia y capacidad).
¨  ESTÁNDAR PCB DESIGN- IPC-2221 “Generic Standard on Printed Board Design”
¨  Esquemático:
¤  Antes de empezar el diseño PCB hay que tener claro el esquema del circuito y el footprint de todos los componentes
del mismo (Hacer el esquema pensando ya en el diseño PCB ayuda mucho).

¨  Unidades de Medida:

¤  En el diseño de PCBs normalmente se trabaja en pulgadas, mils. La mayoría de los componentes se fabrican con un
espaciado en pulgadas.

¤  0.05’’=50 mils =1.27mm

¤  0.1’’=100 mils =2.54 mm
¤  0.2’’=200 mils = 5.08 mm
 3
Posicionamiento
¤  El posicionamiento de componentes se tiene que realizar de tal forma que todos los componentes queden claramente
organizados con un alineamiento y espaciado uniforme.
¤  Los componentes deben estar alineados con los bordes de la placa (Colocados de forma horizontal o vertical)
¤  Los componentes THD sólo pueden estar colocados a un lado de la placa.
¤  Usar un grid de 100 mils para el posicionamiento de componentes en placas no muy complicadas, en caso de placas
mas complicadas no bajar de 20 mils. (100mils, 50 mils, 25mils, 20mils) son los grids recomendados por la IPC para
el posicionamiento de componentes
¤  Para facilitar el diseño la grid se puede hacer visible (puntos o rayas ).
¤  Si es posible orientar de la misma manera todos los componentes con polaridad (diodos, condensadores) para
facilitar el montaje.
¤  Si el diseño lo permite los conectores deben estar en la parte corta de la placa.
¤  Dejar suficiente espacio en los bordes para trabajar con la placa de forma sencilla.

¨  VISTAS
¤  En el diseño de la PCB siempre se trabaja viendo la placa desde arriba y se ven todas las capas como si fueran
transparentes. Esto hay que tenerlo en cuenta a la hora de poner texto o componentes en la capa de abajo.
¤  Algunas herramientas permiten ver la placa en 3D
 4
Posicionamiento
¨  COMPONENTES
¤  “Un buen diseño PCB depende en un 90% de la colocación de los componentes y en un 10% del
enrutado”.
¤  Consejos:
- Poner la rejilla visible.
- Poner todos los componentes.
- Elegir tamaño de placa.
- Formar Bloques Funcionales (Colocar componentes).
 Espaciado recomendado (THDs)
5

Componentes axiales espaciado hasta el

(a)
borde de la placa:
(b) a = 75 mils
b= 90 mils

Espaciado entre componentes

100 mils

Espaciado entre componentes cuando el diámetro

(a) de alguno de ellos es mayor a 100mils
D1
a=70+0.5D1 mils
(b)
b=70+0.5D1+0.5D2 mils
D2
 Espaciado recomendado (THDs)
6

Espaciado entre componentes cuando el diámetro de

alguno de ellos es mayor a 100mils

D1 95+0.5D1 mils

(r) Componentes radiales, espaciado hasta el borde de la placa:

r≥0.5*Diametro mils y r≥ 0.5*Altura mils y r≥60 mils

(r)

(a) IC de inserción, espaciado hasta el borde de la placa:

a=100 mils
b=75 mils

(b)
 Espaciado recomendado (THDs)
7

(b)
Espaciado entre ICs
a=200 mils
b=100 mils
(a)

(a) (b)

Espaciados
D1
(c) (d) a= (D1>100mils) 115+D1 mils
D1 b= 200 mils
c= 100 mils
d= (D1>100mils) 40+0.5D1 mils
 Espaciado recomendado (SMDs)
8

(a) Espaciado hasta el borde de la placa:

60 mils
(a)

Espaciado entre componentes

Tamaño 0603 o mayor à 20 mils
Tamaño menor a 0603 à 12 mils

Espaciado de PAD a VIA 20 mils

(a) ICs SMD espaciado hasta el borde de la placa:

60 mils
(a)

Espaciado entre ICs SMD

componentes
100 mils
9
Pistas
¤  No hay un estándar para el grosor de las pistas, normalmente en un mismo diseño deben haber
pistas de varios grosores dependiendo del tipo de señal que deban conducir cada una de ellas
(Alimentación, señal, …).
¤  Como regla general a mayor grosor de pistas mejor ya que tienen una resistencia, inductancia y
capacidad mas baja y son mas fáciles de fabricar. El problema es que a mayor grosor menos
flexibilidad de enrutado.
¤  El grosor mínimo de las pistas y su separación mínima (Clearance) nos lo debe decir el fabricante
del circuito. Ejemplo 2CISA. IPC no recomienda por debajo de 4mils.
 10
Pistas
¤  Como datos orientativos se puede empezar
con 50mils para las pistas de alimentación,
25 mils para pistas de señal y 12-16mils
para la conexión de integrados.
¤  Se puede cambiar el tamaño de una pista
para poder cumplir con los requerimientos de
clearance al pasar cerca de los pads de los
componentes.
¤  En el caso de tener pistas por las que circule
mucha corriente, hay que tener en cuenta la
resistencia asociada a la pista y que la pista
se calentara debido a la disipación de
potencia (Calculo complejo)
¨  Herramienta:
http://circuitcalculator.com/wordpress/
2006/01/31/pcb-trace-width-calculator/
11
Ejemplo de Pistas de distinto grosor
 12
Cleareance
¨  DISTANCIAS (CLEAREANCES)
¤  Las distancias entre PADS y Pistas son muy importantes a la hora de evitar futuros problemas en
el diseño de las placas. Como en las pistas el fabricante será el que marque las mínimas
distancias a cumplir. Como dato orientativo hay que usar 15mils.
¤  Si se trabaja a altos voltajes hay que tener mas cuidado con las distancias, a continuación se
muestra una tabla (IPC) a modo de ejemplo.
 13
PADs
¨  PADS
¤  El tamaño y la geometría de los PADs depende de los componentes a usar y de la tecnología de fabricación
de las placas.
¤  Normalmente se usan las librerías que vienen con los programas de diseño donde ya vienen diseñados los
PADs de los componentes aunque se pueden modificar y crear nuevos.
¤  Es muy importante que la corona del PAD sea lo suficiente grande para poder realizar el soldado sin
problemas.
 Recomendaciones paraIntroduction
diseñotode packages THD
Design for Manufacturing
14
(a) (b)
¨  Dos grandes categorías: Componentes
LB axiales (resistencias) Component
y componentes radiales (Condensadores)
Place outline Introduction to Design for Manufacturing
LLE outline (Silkscreen) WB
Chapter 5
(a) (b)
(a) (b) LB Component
Component outline Place outline
LLE outline (Silkscreen) WB
Place outline (Silkscreen) 2
DL WB
LLE 2
LP
25 V
22 $F

DL WB LP
LLE
LP LP
Figure 5-13 Generic footprint design parameters for axial-leaded components. (a) Radial-leaded
resistor. (b) Layout radial footprint
Figure 5-13 Generic footprint design parameters for axial-leaded components. (a) Radial-leaded

Lead diameter
2
resistor. (b) Layout radial footprint
n
DL ! 31 (mils) Lead diameter
3 n

DL ! (0.8 mm)
DL ! 31 (mils)
DL ! (0.8 mm)
LP = LB + n ⋅ DL + 2LLE
3

31 " DL # 47 (mils) 31 " D #447 (mils) 4

L
0.8 " DL # 1.2 (mm) 0.8 " DL # 1.2 (mm)
47 " DL (mils) 5
47 " DL (mils) 5
Figure 5-12 Radial-leaded through-hole device.1.2 " DL (mm)
(a) Axial-leaded capacitor. (b)1.2 "D
Layout L (mm)
axial footprint

of device is determined strictly by the construction of the device. Clearly theTable 5-12have
padstacks Bendto radius factor
Table 5-12 Bend radius factor
be located where the leads extend from the body. Radial-leaded devices include pin grid arrays
and many discrete transistor devices such as TO220
is used. Theand TO92
total packages.
length of bothThe only should
leads variablenot
is exceed 1 in. (25 mm) unless the component
the padstack design with regard to the lead diameters. Padstack
is mechanically design is described below.
supported.
is used. The total length of both leads should not exceed 1 in. (25 mm) unless the component
Footprint designs for components with axial leads are highly variable compared to the radial-
is mechanically supported.Padstack design
leaded devices, but the IPC standards (IPC-CM-770, for through-hole
Section 11.1.8, devices
p. 67) and other sources
in literature provide general guidance on
Thefootprint
biggestdesign. Figure 5-13
vulnerability illustrates
of PCB the design
fabrication is the plated through-hole (PTH) because of
ge a pad does not necessarily make a better solder joint and only increases the
t required to make theD
solder joint. Too small a pad can cause a weak solder
P ! a " 2b " c, (5) DL

dd diameter
diameter
Recomendaciones para diseño de packages THD
pad can be easily damaged by heat or mechanical stress and lift off from the
recommended by IPCa(IPC-2221A,
(see Fig. 5-14), is the nishedp. 73) is calculated
hole size (a !using
DHEq.
# (5),
2TP from A
minimum
15 annular ring
DP !requirements
a " 2b " c, from Table 5-14 (IPC-2221A, (5)Table
tandard fabrications allowances from Table 5-15 (IPC-2221A, Table 9-1).
e pad Diseño de
¨  diameter (seetaladros:
Fig. 5-14), a is the nished hole size (a ! DH # 2TP from D
P
s the minimum annular ring requirements from Table 5-14 (IPC-2221A, Table
the standard fabrications allowances Dfrom
L DH = ( DL + 2TP ) ⋅ k
Table 5-15 (IPC-2221A, Table 9-1).
DH

DL A
Tp es el grosor del cobre dentro del agujero (1mil)
Figure 5-14 PTH design parameters
K es un factor de tolerancia 1.05≤k≤3 (1.5 recom.)
A

Internal External
DP
DP Mils
= a + 2b + c 1 2
DP
Millimeters
DH a = D − 2T
H P
0.025 0.05
DH
Table 5-14 Annular ring requirements for
Figure
Figure
5-14
b minimum PTH
5-14 PTH
design
annular ring,
design
parameters
c standard fabrication allowances (ver tabla
parameters de IPC-2221)
internal and external rings
b c
Internal
Internal External
External Level A Level B Level C
Mils
Mils 11 2 2 Mils 16 10 8
Millimeters 0.025 0.05
Millimeters 0.025 0.05 Millimeters 0.40 0.25 0.20
¨  Ejemplo:
Table (DL=32mils)
5-14 Annular ring requirements for
Table 5-14 Annular
internal ring requirements
and external rings for Table 5-15 SFAs for PTH design
DH=(32+2*1)*1.5 = 51 mils à 50 mils
internal and external rings
DP= (50 – 2*1)+(2*2)+16= As an example, if we use the 32-mil lead from the example above (using a hol
68 Bmils Level
Level A Level C
mils) and we are calculating the size of an external pad (TOP or BOTTOM in
Mils 16 10 8
Level A Level B we Level
want aCLevel A producibility level, then the pad size would be (50 # 2 $ 1
Millimeters 0.40 0.25 0.20
Mils 16 10 16 !868 mils.
16
Vias
¤  Las vías se usan para conectar pistas de una cara con pistas de otra cara a través de un agujero
en la placa.
¤  En las placas comerciales todos los agujeros están metalizados por lo que actúan como vías. En
caso de placas ‘caseras’ es necesario hacer el contacto entre las dos capas soldando un cable.
¤  Normalmente las vias suelen ser mas estrechas que los PADS (Cuidado con la corona)
17
Enrutado
¤  Es el proceso de conexión de los distintos componentes de las
placa, cada una de las pistas recibe un nombre (NETS).
¤  Reglas:
- Usar siempre el enrutado forzado a la rejilla.
- Mantener las pistas tan cortas como sea posible (cuidado hacer
todas las líneas directas dificultan el enrutado)
- Las pistas solo deben de tener ángulos de 45º/135º. Hay que
evitar el uso de ángulos rectos (problemas de fabricación).
- Identificar componentes o pistas“Criticos” y enrutarlas al
principio del diseño.
- Realizar el enrutado interno de cada uno de los diferentes
bloques funcionales.
- Realizar la conexión de los distintos bloques.
- Realizar DRC (Design Rule Check)
 18
Enrutado
¤  Llevar siempre las pistas al centro de los PADS (Correcta rejilla).
¤  Solo pasar una pista entre dos pads separado 100mils (en placas complejas se puede llegar a
dos pistas).
¤  Para corrientes altas usar varias vías en paralelo para pasar de una capa a otra.
¤  Enrutar primero las pistas de alimentación y tierra, si es posible mantener las pistas de
alimentación y tierra juntas (Esto evita bucles de inductancia).
¨ 
19
Enrutado
¤  Evitar terminaciones en T

¤  En caso de trabajar sin metalizado del circuito hay que tener en cuenta que no se producirá una
conexión entre las capas donde haya un agujero, habrá que soldar el componente (PAD) o un
cable (VIA) por las dos caras para realizar dicha conexión. En este caso.
¤  Evitar poner VIAS debajo de los componentes (Quedaran inaccesibles una vez el componente
este soldado).
¤  Intentar usar los pads de los componentes que pueden ser soldados en ambas caras para hacer
de VIAS, de esta forma reduciremos el numero de VIAS.
¤  Si es posible realizar el enrutado en una sola cara (Reducción de costes)
20
Planos de Alimentación
¤  Se suelen usar planos para distribuir las señales de alimentación en la placa, de esta forma se
reduce las capacidades e inductancias parasitas (muy perjudiciales en circuitos de alta
frecuencia)

¤  Es recomendable usar planos de masa distintos (aunque unidos mediante pistas) en caso de que
tener una parte analógica y una parte digital en el circuito, de esta forma evitaremos, en parte,
que el ruido provocado por los componentes digitales interfieran con la parte analógica
(Cuidado con los bucles, unir cerca de los condensadores de filtrado).
¤  Usar condensadores de desacoplo para cada integrado (0.1uF)
21
Planos de Masa
Con polígonos se rellenan áreas de cobre, manteniendo las distancias
con los PADs y pistas. Un polígono puede estar asociado a unas señales
(PLANOS de MASA)

Usar siempre polígonos con rellenos SÓLIDO.

En Eagle la asociación se realiza poniéndole al polígono el nombre de la
NET a la que se le quiera asociar.
22
Integridad de la señal
Objetivos en el diseño de la PCB:
1. La PCB debe de ser inmune a la interferencia producida por otros
sistemas. (Electromagnetic Interference EMI)
2. No debe de producir emisiones que causen problemas en otros
sistemas. (EMI / Electromagnetic Compatibility-EMC)

3. Internamente todas las señales debe de tener la calidad deseada.

El layout de la PCB puede reducir en gran medida el EMI y

mejorar el EMC de nuestro sistema.
 emissions that cause problems for other systems, and (3) it should demonstrate th
signal quality. A common factor relating these three issues is electromagnetic wave
Integridad de la señal
6-1 shows, “noise” can be introduced into your PCB from outside sources, and it c
23
noise that is radiated to other systems and to itself.

Other
systems

Interference Emissions

Power supplies PCB

“Noise”
Instruments
Sensors “Noise”
Actuators

Enclosure (packaging)

Your system

Figure 6-1 The enemy—electromagnetic interference.

hematically by a cross product called the Biot-Savart law. By applying some calculus,
Integridad de la señal
ch will not be shown here, an equation can be derived for the scalar (non-vector) magni-
, B,24of the magnetic eld vector, B, near the conductor.

Magnetic
B field

Conductor I

Current
flow

Figure 6-2 Magnetic field caused by a current-carrying conductor.

will point in the direction of the force applied to the positive charges (FC!) and therefore the
positive current ow. The resultant voltage and current are shown in Fig. 6-3. Notice that the
Integridad de la señal
current in the secondary conductor ows in the direction opposite that of the current in the
primary conductor as a result of the induced voltage. This produces a secondary magnetic
25
eld which opposes and partially cancels the primary magnetic eld (by Lenz’s Law).

Field expansion
velocity ("B) B FC!
"C (relative)

B (!I)
Fc! !
Eg
"B
!
dI/dt
"C (relative)
#

Field expansion velocity ("B)

Figure 6-3 Voltage induced into adjacent trace by varying magnetic fields.
gments of the traces were shown. Of course for current to ow through the I
h must exist, as shown in Fig. 6-4. Any conductor in the circuit that carries
Integridad de la señal
e a magnetic eld as indicated by the circular arrows.
26
Figure 6-4 Loop inductance of a closed c
he closed loop circuit shown in Fig. 6-4 with respect to its volume, we
Anisequation
uit for
physically
I inductance
large and makesis agiven
large in Eq.it(5)
loop, will(Serway, p.is905),
have what refer
uctance.
2
hand weVSarrange the circuit as shown
RL in Fig.L ! µ0n Aℓ,see from Eq.
6-5, we can
nductance will be less since there is less volume. If you notice the direc
e magnetic elds) you can see that the source current and the return cu
where n is the number of turns (1), Aℓ is the volume
s oppose each other, thereby reducing the ux and inductance.
I that the circ
relative permeability of the material in which the circuit exists. F
PCBs, µ06-4
Figure 1. So
! Loop the inductance
inductance of a closed is a function of the volume of t
circuit.
I
of turns
ductance of the
is given conductor
in Eq. around
(5) (Serway, p. 905),the space. Therefore, inductanc
VS RL
geometry, by which a smaller volume results in a smaller circuit
L ! µ0n2Aℓ, I (5)
115
Figure
ber of turns (1),6-5 Closed
Aℓ is loop that
the volume circuit with low
the circuit loop and
occupies, µ0 is the
inductance.
 Figure 6-6(a) shows the
(maximum resultant
coupling magnetic
and small eld ofareas).
cross-sectional two The
conductors intoclose
easiest way do thisproximity
is by using where
the currentsaare
plane
inlayer
the as the return
same path. The
direction. Asreturn plane has
indicated the historically
magnetic(and most
elds often inappro-
circulate in the same
Integridad de la señal
priately) been called the ground plane, but it is being referred to more often as an image
direction and aidoreach
plane other.
a return This
plane. is the
In PCB casea return
design for anplane
inductor
has lowininductance
which the turns
(and are wound
therefore low in
the same direction and build
self-inductance) and itup an overall the
is everywhere strong
signalmagnetic eld.
trace is and therefore allows for maximum
27
coupling between the signal trace and the plane for any and all widths of the signal trace.
(a) (b)
From this discussion then we can say that one of the most important functions of the
return (image) plane is to reduce loop inductance. Reducing loop inductance (and the
magnetic elds related to it) provides a low-impedance return path for power and signal
lines and reduces unwanted cross talk to nearby conductors. It should also be stated that
cross talk between unrelated conductors is also reduced by keeping them farther apart
(i.e., r is large).

Electric fields and capacitive coupling

We saw in the previous paragraphs that keeping signal and power lines close to their return
paths provides ux cancellation and reduces loop inductance, which is bene cial in all
respects. But what happens with the electric elds under these circumstances and what is the
effect on the circuit? Figure 6-7(a) shows electric eld lines for a single charged conductor,
which can represent a signal trace that is a long way away from its return path. Figure 6-7(b)
shows electric eld lines between two oppositely charged conductors, which can represent a

Figure 6-6 Aiding and opposing

(a)
magnetic fields. (a) Aiding fields.
(b)
(b) Opposing fields.
" " " " "
" " " " "
Figure 6-6(b) shows the resultant magnetic eld when the currents of the two conductors are
in opposite directions. "
The" magnetic
" " "
elds oppose each other and result in partial ux cancel-
lation. The amount of cancellation
" " " " depends
" on the amount of mutual inductance, which in
turn depends in part on the distance between the conductors.
# # # # # #
The situations in Figs. 6-4, 6-5, 6-6(a), and 6-6(b) are steady-state DC circuits, but if we
# # # # # #
apply the concept in Fig. 6-3 and Eq. (3) for time-varying currents then we can see that, if the
return trace onFigure
a circuit boardfields
6-7 Electric is in
onclose proximity
conductors. to the
(a) A single signal
charged trace, then
conductor. (b) A fithe inductance of
eld between
is also called a separate ground system, since the current ow in each branch is supplied
by and returns to the source through completely separate paths. A series connected ground
Integridad de la señal
system is shown in Fig. 6-9(b). The series connected ground system is also referred to as a
common ground system or daisy chain, since the current ows in the two branches share a
28
common path.

(a) (b)
I2
I1 I1 I2
! ! ! ! ! !
VS IT R1 VR1 R2 VR2 VS IT R1 VR1 R2 VR2
" " " " " "
PCB Design for Signal Integrity
(1) (2)
ZCOMMON1

Figure 6-9 Typical

! Vz2signal
" and
! Vreturn
z2 " connection
! Vz2 " schemes. (a) !
Parallel
Vz2 "connected.
I (b) Series connected.
2
! Vz1 " ! Vz1 " ! Vz1 "
At the schematic levelI1 the circuits in Fig. 6-9 are identical; mathematically the circuits
are also identical,
! that is, IT # I1 ! I2 and VR1 # VR2 # VS. Furthermore,
! as indicated
! in
VS R1 VR1 R2 VR2
Fig. 6-9(b), you
"
could connect R 1 to the common return path at
"
either point (1) or"point (2)
without changing the meaning of the circuit description in any way. However, on the PCB,
the two circuits shown"inVz1Fig. I1
! 6-9 can
" Vz1be!signi cantly different. There may even be signi cant
(1)
differences between points (1) and (2) in Fig. 6-9(b). (2)
IT
" V ! " V ! " V !
It was said earlier that anyz2conductor that
z2 z1
carries current will produce a magnetic eld. Even
if there is very tight coupling between
ZCOMMON2 the signal conductor and its return conductor,
I2 some
inductance will always exist because the coupling is not 100.0% complete;
" Vz2 ! " Vz2 !
that is, there is
less than perfect mutual inductance from the primary trace to the secondary trace (the return
plane) and from the secondary trace back to the primary trace.
 current paths do not interfere with each other in the parallel

29
Integridad de la señal
completely separate, and since each signal path is directly ab

(a) (b)

R1
Signal
J1 paths 1 J1

2 2
2
1 1

R2

1
1

Return
paths
1

Figure 6-11 Signal and return connection schemes in Layout

other in the parallel connection since their paths are
al path is directly above its return path, there is tight
30
Integridad de la señal
(b)

R1
Common
J1 signal
1
path
2
2
1
Common

R2
1

return
path
1
pedance and, particularly on PCBs, the path of least inductance. The only
Integridad de la señal
pen is if the return current travels directly under the signal trace on its way
31

Signal

R1
Return
Signal

Return
J1

R2
1

Return
For example, at a logic state of 0, Q1 is off and Q2 is on, the output
At rst glance there may appear to be no difference electrically speaking, but the differences
charges). Because
V). When the gate tries to switch to a high state, alogic
high
can be signi
current
level
cant at high1,
results
Q1 turns
frequencies
(even if only brie y) the voltage at the VDD
and fast rise times. Additionally, other issues such as the

Integridad de la señal
to drop
CL begins to charge to VDD. During until
this the switching
transition
method the
of gate
assemblyis(wave
complete
vs re ow and
consumes CL and
soldering) is fully charged.
the available Aestate
board real similar thing
often in u- hap
ence orientation and routing of bypass capacitors. Sources in the literature do not all agree
the gate tries
use for a brief moment Q1 and Q2 are both withto change
partially from
on. A
which method
ashort
logic
is best,
1 tooften
circuit
but more
a logic 0 state except that as CL tries to dis
Fig. 6-37(a) is recommended for analog circuits
through
32 through
Q1 and Q2 and through Q2 (which
CL (which has
and is6-37(b)
Fig.low turning
impedance on circuits.
for digital as Q1whileturns
it off) the voltage at the VSS pin tends to
the switching is complete and CL is fully discharged.
(a) (b)

Because the power and ground planes are not superconductors Via to
power
there is a drop in vo
VDD between the supply pins of the gate and where Via to power is connected
plane
to the PCB (sam
IC IC
power
return plane). Remember that there is always plane some amount of resistance and induct
Bypass Bypass
even on the so-called ground plane. This is shown in Fig. 6-14, in which cap
cap we see the
Q1
voltages across the PCBViawhile to
the gate is switching. The dropViain to
the positive rail is
collapse and the rise in ground
ground
plane
potential is called ground bounce. ground Note that, since t
plane
really nothing magical about the so-called ground plane, the term “rail collapse” ca
the ground rail rising
Figure as
6-37well
Poweras
pinthe supply
fan-out rail dropping.
methodologies. (a) Power pin to bypass capacitor to via.
In Out (b) Power pin to via to bypass capacitor.

VDD
Trace width for current carrying capability Rail collapse
CL (When switching 2
When current ows through a conductor it will heat up due to I R losses. Wider traces exhibit
from
less resistance and low to less
therefore high)
heating. To determine the minimum trace width required
Q2
to minimize heating, determine the maximum current a trace will carryWithout
and the thickness of
bypasstrace width,
the copper you will use on your board. Use Eq. (17) to calculate the minimum
Voltage

capacitors
⎛ 1 ⎞⎟ ⎛ I ⎞⎟1.379
w ! ⎜⎜ ⎟⋅⎜ ⎟ , With bypass (17)
⎜⎝ 1 . 4 ⋅ h ⎟⎟⎠ ⎜⎜⎝ k ⋅ "T 0.421 ⎟⎟⎠
VSS capacitors
(When switching
where w is the minimum trace width (in mils), h is the thickness of the copper cladding (in
from high
oz/ft2), I is the current tothe
load of low)
trace (in amps), k ! 0.024 is used for inner layers and
Figure 6-13 A CMOS logic gate. Ground bounce
VSS
151
PCB Gate
power Distance
123 (at time t ! 0")
connector
Ch06-H8214.indd 151 2/13/07 12:21:22

Figure 6-14 Illustration of ground bounce and rail collapse.

d. If the end of the rope is loose (a high impedance) the wave will be re ected ba
he person, who will feel an identical wave returned.
33
Integridad de la señal - Reflejos

ZT
Zline

Zline < ZT

ZT
Zline
pter 6
34
Integridad de la señal - Reflejos

ZT

Zline

Zline % ZT

ZT

Zline
35
Integridad de la señal - Reflejos
PCB Design for Signal Integrity

ZT
Zline

Zline " ZT

Zline " ZT
36
Integridad de la señal
37
Fabricación
38
Documentación a mandar
¤  Al fabricante hay que mandar documentación en formato GERBER.
¤  Ficheros:
¤  Fichero de enrutado por cada una de las capas usadas.
¤  Ficheros de mascara de soldadura (Solder Mask Top, Solder Mask Bottom)
¤  Ficheros de serigrafía.
¤  Fichero de taladros.

¤  En caso de automontaje

¤  Fichero de posicionamiento de componentes
¤  Fichero de pasta de soldar
¤  EAGLE genera todos estos fichero automáticamente a través del CAM processor (ver
apuntes EAGLE)
¤  En caso de fabricación con insolad ora hay que imprimir las caras deseadas en un fotolito.