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VHDL

xd

Cargado por

Carlos Gómezz
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© © All Rights Reserved
Nos tomamos en serio los derechos de los contenidos. Si sospechas que se trata de tu contenido, reclámalo aquí.
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Descarga como DOCX, PDF, TXT o lee en línea desde Scribd
91 vistas14 páginas

VHDL

xd

Cargado por

Carlos Gómezz
Derechos de autor
© © All Rights Reserved
Nos tomamos en serio los derechos de los contenidos. Si sospechas que se trata de tu contenido, reclámalo aquí.
Formatos disponibles
Descarga como DOCX, PDF, TXT o lee en línea desde Scribd

TECNOLÓGICO NACIONAL DE MÉXICO

INSTITUTO TECNOLÓGICO DE TUXTLA GUTIÉRREZ

INGENIERÍA ELECTRÓNICA

Materia: Diseño digital con VHDL

Trabajo a realizar:

Diseño de un circuito sumador y comparador con PLD

Alumno:
CABRERA ESQUIVEL MARIO ALBERTO
DÍAZ OLETA OSCAR DANIEL
LÓPEZ GÓMEZ CARLOS ALBERTO

Catedrático:

ING. DOMÍNGUEZ ZENTENO JOAQUIN EDUARDO

Tuxtla Gutiérrez, Chiapas, a 11 de septiembre del 2018


Diseño de Circuito Comparador.
se trata de una descripción funcional de dos bits porque expone la forma en que
trabaja el sistema; es decir, las descripciones consideran la relación que hay entre
las entradas y las salidas del circuito, sin importar cómo esté organizado en su
interior.
Si a = b la salida c será = 1
Si a ≠ B la salida c será = 0.
Para esta práctica se usaron los siguientes componentes.
-PLD GAL 16v8, - Leds diferentes colores, -Switch, -Bornera, -Resistencias y cables

Código usado.
library ieee;
use ieee.std_logic_1164.all;
entity comp is
port (a, b: in bit;
c:out bit);
end comp;
architecture funcional of comp is
begin
compara: process (a, b)
begin
if a = b then
c <='1';
else
c<='0';
end if;
end process compara;
end funcional;
Archivo RPT.
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |

======================================================================
Compiling: [Link]
Options: -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8-15pc/pi -b
[Link] -u [Link]
======================================================================

vhdlfe V6.1 IR 28: VHDL parser


Sun Sep 09 [Link] 2018

Library 'work' => directory 'lc16v8'


Linking 'C:\Archivos de programa\Cypress\Warp\bin\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\[Link]'.
Library 'ieee' => directory 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work'
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\[Link]'.

vhdlfe: No errors.

tovif V6.1 IR 28: High-level synthesis


Sun Sep 09 [Link] 2018

Linking 'C:\Archivos de programa\Cypress\Warp\bin\[Link]'.


Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\[Link]'.

tovif: No errors.

topld V6.1 IR 28: Synthesis and optimization


Sun Sep 09 [Link] 2018

Linking 'C:\Archivos de programa\Cypress\Warp\bin\[Link]'.


Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\[Link]'.
----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------

------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 3 PLD nodes.

topld: No errors.

----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

DESIGN HEADER INFORMATION ([Link])

Input File(s): [Link]


Device : c16v8
Package : palce16v8-15pc/pi
ReportFile : [Link]

Program Controls:
COMMAND LANGUAGE_VHDL
COMMAND PROPERTY BUS_HOLD ENABLE

Signal Requests:
GROUP USEPOL ALL
GROUP FAST_SLEW ALL

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

OPTIMIZATION OPTIONS ([Link])

Messages:
Information: Optimizing logic using best output polarity for signals:
c
Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 01/NOV/1999 [v4.02 ] 6.1 IR 28

LOGIC MINIMIZATION ()

Messages:

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

OPTIMIZATION OPTIONS ([Link])

Messages:

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

DESIGN EQUATIONS ([Link])

c =
a * b
+ /a * /b

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

DESIGN RULE CHECK ([Link])

Messages:
None.

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

PINOUT INFORMATION ([Link])

Messages:
Information: Checking for duplicate NODE logic.
None.

C16V8A
__________________________________________
b =| 1| |20|* not used
a =| 2| |19|= c
not used *| 3| |18|* not used
not used *| 4| |17|* not used
not used *| 5| |16|* not used
not used *| 6| |15|* not used
not used *| 7| |14|* not used
not used *| 8| |13|* not used
not used *| 9| |12|* not used
not used *|10| |11|* not used
__________________________________________

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

RESOURCE UTILIZATION ([Link])

Information: Macrocell Utilization.

Description Used Max


______________________________________
| Dedicated Inputs | 2 | 10 |
| Output Macrocells | 1 | 2 |
| I/O Macrocells | 0 | 6 |
______________________________________
3 / 18 = 16 %

Information: Output Logic Product Term Utilization.

Node# Output Signal Name Used Max


________________________________________
| 12 | Unused | 0 | 7 |
| 13 | Unused | 0 | 7 |
| 14 | Unused | 0 | 7 |
| 15 | Unused | 0 | 7 |
| 16 | Unused | 0 | 7 |
| 17 | Unused | 0 | 7 |
| 18 | Unused | 0 | 7 |
| 19 | c | 2 | 7 |
________________________________________
2 / 56 = 3 %

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

JEDEC ASSEMBLE ([Link])

Messages:
Information: Output file '[Link]' created.

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully at [Link]

Diseño de Circuito Sumador.


El objetivo del desarrollo de un circuito sumador es una vez dadas las entradas en
este caso el circuito estará compuesta por cuatro bits entradas, este devuelva la
suma de ambas entradas en tres bits.
Para esta práctica se usaron los siguientes componentes.
-PLD GAL 16v8, - Leds diferentes colores, -Switch, -Bornera, -Resistencias y cables
Código usado.

library ieee;

use ieee.std_logic_1164.all;

entity sum is

port (a: in bit_vector(3 downto 0);

s: out bit_vector(2 downto 0));

end sum;

architecture sumar of sum is

begin

process (a)

begin

case a is

when "0000" => s <= "000";


when "0001" => s <= "001";

when "0100" => s <= "001";

when "0010" => s <= "010";

when "0101" => s <= "010";

when "1000" => s <= "010";

when "0011" => s <= "011";

when "0110" => s <= "011";

when "1001" => s <= "011";

when "1100" => s <= "011";

when "0111" => s <= "100";

when "1010" => s <= "100";

when "1101" => s <= "100";

when "1011" => s <= "101";

when "1110" => s <= "101";

when others => s <= "110";

end case;

end process;

end sumar;
Archivo RPT.
| | | | | | |
_________________
-| |-
-| |-
-| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 6.1 IR 28
-| |- Copyright (C) 1991-2001 Cypress Semiconductor
|_______________|
| | | | | | |

======================================================================
Compiling: [Link]
Options: -yu -e10 -w100 -o2 -ygs -fP -v10 -dc16v8 -ppalce16v8l-15pc -b [Link]
-u [Link]
======================================================================

vhdlfe V6.1 IR 28: VHDL parser


Mon Sep 10 [Link] 2018

Library 'work' => directory 'lc16v8'


Linking 'C:\Archivos de programa\Cypress\Warp\bin\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\[Link]'.
Library 'ieee' => directory 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work'
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\[Link]'.

vhdlfe: No errors.

tovif V6.1 IR 28: High-level synthesis


Mon Sep 10 [Link] 2018

Linking 'C:\Archivos de programa\Cypress\Warp\bin\[Link]'.


Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\[Link]'.

tovif: No errors.

topld V6.1 IR 28: Synthesis and optimization


Mon Sep 10 [Link] 2018

Linking 'C:\Archivos de programa\Cypress\Warp\bin\[Link]'.


Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\common\work\[Link]'.
Linking 'C:\Archivos de programa\Cypress\Warp\lib\ieee\work\[Link]'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 0 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 7 PLD nodes.

topld: No errors.

----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

DESIGN HEADER INFORMATION ([Link])

Input File(s): [Link]


Device : c16v8
Package : palce16v8l-15pc
ReportFile : [Link]

Program Controls:
COMMAND LANGUAGE_VHDL
COMMAND PROPERTY BUS_HOLD ENABLE

Signal Requests:
GROUP USEPOL ALL
GROUP FAST_SLEW ALL

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

OPTIMIZATION OPTIONS ([Link])

Messages:
Information: Optimizing logic using best output polarity for signals:
s(0) s(1) s(2)

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 01/NOV/1999 [v4.02 ] 6.1 IR 28

LOGIC MINIMIZATION ()

Messages:

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

OPTIMIZATION OPTIONS ([Link])

Messages:

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

DESIGN EQUATIONS ([Link])

s(0) =
/a(0) * a(2)
+ a(0) * /a(2)

s(1) =
a(0) * a(1) * a(2) * a(3)
+ a(0) * /a(1) * a(2) * /a(3)
+ /a(0) * /a(1) * a(3)
+ /a(1) * /a(2) * a(3)
+ /a(0) * a(1) * /a(3)
+ a(1) * /a(2) * /a(3)

s(2) =
a(0) * a(2) * a(3)
+ a(0) * a(1) * a(2)
+ a(1) * a(3)

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

DESIGN RULE CHECK ([Link])

Messages:
None.

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

PINOUT INFORMATION ([Link])

Messages:
Information: Checking for duplicate NODE logic.
None.

C16V8A
__________________________________________
a(3) =| 1| |20|* not used
a(2) =| 2| |19|= s(1)
a(1) =| 3| |18|* not used
a(0) =| 4| |17|* not used
not used *| 5| |16|* not used
not used *| 6| |15|* not used
not used *| 7| |14|* not used
not used *| 8| |13|= s(0)
not used *| 9| |12|= s(2)
not used *|10| |11|* not used
__________________________________________

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

RESOURCE UTILIZATION ([Link])

Information: Macrocell Utilization.

Description Used Max


______________________________________
| Dedicated Inputs | 4 | 10 |
| Output Macrocells | 2 | 2 |
| I/O Macrocells | 1 | 6 |
______________________________________
7 / 18 = 38 %

Information: Output Logic Product Term Utilization.

Node# Output Signal Name Used Max


________________________________________
| 12 | s(2) | 3 | 7 |
| 13 | s(0) | 2 | 7 |
| 14 | Unused | 0 | 7 |
| 15 | Unused | 0 | 7 |
| 16 | Unused | 0 | 7 |
| 17 | Unused | 0 | 7 |
| 18 | Unused | 0 | 7 |
| 19 | s(1) | 6 | 7 |
________________________________________
11 / 56 = 19 %

Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: [Link] 31/03/2000 [v4.02 ] 6.1 IR 28

JEDEC ASSEMBLE ([Link])

Messages:
Information: Output file '[Link]' created.

Summary:
Error Count = 0 Warning Count = 0

Completed Successfully at [Link]

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