INGENIERA EN ELECTRNICA E INSTRUMENTACIN
Nombre: Zambrano Alex
Nivel: Quinto
Fecha de entrega: 17, julio de 2017
Ing. Amparo Meythaler
1. Consulte las 15 interrupciones del PIC16F877
INTCON
REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Timer 0 (interrupcin interna)
bit 2 TMR0IF: Sealizador de desbordamiento en TMR0
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
External 0 (Interrupcin externa)
bit 4 INTE : Bit de permiso de la interrucin externa por RB0/INT
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RB Port Change (Interrupcin externa)
bit 3 RBIE: Bit de permiso de interrucin por cambio en RB4-RB7
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
Registro de permiso de interrupciones 1 (PIE1)
Parallel Slave Port Read/Write ()
bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit (1) 1=
Enables the PSP read/write interrupt 0=
Disables the PSP read/write interrupt
A/D Converter (Interrupcin interna)
bit 6 ADIE : A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
USART Receive (Interrupcin externa)
bit 5 RCIE : USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
USART Transmit (Interrupcin interna)
bit 4 TXIE : USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
Synchronous Serial Port
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1 (Capture, Compare, PWM) (Interrupcin interna )
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
Timer 1 (Interrupcin interna)
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1=
Enables
the
TMR1
overflow
interrupt
0 = Disables the TMR1 overflow interrupt
Registro de permiso de interrupciones 2 (PIE2)
Comparator (Interrupcin interna)
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disable the Comparator interrupt
EEPROM Write Operation(Interrupcin interna)
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
Bus Collision(Interrupcin externa)
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
CCP2 (Capture, Compare, PWM) (Interrupcin interna)
bit 0 CCP2IE : CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Registros de los sealizadores de interrupciones 1 y 2 (PIR1 y PIR2)
PIR1 REGISTER (ADDRESS 0Ch)
TMR2 to PR2 Match (Interrupcin interna)
bit 1 TMR2IF : TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
Referencias bibliogrficas y de la web
[1][Link]
[2][Link]
[3][Link]
[4][Link]
[5][Link]
[6][Link]
