Powering ADC using Buck Boost Converter
Basic Explanation of my System:
The proposed design is a battery-powered wearable device that integrates advanced sensing and power management features. The system operates primarily from a single-cell Li-ion battery (3.7 V nominal) and includes a USB Type-C interface for charging and external power supply.
The device uses a battery charger with power-path management ( BQ24075) to ensure seamless operation:
When USB power is connected, the system is powered directly from the USB input while simultaneously charging the battery. When USB is disconnected, the system automatically switches to battery power without interruption. A fuel gauge IC monitors battery health parameters such as voltage, state of charge (SOC), and remaining capacity, reporting these to the microcontroller via I²C.
The system includes an electrochemical front end (AD5941) with a 16-bit ADC for high-precision sensor measurements.
Sensor signals are routed through a multiplexer (MUX) to the AD5941, which interfaces with an STM32 microcontroller development board for data acquisition and processing.
My Question
Initially, I considered using the ADM7155 low-noise LDO to power the ADC. However, given the system’s 3.7 V Li-ion battery, the limited headroom and dropout voltage of the ADM7155 present a challenge, especially as the battery discharges.
To address this, I decided to use a buck-boost converter, specifically the ADP2504, which can maintain a stable output voltage across the full battery discharge range and during USB power input. This ensures reliable operation for both the ADC and the microcontroller.
For powering the AD5941, my plan is to supply DVDD directly from the ADP2504 output and derive AVDD from DVDD using a ferrite bead for isolation, along with appropriate decoupling capacitors. This approach minimizes noise coupling between digital and analog domains while maintaining a compact and efficient power architecture.
Could you confirm if this is an optimal solution for powering the AD5941 in a wearable application.
Or may I know you have any suggestions for better circuit /IC options.
1 answer
The following users marked this post as Works for me:
| User | Comment | Date |
|---|---|---|
| newbie | (no comment) | Dec 16, 2025 at 15:55 |
This all comes down to how much noise you can tolerate.
You are using a 16 bit A/D. That means each count is 1/65535 of the input range. If that input range is 3.3 V, for example, then each digital count represents 50 µV.
Now look at the ripple on the power voltage. Ideally you want to attenuate that to below 50 µV. You therefore need to know the peak to peak size of the ripple, and the frequency of that ripple. You can only design the L-R-C filter after you know what it needs to accomplish.
Let's say the power supply ripple is 50 mV peak to peak at 100 kHz. You want to attenuate that by 1000. Another way of saying the same thing is that you want to attenuate by 60 dB.
The only limitation on how low frequency the filter can go is startup considerations. During normal operation, the output of the filter is supposed to be a constant (0 frequency). The slower you make the filter, the longer the system will take after powerup to be ready to use. There may also be some limitation on the Avdd voltage relative to the Dvdd voltage. Check the datasheet.
I usually use two ferrite chip inductors each followed by a capacitor to ground in situations like this, but I'm also usually not requiring the result to be good to 16 bits. At 16 bits, there are a lot of other issues to consider than just reference voltage noise.
The rolloff frequency of a single L-C filter is 1/(2π⋅Sqrt(LC)). There will actually be two poles at the roloff frequency. Let's say the chip inductor is 1 µH, and see what we get with 20 µF following it.
1/(2π⋅Sqrt((1 µH)(20 µF)) = 36 kHz
That's only going to attenuate 100 kHz by about 8, or about 18 dB. Another one of these would add another 18 dB (actually a bit more because they interact, but let's keep it simple for now). That leaves 24 dB to go. A third L-C would get you to 54 dB, so only another 6 dB to go. Remember this was just an example to see where we're at. Three chip inductors followed by capacitors isn't too bad. There is some wiggle room here in using more capacitance, and maybe the ripple frequency is higher, or you don't really need 16 bits. Those are all things for you do decide.
The above shows that this problem can be addressed with chip inductors and capacitors, but that the requirements are stringent enough that you have to do the math and not just slap down "the usual".
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