Integrated Power Electronics and

Maximum Power Point Tracking for

Microgranular PV Energy Harvesting

Von der Fakultät für Elektrotechnik und Informationstechnik

der Rheinisch-Westfälischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines Doktors der
Ingenieurwissenschaften genehmigte Dissertation

vorgelegt von

M. Sc.
Leo Rolff
aus
Köln

Berichter: Universitätsprofessor Dr.-Ing. Stefan Heinen

Universitätsprofessor Dr.-Ing. Stefan van Waasen

Tag der mündlichen Prüfung: 11.06.2021

Diese Dissertation ist auf den Internetseiten der Universitätsbibliothek online verfügbar.
There and back again.
 Acknowledgement

An dieser Stelle möchte ich mich bei einigen Menschen bedanken ohne
welche diese Arbeit nicht entstanden wäre.
Mein erster Dank geht an Stefan Heinen der mir die Möglichkeit gegeben
hat dieses Thema am IAS zu bearbeiten.
Ganz besonders danke ich meinen Bürokolleg*innen Michael und Eva. Für
die gute Zusammenarbeit und die gegenseitige Unterstützung ohne die ein
Tape-Out nicht zu schaffen gewesen wäre. Im Speziellen danke ich Michael
und auch Léon für die Fortführung der Arbeit am MPPT zu einem Tape-
Out.
Ein weiterer Dank geht an Markus. Für das freundschaftliche Verhältnis,
die lange gemeinsame Zeit am IAS und ohne den ich die Arbeit dort wohl
niemals aufgenommen hätte.
Weiterhin danke ich Tobi und Tobi, für die gute gemeinsame Pendelzeit
und das fungieren als Diskussionspartner bei allen möglichen auftretenden
Themen der Wissenschaft, der Universität und des Lebens. Erwähnung
verdienen ebenfalls Rieke und Ralf, die mich über manche verwaltung-
stechnischen Hürden gehoben haben und an die ich mich jederzeit mit ver-
schiedensten Fragen wenden konnte.
Und nicht zuletzt geht ein riesen Dank an Nadine. Zum Einen für die
signifikante Verbesserung der Interpunktion dieser Arbeit. Vor allem aber
für die Unterstützung während der Arbeit und dafür, dass sie mich, meine
Launen und die viele Zeit die diese Arbeit gekostet hat ausgehalten hat.

III
 Contents

List of Figures VII

List of Tables X

1 Introduction 1
1.1 Aim of this work . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Structure of this work . . . . . . . . . . . . . . . . . . . . . 4

2 Basic Circuits 7
2.1 DC-DC converters . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Buck Converter . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Boost converter . . . . . . . . . . . . . . . . . . . . . 10
2.2 Digital to Analogue Converter . . . . . . . . . . . . . . . . . 11
2.3 Maximum Power Point Tracking . . . . . . . . . . . . . . . 14
2.3.1 Characteristics of PV Modules . . . . . . . . . . . . 14
2.3.2 PV Energy Harvesting Topologies . . . . . . . . . . 16
2.3.3 MPPT techniques . . . . . . . . . . . . . . . . . . . 23
2.3.4 Presentation of different MPPT techniques . . . . . 25

3 Power Management Unit 35

3.1 Undervoltage Lockout Basics . . . . . . . . . . . . . . . . . 40
3.1.1 Conditions and Requirements . . . . . . . . . . . . . 42
3.1.2 UVLO Concepts . . . . . . . . . . . . . . . . . . . . 45
3.2 Selection of PMU Architecture . . . . . . . . . . . . . . . . 45
3.2.1 Selection of UVLO concept . . . . . . . . . . . . . . 46
3.2.2 Bandgap reference . . . . . . . . . . . . . . . . . . . 48

IV
 3.3 Linear Voltage regulators . . . . . . . . . . . . . . . . . . . 51
3.3.1 Self Starting 5 V LDO . . . . . . . . . . . . . . . . . 53
3.3.2 Auxiliary 1.8 V LDO . . . . . . . . . . . . . . . . . . 57
3.4 DCDC Buck Converter . . . . . . . . . . . . . . . . . . . . . 58
3.4.1 PFM Control . . . . . . . . . . . . . . . . . . . . . . 58
3.4.2 High voltage Comparator . . . . . . . . . . . . . . . 61
3.4.3 Improved charge reuse of current sink . . . . . . . . 61
3.5 PMU Control . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.5.1 Start-up Flowchart . . . . . . . . . . . . . . . . . . . 63
3.5.2 Power Good Detection . . . . . . . . . . . . . . . . . 63
3.5.3 Debug and Backup Features . . . . . . . . . . . . . . 67
3.5.4 Logic of the Control . . . . . . . . . . . . . . . . . . 69
3.6 Measurements of the PMU . . . . . . . . . . . . . . . . . . 71
3.6.1 Measurement 1 V15V = 10 V . . . . . . . . . . . . . . 74
3.6.2 Measurement 2 V15V = 15 V . . . . . . . . . . . . . . 75
3.6.3 Buck Converter Measurements . . . . . . . . . . . . 77
3.7 Further Improvements of the Start-up LDO . . . . . . . . . 80
3.7.1 Leakage activated start-up circuit . . . . . . . . . . . 81
3.7.2 Improved start-up detection . . . . . . . . . . . . . . 81
3.7.3 Start-up detection with reference current . . . . . . 82

4 Energy Harvesting ASIC 85

4.1 Selection of MPPT Concept . . . . . . . . . . . . . . . . . . 86
4.2 System overview . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2.1 Requirements . . . . . . . . . . . . . . . . . . . . . . 89
4.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . 91
4.3 Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . 93
4.4 Power Management Unit . . . . . . . . . . . . . . . . . . . . 96
4.4.1 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.4.2 Bandgap Reference . . . . . . . . . . . . . . . . . . . 99
4.4.3 LDO 1.8 V . . . . . . . . . . . . . . . . . . . . . . . 100
4.4.4 LDO 5 V Drive . . . . . . . . . . . . . . . . . . . . . 102
4.4.5 LDO 5 V Analogue . . . . . . . . . . . . . . . . . . . 103
4.4.6 Auxiliary LDO . . . . . . . . . . . . . . . . . . . . . 106
4.5 Implemented MPPT Concept . . . . . . . . . . . . . . . . . 109
4.5.1 Principle and Adaptions . . . . . . . . . . . . . . . . 109
4.5.2 Implementation and MPPT Procedure . . . . . . . . 110
4.5.3 Convergence . . . . . . . . . . . . . . . . . . . . . . 113
4.5.4 Design requirements of the DACs and Comparators 116

V
 4.6 Implementation of the Functional Blocks . . . . . . . . . . . 119
4.6.1 Comparators . . . . . . . . . . . . . . . . . . . . . . 120
4.6.2 DACs . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.6.3 Digital Implementation of Algorithms . . . . . . . . 131
4.7 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 136
4.7.1 Static Tracking Efficiency . . . . . . . . . . . . . . . 137
4.7.2 Tracking Speed . . . . . . . . . . . . . . . . . . . . . 140
4.7.3 Efficiency at Different Irradiance Profiles . . . . . . 142
4.8 Appended: Measurement Results . . . . . . . . . . . . . . . 146

5 Conclusion and Outlook 151

Bibliography 155

Curriculum Vitae 169

List of Publications 171

VI
 List of Figures

1.1 Historical data on the world energy demand and global tem-
perature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Global PV market forecast and LCOE [3]. . . . . . . . . . . 3
1.3 PV in a bicycle path surface. . . . . . . . . . . . . . . . . . 5

2.1 Schematic of a buck converter. . . . . . . . . . . . . . . . . 8

2.2 Vsw and IL of the buck converter operation. . . . . . . . . . 9
2.3 Schematic of a boost converter. . . . . . . . . . . . . . . . . 11
2.4 Block diagram of an R2R-ladder based DAC. . . . . . . . . 11
2.5 Schematic of a DAC with an R2R-ladder. . . . . . . . . . . 12
2.6 Illustration of INL and DNL for 3 bit DAC [4, p. 504]. . . . 12
2.7 Block diagram of a SAR ADC utilizing a DAC. . . . . . . . 13
2.8 VI characteristic of PV cell. . . . . . . . . . . . . . . . . . . 14
2.9 PV module with bypass diode. . . . . . . . . . . . . . . . . 16
2.10 General PV System with applied MPPT. . . . . . . . . . . 17
2.11 String level MPPT topology [119]. . . . . . . . . . . . . . . 18
2.12 Microinverter MPPT topology [119]. . . . . . . . . . . . . . 19
2.13 Module power optimizer topology [119]. . . . . . . . . . . . 20
2.14 Submodule power optimizer topology [119]. . . . . . . . . . 21
2.15 Substring buck-/boost converter topology. . . . . . . . . . . 22
2.16 Communication options. . . . . . . . . . . . . . . . . . . . . 25
2.17 Flow chart for the standard P&O technique. . . . . . . . . . 27
2.18 Flow chart for the basic InCond technique. . . . . . . . . . 29
2.19 Schematic illustrating the principle of the RCC technique. . 31
2.20 Modified MPPT based on RCC [6]. . . . . . . . . . . . . . . 32

3.1 Block diagram of the complete gate driver IC. . . . . . . . . 37

VII
3.2 Output stage of the gate driver IC. . . . . . . . . . . . . . . 37
3.3 Graph of a switching event. . . . . . . . . . . . . . . . . . . 38
3.4 High side driver of the PMOS output stage from figure 3.2. 39
3.5 Operating modes of an ASIC. . . . . . . . . . . . . . . . . . 41
3.6 NAND to inhibit signal transmission. . . . . . . . . . . . . . 43
3.7 Inhibiting signal. . . . . . . . . . . . . . . . . . . . . . . . . 44
3.8 Generate a RESET signal at off state. . . . . . . . . . . . . 44
3.9 Level shifter that flips to desired state during start-up. . . . 44
3.10 Qualitative start-up voltage sequence. . . . . . . . . . . . . 47
3.11 Block diagramm of the PMU architecture. . . . . . . . . . . 48
3.12 Block diagram of the bandgap reference. . . . . . . . . . . . 49
3.13 Schematic of the bandgap reference. . . . . . . . . . . . . . 50
3.14 Principle of an LDO. . . . . . . . . . . . . . . . . . . . . . . 52
3.15 Schematic of the core of the LDO. . . . . . . . . . . . . . . 52
3.16 Schematic of the LDO with start-up circuitry. . . . . . . . . 54
3.17 Different start-up behaviour for different start-up times. . . 54
3.18 Schematic of the start-up detection circuitry. . . . . . . . . 57
3.19 Schematic of the auxiliary 1.8 V LDO with enable circuitry. 58
3.20 Block diagram of the implemented buck converter. . . . . . 60
3.21 Schematic of the high voltage comparator C2. . . . . . . . . 62
3.22 MISO principle for the buck converter [100]. . . . . . . . . . 62
3.23 Flowchart of regular start-up sequence. . . . . . . . . . . . . 64
3.24 Voltage monitoring of V5V . . . . . . . . . . . . . . . . . . . 65
3.25 Calculation of PGV5 . . . . . . . . . . . . . . . . . . . . . . . 66
3.26 Voltage monitoring of V1.8V and V15V . . . . . . . . . . . . . 67
3.27 Trimming of the feedback paths. . . . . . . . . . . . . . . . 68
3.28 Control logic for start-up. . . . . . . . . . . . . . . . . . . . 71
3.29 Generation of auxiliary supply voltage. . . . . . . . . . . . . 72
3.30 Micrograph of gate driver IC. . . . . . . . . . . . . . . . . . 72
3.31 Micrograph of the PMU of the gate driver IC. . . . . . . . . 73
3.32 Measurement with V15V = 10 V. . . . . . . . . . . . . . . . . 75
3.33 Detail view of V1.8V . . . . . . . . . . . . . . . . . . . . . . . 76
3.34 Start-up for V15V = 15 V. . . . . . . . . . . . . . . . . . . . 76
3.35 Measurement with V15V = 15 V showing Vsw . . . . . . . . . 77
3.36 Detail of buck converter converter cycle. . . . . . . . . . . . 78
3.37 Buck converter cycle showing the control functioning. . . . 79
3.38 Different buck converter cycle lengths. . . . . . . . . . . . . 80
3.39 Improved start-up circuit for the LDO with leakage activation. 82
3.40 Start-up circuit for the LDO with improved start-up detection. 83
3.41 Start-up detection for the LDO with given reference current. 84

VIII
4.1 MPPT from figure 2.20 with adapted perturbation. . . . . . 88
4.2 Block diagram of the ASIC. . . . . . . . . . . . . . . . . . . 92
4.3 Block diagram of the implemented boost converter. . . . . . 94
4.4 Block diagram of the PMU. . . . . . . . . . . . . . . . . . . 97
4.5 Block diagram of the UVLO. . . . . . . . . . . . . . . . . . 99
4.6 Block diagram of the bandgap reference. . . . . . . . . . . . 100
4.7 Block diagram of the 1.8 V LDO. . . . . . . . . . . . . . . . 101
4.8 Block diagram of the 5 V LDO for the output drivers. . . . 103
4.9 Block diagram of the 5 V LDO for constant loads. . . . . . 104
4.10 Achieved PSRR at different load currents. . . . . . . . . . . 105
4.11 Source follower principle of the auxiliary LDO. . . . . . . . 106
4.12 Implementation of the auxiliary LDO. . . . . . . . . . . . . 108
4.13 System diagram of the selected MPPT. . . . . . . . . . . . 110
4.14 Implementation of the MPPT. . . . . . . . . . . . . . . . . 111
4.15 Flow chart of the MPPT procedure. . . . . . . . . . . . . . 113
4.16 A simple closed loop with an OP and an integrator. . . . . 118
4.17 Structure of the DM comparator C2. . . . . . . . . . . . . . 120
4.18 Structure of the MEAS comparator C1. . . . . . . . . . . . 121
4.19 Clock synchronization for the sampling of the comparators. 123
4.20 Application of the DM DAC. . . . . . . . . . . . . . . . . . 125
4.21 Block diagram of the LSB/MSB DAC. . . . . . . . . . . . . 126
4.22 Implementation of the DM DAC. . . . . . . . . . . . . . . . 127
4.23 Block diagram of the CTRL DAC. . . . . . . . . . . . . . . 128
4.24 Block diagram of the MEAS DAC. . . . . . . . . . . . . . . 129
4.25 MSB R2R current injection principle of the MEAS DAC. . 130
4.26 Output stage of the MEAS DAC. . . . . . . . . . . . . . . . 131
4.27 Flow chart of the MEAS DAC adjustment routine. . . . . . 133
4.28 Flow chart of the DM DAC adjustment routine. . . . . . . . 135
4.29 Test-bench to simulate the MPPT. . . . . . . . . . . . . . . 138
4.30 Comparison of schematic to model for 50 % irradiance. . . . 139
4.31 Tracking of VPV for different steps of the irradiance. . . . . 141
4.32 Different simulated irradiance profiles. . . . . . . . . . . . . 143
4.33 Tracking efficiency of the slow slopes. . . . . . . . . . . . . . 144
4.34 Tracking efficiency of the bike, car and comparison profile. . 145
4.35 Micrograph of the application specific integrated circiut (ASIC).147
4.36 Picture of the measurment printed circuit board (PCB). . . 147
4.37 Settling for 45 % and 100 % of the maximum input power. . 148
4.38 Impact of input output (IO) cell series resistance. . . . . . . 149
4.39 Variations of input power during steady state. . . . . . . . . 150

IX
 List of Tables

3.1 Requirements and behaviour of the different supply voltages. 40

4.1 Comparison of topologies. . . . . . . . . . . . . . . . . . . . 86

4.2 Comparison of MPPT techniques. . . . . . . . . . . . . . . 87
4.3 Specifications for the boost converter. . . . . . . . . . . . . 90
4.4 Simulation results for the DAC. . . . . . . . . . . . . . . . . 127
4.5 Summarized simulation results for static input irradiance. . 139
4.6 Tracking efficiency at different input [96]. . . . . . . . . . . 140
4.7 Summarized simulation results for an input irradiance step. 142
4.8 Average tracking efficiencies of the simulated scenarios. . . 146
4.9 Measured tracking efficiencies. . . . . . . . . . . . . . . . . . 149

X
 Third Party Contributions

This thesis focuses on the implementation details of a maximum power

point tracking technique into an IC and the therefore required preliminary
work. Accomplishing the implementation of two different ICs would have
been impossible without the contribution of others.
Eva Schulte Bocholt did the main work of the first tape-out, the inte-
grated gate driver, including the main functionality, pad connection and
top level routing. The implementation of the power management unit was
an isolated sub-circuit which had to fulfil the requirements of the main
application and provides a standalone capability to the IC.
Jonas Meier provided support to the implementation of the digital part of
the second tape-out, the MPPT IC and implemented the SPI core.
Johannes Bastl provided the DIFG tool, highly improving the reliability
and the implementation speed of the on-chip SPI.
Fabian Speicher implemented the top level models of the MPPT subcircuits,
which dramatically reduced the simulation time and allowed the simulation
of the profiles to evaluate the dynamic MPPT performance.
Léon Weihs implemented the 1.8 V LDO as his master thesis and contin-
ued his support of the IC implementation by performing several system
simulations afterwards.
Michael Hanhart, last but definitively not least, worked together with the
author at the whole implementation process of the MPPT IC. He im-
plemented the complete boost converter, the 5 V low dropout regulators
(LDOs), the bandgap reference and the undervoltage lockout.

XI
Appended: After my departure at IAS, Léon Weihs and Michael Hanhart
finalized the tapeout of the ASIC. The measurements of the ASIC were
prepared and mainly performed by Michael Hanhart aswell.

XII
 Chapter 1
Introduction

The industrial revolution is considered to be the second fundamental rev-

olution in mankind, which deeply changed society and influenced almost
every aspect of daily life [37]. One part of this ongoing process is, the elec-
trification, which took place in Europe and the US from the 1880s to the
1930s. It was boosted by major innovations on generation, transmission
and usage of electrical power [130, 131]. Replacing shafts by wires brought
reliably available electrical power to nearly every location in the western
world [22]. Following this trend, electric techniques replaced mechanical
ones in many applications, which is currently observable at electric cars.
This is accompanied by a still increasing demand in energy which is ex-
pected to continue. Figure 1.1a shows the history and a forecast on the
world’s energy demand and by which technologies it is fulfilled [87].
The excessive usage of fossil energy in the past has caused a significant
global warming as shown in figure 1.1b, which is a major part of the cur-
rently observed anthropogenic climate change. The consequences of this
climate change threatens billions of people by an increase of sea level,
higher probability of droughts and extreme weather conditions [71]. For
reasons of justice it is urgently necessary to counter or at least mitigate

1
 1 Introduction

Billion toe
20

Renewables

Hydro
15
Nuclear

Coal

Gas
10
Oil

0
1970 1980 1990 2000 2010 2020 2030 2040

(a) World energy demand [87]. (b) Global temperature 1880-2020 [38, 64].

Figure 1.1: Historical data on the world energy demand and global temper-
ature.

the impact of this climate change [54]. Therefore the United Nations (UN)
agreed in the paris agreement to keep the global warming “well below 2 ◦C”
and “pursuing efforts to limit the temperature increase to 1.5 ◦C above pre-
industrial level” [83]. To achieve this aim the increase on greenhouse gas
(GHG) emissions has to be stopped as fast as possible. This can only be
sustainably fulfilled by renewable energies, of which wind and solar power
currently have the highest importance. Together, they have the potential
to provide a reliable energy supply without the need for fossil fuels [45, 46,
108].
Following from the need for renewable energy the solar market has devel-
oped an impressive dynamic in the last years. In 2019 about 117 GW peak
were installed and the cumulative installed power exceeded 630 GW peak
which is an increase of 1500 % since 2010 [3]. This development is expected
to continue in the next years, even if a small decrease due to the corona
pandemic in 2020 is predicted, as shown in figure 1.2a. This dynamic is
caused by two main reasons. Political interventions promoting solar energy
in the light of global warming and an increasing competitiveness in form of
rapidly falling levelized cost of electricity (LCOE) as shown in figure 1.2b.
The endorsed massive deployment of solar energy harvesting comes along
with a strong land consumption [3]. Building integrated photovoltaic (BIPV)
has the potential to generate energy without requiring additional areas. In-
stead, it utilizes the available facades and rooftops of houses. The share
of BIPV on the solar energy generation increased in the last years and
is expected to grow further [91]. Another promising trend is infrastruc-
ture integrated photovoltaic (IIPV), where the photovoltaic (PV) energy

2
 1 Introduction

(a) (b)

Figure 1.2: Global PV market forecast and LCOE [3].

generation is attached to existing infrastructure like roads, noise barriers,

bus stops and many other kinds of infrastructure [150]. Here, there are
technical challenges like highly different and rapidly changing irradiance
conditions, due to partial shading as well as passing cars.

1.1 Aim of this work

This work aims to implement a cost and energy efficient PV energy har-
vesting ASIC to enable new applications like BIPV or IIPV and reduce
the effort for current applications. A main focus is set to the maximum
power point tracker (MPPT), which optimizes the operating point of the
PV module. Therefore it has to be flexible, robust and fast. Moreover, the
start-up and power management of the ASIC is investigated. Such tech-
niques have the potential to reduce the bill of materials (BOM) of several
different integrated power electronic systems.
In the research projects ”Energieoptimiertes Quartier Margarethenhöhe Es-
sen” (ENQM) and ”Rolling Solar” the Chair for integrated analog circuits
(IAS) is researching on BIPV as well as IIPV. The ENQM project aims
to increase the energy yield of roof tile integrated solar cells [29]. A main
focus is the implementation into heritage protected buildings where the
application of standard PV modules is not possible, since it would signifi-
cantly change the appearance. Therefore the energy of very small modules
in the size of a single roof tile have to be harvested efficiently. Similar
requirements apply to other BIPV as in facade integrated PV installa-
tions. Instead on focusing on rooftops ”Rolling Solar” is researching to

3
 1 Introduction

integrate PV cells into the road surface and noise barriers as illustrated in
figure 1.3 [59]. Here the PV cells face partial shading and rapidly changing
shading conditions from passing cars or bicycles. Both applications have
to mitigate energy losses due to uneven irradiance. Therefore it is benefi-
cial to implement the MPPT on smaller entities rather than for long PV
strings. Following from this, a cost efficient solution, which is capable of
performing the MPPT on such small entities, is required in vast numbers.
This is enabled by the use of a monolithical integrated energy harvesting
ASIC on complementary MOS (CMOS) basis. Due to the huge market,
a small share already allows to easily pay off for the required initial cost
of the monolithic integration. The integrated approach has the additional
potential to offer higher flexibility to the applier. Therefore it should be
compatible to standard 9 A PV cells. Because of the low cost and the
increased expected shading only short strings should be used. Therefore
the solution should allow the flexible stacking of these short strings into
modules and systems. Following from this, the resulting voltages for each
ASIC are expected to be relatively low, which suits well for the monolithic
integration. To reduce the BOM and thus the costs, as much as economi-
cal possible should be implemented into the ASIC. Especially the need for
additional external power management should be minimized, which would
also translate to a higher lifetime of the circuit being expected.
Other projects at the IAS have shown the power management (PMM) to be
a critical part. Therefore the implementation of the ASIC was set onto the
experience from a former project, where a power management unit (PMU)
was implemented in a gate driver integrated circuit (IC). Considering the
trend of increasingly complex power electronic systems, the application
to an energy harvesting ASIC and an gate driver integrated circuit (IC)
are only examples for many other applications of integrated smart power
electronics.

1.2 Structure of this work

This work approaches the implementation of a PV energy harvesting ASIC
in three chapters. First the basics of DC to DC (DC-DC) converters, digital
to analogue converters (DACs) and MPPT are summarized in chapter 2.
These form the basis for several decisions in the development of the ASIC.
A special focus is set on the MPPT, for which different energy harvesting

4
 1 Introduction

Figure 1.3: PV in a bicycle path surface.

topologies and tracking techniques are shown. The decision on the imple-
mented topology and MPPT technique in chapter 4 strongly relies on the
presented basics.
The implementation of the PV energy harvesting ASIC uses the experience
gained from another chip, implemented at the IAS. This implementation of
a PMU in an integrated gate driver is discussed in chapter 3. Based on the
requirements and conditions, especially regarding the undervoltage lockout
(UVLO) of the ASIC, the architecture of the PMU is selected. Subsequently
the implemented LDOs, buck converter and bandgap reference are shown.
The principle of the developed start-up LDO, which enables the ASIC to
independently start after the supply voltage is applied, is presented. The
function of the PMU with special consideration of the start-up is shown by
measurement results. Finally further possible improvements of the start-up
LDO based on the gained experience are discussed .
The actual implementation of the PV energy harvesting ASIC is presented
in chapter 4. Based on the desired application and the MPPT basics, the
decision for the substring boost topology and an MPPT technique, which
combines the ripple correlation control (RCC) and incremental conduc-
tance (InCond) technique together, is discussed. Based on these decisions
the requirements to the boost converter and the MPPT are developed and
the resulting system block diagram is presented. Subsequently the different
functional blocks are presented. Since the focus of this work is set to the
MPPT, the implementation of the boost converter is only briefly shown.
The PMU is presented in detail particularly regarding the start-up of the
ASIC. The implementation of the MPPT is discussed in detail, showing
the convergence to the maximum power point (MPP) and presenting the
implemented circuits as well as the digital algorithm. Following this, the

5
 1 Introduction

implemented circuits are mentioned especially regarding the relaxed re-

quirements due to the MPPT principle. Finally simulation results showing
the aimed performance are given.

6
 Chapter 2
Basic Circuits

This chapter presents the basics of DC-DC converters and digital to ana-
logue converters (DACs) on which the implemented ASICs rely. After this,
the basics of maximum power point trackers (MPPTs) are investigated and
different solutions for the MPPT are presented.

2.1 DC-DC converters

DC-DC converters are power converters, which convert an input voltage Vin
into an output voltage Vout . This is realized by a periodically switching
element and an energy storage [30]. Many different topologies are devel-
oped, discussed and used in commercial products. Here, only two basic
topologies, the buck converter and the boost converter, are mentioned, as
they already show a sufficient flexibility and efficiency for the dedicated
application. Further information can be found in [16, 30].

7
 2 Basic Circuits

2.1.1 Buck Converter

The buck converter transfers the input voltage Vin to a lower output voltage
Vout with the same polarity [16, p.6]. Figure 2.1 shows the standard buck
converter. At the input the capacity Cin buffers Vin to reduce the influence
of the switching. The power switch M2 can be implemented as metal oxide
semiconductor field effect transistor (MOSFET) or another power switch
and connects Vsw with Vin . Together with the power switch M2, it switches
Vsw between Vin and GND, which controls the current in the inductor L.
This current is constantly conducted into the output Vout , which is buffered
by Cout .

M2 Vsw L
Vin Vout

Cin ϕ2 ϕ1 M1 Cout

Figure 2.1: Schematic of a buck converter.

The buck converter periodically switches M1 and M2 with Φ1 and Φ2 . This

forces Vsw to alternate between GND and Vin . Figure 2.2 illustrates the
buck converter switching. For a timespan ton , Vsw is connected to Vin
when M2 is switched on. During this time, the voltage across the inductor
is V∆ = Vin − Vout . Thus the current IL increases up to IL,max when
M2 is switched off and M1 is switched on. Now Vsw is at GND and IL is
reduced down to IL,min . After a timespan toff , M1 is switched off and M2
is switched on again and the cycle starts over again [132, p.913].
During this operation mode, the ratio of Vin to Vout only depends on the
duty cycle D = tont+t
on
off
. It can be calculated to

Vout = D · Vin (2.1)

as shown in [30, pp.13-14]. Since IL is continuously flowing in this mode, it

is called the continuous conduction mode (CCM). If IL,min gets below zero,
it is beneficial to change to the discontinuous conduction mode (DCM). In
this mode, IL = 0 A for an additional timespan. Thereby, the efficiency
can maintain high at light loads where otherwise the losses in the power
switches would cause a drop in efficiency. However, this mode comes along

8
 2 Basic Circuits

Vin
ton
Vout
toff
Vsw
0V
IL,max

IL,avg

IL,min IL
t
Time
Figure 2.2: Vsw and IL of the buck converter operation.

with an increased voltage ripple since Vout is supplied out of Cout during
the idle time [30, pp.103 ff.].
Many different control techniques are reported for buck converters. With-
out a distinct control loop, the buck converter is operated in a pulse width
modulation (PWM) control [132, p.918]. Here the duty cycle is set ex-
ternally, resulting in an output voltage according to equation 2.1. These
controls have a very poor transient performance and are normally used as
a basis for a voltage mode control [132, p.918]. This control features an
additional control which feeds back Vout to adjust the PWM duty cycle [69,
82, 149]. A voltage mode control is widely used and shows a good perfor-
mance. However, the response time still is limited since a change in load
first has to affect Vout . Moreover the compensation of the loop control is
complicated due to the double pole from the LC output filter and the input
dependent loop gain [69].
To build faster controls, the current mode control, especially the peak cur-
rent control, was developed [11, 15, 20, 69]. A control loop only controlling
the inductor current is added. This control loop only features a single pole
which allows a relatively simple implementation. Thereby, the enclosing
voltage control loop only sees a single pole too, avoiding the mentioned
stability issues [132, p.920]. However, this control requires a slope compen-
sation, if the duty cycle can get above D = 50 % since the control loop gets

9
 2 Basic Circuits

unstable then [20].

The mentioned control techniques are only suitable for a CCM operation.
For light load operations, this often results in low efficiencies since the
switching losses scale to the switching frequency rather then the load. The
pulse frequency modulation (PFM) control allows for an operation in the
DCM [132, p.922] [106, 129, 151]. Here the power switches are not switched
with a fixed frequency. Instead, on-pulses with a distinct pulse duration
transfer an amount of energy to the output when the output voltage gets too
low [132, p.922]. This allows a high conversion efficiency for a wide range
of loads. A drawback of this control is the varying switching frequency,
which aggravates the estimation of on-chip interference and electromagnetic
interference (EMI) [132, p.922].
A digital control technique is the hysteresis control [24] [118, p.34]. Here the
inductor current is continuously monitored and kept in a specified window
by switching M1 and M2 when the current is above or below. The major
advantage of the hysteresis control is its inherent stability at an area and
energy efficient implementation[118, p.34]. However, it has the drawbacks
of the PFM and requires a continuous control of the inductor current.
Moreover in a fully digital implementation, a steady state is never really
achieved due to the discretization of the control signals.

2.1.2 Boost converter

The boost converter allows to transfer energy from an input voltage Vin to
a higher output voltage Vout with a high efficiency [30, p.22]. Figure 2.3
shows the schematic of a standard boost converter. The boost converter,
too, needs the buffering capacities Cin and Cout at the input and output,
an inductor and two power switches M1 and M2 which control the switch-
ing potential Vsw . In comparison to the buck converter, L and M2 are
exchanged, and thus L is always connected to Vin . Similar to the buck
converter, the boost converter has a CCM and a DCM operation mode
with equal characteristics [80, 144]. The output voltage in CCM is
1
Vout = Vin · (2.2)
1−D
depending on Vin and D. Thus, Vout is always greater or equal to Vin .
Because of the big similarity to buck converters, the control of a boost

10
 2 Basic Circuits

converter can be implemented using the same techniques [132, p.924].

L Vsw M2
Vin Vout

Cin ϕ1 M1 ϕ2 Cout

Figure 2.3: Schematic of a boost converter.

2.2 Digital to Analogue Converter

A digital to analogue converter (DAC) converts a given digital input to
an analogue output [132, p. 970][4, p. 499]. The output is in most cases
either an output voltage or current. There are several different topologies
for DACs like the PWM, oversampling and binary-weighted. However, the
binary weighted topology is used most, when an accurate output signal is
required [132, p. 971]. Figure 2.4 shows the implementation of a binary
weighted DAC which is based on the switching of an R2R-ladder. The
input to the R2R-ladder is a digital bus and a reference voltage Vref . The
R2R-ladder scales the output voltage VR2R in reference to IN and Vref .
The operational amplifier (OP) buffers VR2R to provide a low impedance
Vout .

IN Vout
R2R ladder
Vref VR2R

Figure 2.4: Block diagram of an R2R-ladder based DAC.

Figure 2.5 shows the schematic implementation of an R2R-ladder based

DAC. The R2R-ladder is built up of regularly arranged resistors of size R
and 2R. The switches S1-4 switch the bottom taps of 2R to either Vref or
GND controlled by IN. This leads to a voltage of
IN
Vout = Vref · (2.3)
16

11
 2 Basic Circuits

with the binary represented input value IN. This principle scales easily to
an arbitrary number of bits. The monotony and absolute output value
accuracy is then only limited by the relative matching of the resistors.
R R R VR2R
Vout

2R 2R 2R 2R 2R
LSB S1 S2 S3 S4
IN MSB
Vref

Figure 2.5: Schematic of a DAC with an R2R-ladder.

To characterize DACs different non-idealities are considered. The most

important static characteristics are the differential nonlinearity (DNL) and
the integral nonlinearity (INL). Figure 2.6 shows a graph which illustrates
these characteristics using the example of a 3 bit DAC. The resulting output
voltage normalized to the full scale output is plotted dependent on the
binary input IN. As a reference, the ideal characteristic of an DAC with an
infinite resolution is plotted in blue. The ideal 3 bit characteristic is shown
in the dashed red trace and the actual characteristic of the sample DAC is
shown in green.
1
7 inf. res. char. +1 lsb INL
8 ideal char.
6
8 actual char.
normalized Vout

5
8
4
8
3
−1.2 lsb DNL +1 lsb DNL
8
2
+0.5 lsb DNL
8
1
−0.7 lsb INL
8
non-monotonicity
0
000 001 010 011 100 101 110 111
IN [bit]

Figure 2.6: Illustration of INL and DNL for 3 bit DAC [4, p. 504].

Multiple different integral nonlinearity (INL) and differential nonlinearity

(DNL) occur in this characteristic. At the step from ”001” to ”010”, the

12
 2 Basic Circuits

actual characteristic increases 0.5 LSB too munch which equals a DN L =

+0.5 LSB. At the next step, the characteristic does not increase but rather
decrease. Since thereby the step is −1.2 LSB smaller then expected, this
is a DN L = −1.2 LSB. This causes an IN L = −0.7 LSB between ”011”
and ”100”. At the step to ”101”, the output voltage increases by double
the expected amount resulting in a DN L = +1 LSB. Since IN L = 0 LSB
was for the interval from ”100” to ”101”, the INL from ”101” to ”110” is
IN L = +1 LSB.
The negative step at ”011” is an example of a non-monotonicity. At this
point, an increase of the input IN results in a decrease of the output volt-
age Vout . In general from the presence of a DN L < −1 LSB follows the
existence of a non-monotonicity. For DACs with a high number of bits the
implementation of an analogue to digital converter (ADC) gets increasingly
challenging [4, p.506].
Despite the mentioned static characteristics, DACs have dynamical ones.
The primary dynamic characteristic is the conversion speed. This is the
time it takes for the DAC to change the output Vout after the input IN has
changed.
In combination with a comparator, a DAC can implement a successive
approximation register (SAR) ADC [4, p. 559]. The structure is shown in
figure 2.7. The SAR logic adapts the output of the DAC, VDAC based on
the output of the comparator. If VDAC is adapted as close as possible to Vin ,
the current control value of the DAC CTRL is the digital representation of
the input voltage [4, p. 560]. This output is then passed to OUT.

Vin Vsample
VDAC

CTRL
DAC SAR logic OUT

Figure 2.7: Block diagram of a SAR ADC utilizing a DAC.

filling

13
 2 Basic Circuits

2.3 Maximum Power Point Tracking

For PV energy harvesting applications it is necessary to keep the PV cells in
their specific maximum power point (MPP). Doing this is called maximum
power point tracker (MPPT). This section investigates on different solu-
tions for this MPPT. First the need for MPPT, to achieve the main goal of
this thesis and to implement an energy harvesting ASIC for solar cells, is
explained in section 2.3.1. After this, different possible converter topologies
and MPPT techniques are introduced in sections 2.3.2 and 2.3.3.

2.3.1 Characteristics of PV Modules

Figure 2.8 shows a qualitative trace of a typical voltage to current (VI)

characteristic of a PV cell [42, 122][141, p.50]. The offset and scale of the
absolute values of the axes mainly depend on the irradiance and tempera-
ture. The blue trace shows the PV current IPV as a function of the module
voltage VPV . The green trace shows the resulting power PPV . PPV shows
a maximum of PMPP at a voltage of VMPP and a current of IMPP , which is
called the MPP [141]. At this operation point, the highest possible power
is harvested from the PV cell. Thus, it is desirable to operate the PV cell
as close as possible to this point to harvest the maximal power.

PMPP MPP

IMPP
PP V [W]
IP V [A]

VMPP
VP V [V]

Figure 2.8: VI characteristic of PV cell.

14
 2 Basic Circuits

The MPP depends on multiple different parameters. The biggest impact

on the maximum deliverable power has the irradiation to the PV cell. It
shifts the graph of IPV along the current axis linearly to the irradiation.
Thereby, the current IMPP strongly varies whereas VMPP keeps relatively
unchanged [66]. An converse impact has the cell junction temperature.
In contrast to the irradiation, the temperature mainly varies the voltage
VMPP and IMPP is not changed much [42].
Both the irradiation and the temperature dynamically change during the
energy harvesting [137]. The irradiation due to the day and night cycle
but also because of shading from mobile or immobile objects [113]. Here,
mobile objects like cars or flying birds passing by can cause rapid changes
in a timespan of ms [154]. The temperature mostly changes as a result
of the irradiation, which heats the PV cells up [137]. Since temperature
changes in general are relatively slow and the absolute temperature only
varies about ±20 %, the VMPP changes slower and less than IMPP . Due
to the varying available input power, it is required to continuously track
the MPP during operation which is called MPPT. However, the irradiation
can change much faster than the temperature, so it is more critical to keep
track to the irradiation, and thus fast changes of the cell current [137].

Other aspects of PV modules

To form PV modules with a technically suitable output voltage, several cells

are connected in series. Some more aspects determine the behaviour of PV
modules. The performance of a PV module depends on the mismatch of
the single PV cells, which it is composed of. The mismatch can be caused
by partial shading, dirt, ageing or manufacturing tolerances [81, 113]. Since
the cells are connected in series, all cells conduct the same module current.
Because of their different characteristics, they are operated at different
operating points resulting in a different individual MPP [141, pp.83 ff.].
The current through the module is then limited by the smallest PV current
of the cells of the module [141, p.86]. Thereby, the maximum power which
can be harvested is reduced. Another problem of this is the resulting reverse
voltage, which is applied to some of the cells. It can lead to hot spots and,
in case of thin film PV cells, to damages of the cell [26, 43].
To mitigate these losses, antiparallel bypass diodes are often implemented
to PV modules, as shown in figure 2.9a [141, p.83]. In many cases, more

15
 2 Basic Circuits

than one bypass diode is implemented per module, increasing the granular-
ity and to bypass smaller parts of the PV cells. The resulting VI character-
istic of two in series connected modules, where one only delivers about 25 %
of the other, is shown in figure 2.9b. In contrast to figure 2.8, PPV shows
two local maxima. A local MPPlocal is found at a high VPV , where the
current runs through both modules and is limited by the underperforming
one. The global MPP is located at a much lower VPV , where only one of the
modules is generating energy and the underperforming module is bypassed
by the diode. This will reduce the mismatch losses if only a small share
of the PV modules is underperforming. Additionally, the reverse voltage
stress can be reduced to a specified maximum value, at which the cells are
not damaged and no harmful hot spots occur [113]. The occurring local
maxima increase the required effort for the MPPT [123]. Alternatively, in-
stead of adding bypass diodes, active sub-string or module optimizers can
be added as discussed in section 2.3.2.

MPP

PP V [W]
IP V [A]

Bypass MPPlocal
Diode

VP V [V]
(a) Schematic (b) VI characteristic

Figure 2.9: PV module with bypass diode.

2.3.2 PV Energy Harvesting Topologies

After we have shown that a MPPT is necessary to maximize the harvested

energy, different topologies are investigated. In the past years, a huge
variety of different topologies for PV energy harvesting have been developed
and scientifically explored [55, 119]. They have different advantages and
disadvantages, which fulfil the demands of different applications.

16
 2 Basic Circuits

MPPT System

Figure 2.10 shows a general block diagram of a PV energy harvesting system

with a MPPT [90]. It features the PV power generator, which can be
composed of an arbitrary number of either PV cells or PV modules. This
PV power generator provides a current of IPV , at a voltage of VPV , to
a power converter. The power converter converts the input power at a
voltage of Vin to an output voltage Vout , which can be either alternating
current (AC) or direct current (DC). A MPPT monitors the state of the
PV power generator and controls the operation of the power converter to
maximize the energy, which is delivered at Vout . This control can e.g. be
implemented by a control voltage Vctrl . Other possibilities are the duty
cycle of a PWM signal, a control current or a digital signal [30].
The MPPT can monitor the PV power generator in multiple different ways.
Sensors can measure IPV , VPV , Iout , the irradiance or the temperature [18,
32]. These inputs can be combined to increase the performance. E.g. VPV
and IPV are combined in many cases to directly calculate the power, which
is to be maximized [31, 126]. The measurement of the inputs should depend
on the required tracking accuracy for the application.

Vin Power
Converter

VPV Vout Load

Vctrl
MPPT

Figure 2.10: General PV System with applied MPPT.

There are different selection criteria for the topology. In the end, the max-
imization of economical profit is the target of the final fund owner [70].
However, this is highly depending on the application, and thus not often
directly possible. Instead, there are different criteria, which hint at the
final profitability. For the selection of the topology, the cost, complexity,
efficiency, shading tolerance and flexibility of application are considered [5,
86, 118].

17
 2 Basic Circuits

String Inverter

The string inverter, depicted in figure 2.11, is the most commonly used
topology for PV systems, especially when not regarding large scale PV
power plants [51]. They feature a DC to AC (DC-AC) inverter, which is
directly connected to the modules and converts their output to the grid
voltage. The modules itself are connected in long series, providing a high
input voltage to the DC-AC converter. Due to the high input voltage and
power, these converters achieve very high peak efficiencies of up to 99.1 %
and European efficiencies of up to 98.8 % [2]. However, since the current
through all the modules connected in series is equal, they suffer from cell
mismatch and especially from partial shading. At the cost of more complex
MPPT the utilization of bypass diodes can partly mitigate this [77].

DC
Grid
AC

String
Inverter

Figure 2.11: String level MPPT topology [119].

Module level MPPT

To overcome the mismatch issues caused by a long series of PV modules,

the location of the MPPT can be shifted to the module level. For this, the
micro inverter topology, shown in figure 2.12, was developed [33, 65, 67].
In this concept, each module features a small DC-AC inverter, which is
parallelly applied to the grid. Thereby, each module is operated at its own
MPP, so the problems of shading mismatch between different modules can
be completely eliminated. Another advantage is the high flexibility of this
topology. Since the micro inverters are connected in parallel, it is easy to
add, remove or replace modules. However, due to the high ratio between

18
 2 Basic Circuits

the input voltage and the AC output voltage, they only achieve efficiencies
of 90 − 95 % [51]. The required safety control features for the direct grid
connection further increases the complexity of the converter and reduces
the benefit of this concept.

DC
DC
AC

Grid

DC
DC
AC

Micro
Inverter

Figure 2.12: Microinverter MPPT topology [119].

Another topology is the module power optimizer which is shown in fig-

ure 2.13 [21, 67, 81, 119]. In this topology, instead of a micro inverter, a
DC-DC converter is applied to every module performing the MPPT. The
converters of the modules itself keep being connected in series, reducing
the resistive losses. Thereby, every module is operated at its MPP, which
reduces the mismatch losses equally to the micro inverter topology. An
additional central DC-AC inverter connects the string to the grid and per-
forms the conversion to grid voltage. The sum of the output voltages is
spread to each module according to its individual harvested power main-
taining a constant current in the complete string. The DC-DC converters
can be implemented in different topologies as buck, boost, buck-boost or
else but in nearly all cases, buck or boost are superior to other topolo-
gies [67, 86, 142].
By cascading the DC-DC converters of the modules, a reasonably high
voltage is provided to the DC-AC inverter. Thereby, it can be realized
with a higher efficiency than normal string inverters. However, a MPPT
functionality is not required for the DC-AC inverter, reducing the effort
for the control. High efficiencies can be achieved for the DC-DC converters
since they do not need high conversion ranges [142]. This enables a high
system efficiency with a MPPT on module level.

19
 2 Basic Circuits

DC
DC

DC
Grid
AC

DC
DC

Module
Optimizer

Figure 2.13: Module power optimizer topology [119].

Submodule MPPT

The above section shows that applying DC-DC converters to each module
increases the energy yield. From this it is consistent to expand the con-
cept to the submodule level [86, 119]. This increases the granularity of
MPPT and therefore the mismatch tolerance. Moreover, the demands to
the technology are lowered because of the smaller voltages for each sub-
string compared to the module level. Figure 2.14 shows a topology with
DC-DC converters as a submodule optimizer. Unless only one converter
per module is depicted, each of the modules features multiple submodular
converters. The interconnection of the modules and the connection to the
grid is performed similar to the module level MPPT in the above section.

Different submodule optimizer concepts have been proposed in literature.

In the delta concept, additional DC-DC converters leverage the mismatch
between the substrings [8]. Since these DC-DC converters only transfer
the power difference between the substrings, they only need to handle a
share of the full power. However, this concept increases the wiring effort
and still requires a MPPT which can be implemented on module or string
level [8].
Another topology is the virtual parallel concept. Similar to the module op-
timizer, a main DC-DC converter is added to each module, which performs
the MPPT [89]. In addition to this, auxiliary DC-DC converters are added.

20
 2 Basic Circuits

Submodule
Optimizer

DC
DC

DC
Grid
AC

DC
DC

Figure 2.14: Submodule power optimizer topology [119].

They are able to transfer a current from the substrings to the output. By
the combination of full and partial power conversion, power converters with
1.75 times the rated power of all substrings together are required and by-
pass diodes are still necessary for heavy mismatch situations [118].
The last two presented topologies are the substring buck converter [86] and
the substring boost converter [119] concept, which are quite similar. Fig-
ure 2.15 shows a block diagram of both concepts. As for the other two
described concepts, the PV module is split into multiple submodules, in
this case Sub1-3. A DC-DC converter performing the MPPT is applied
to each of the submodules. The selection of this DC-DC converter distin-
guishes the two concepts, for the substring buck converter concept, a buck
converter is utilized, for the substring boost converter concept a boost con-
verter. The buck converter concept is able to operate at a relatively low
conversion ratio, if the mismatch between the substrings is small, resulting
in a potentially high conversion efficiency. For this, the string inverter needs
to adapt the string voltage depending on the available power, which needs
additional control effort [86]. Another advantage of the buck converter
concept is that it can handle any mismatch between the submodules, only
limited by the minimum and maximum duty cycle. However, this results
in a higher string current, increasing the resistive cable losses. Moreover,
due to the discontinuous current at the input of the buck converter during
the off phase, the input ripple is relatively large and has to be limited by
input buffer capacities.
When substring boost converters are implemented, the output voltage of
each DC-DC converter is higher than the input voltage. Thereby, the string
current is reduced, resulting in smaller resistive power losses. Another ad-

21
 2 Basic Circuits

PV Module

DC Vp
Sub1
DC

DC
Sub2
DC

DC
Sub3
DC Vm

Figure 2.15: Substring buck-/boost converter topology.

vantage of the increased module voltage is, that less modules in series are
necessary to achieve a required minimum string voltage, which the string
inverter needs to efficiently transfer the harvested energy to the grid. The
mismatch capability of this concept is limited to PPmaxmin
= VVmax
min
. This is,
because the output voltage of each buck converter is always greater than
or equal to the input voltage, and the string current has to be equal for
all DC-DC converters. However, this drawback can be overcome when the
boost converters have a sufficient output voltage range to cover all nec-
essary mismatch scenarios, where a significant amount of energy would
otherwise be lost. If the mismatch exceeds the tolerable limit, the sub-
module will be bypassed by switching on both power switches of the boost
converter [118]. Another advantage of this concept is, that by the usage of a
boost converter, the inductor current is continuously drawn from the input.
Thereby, the current ripple in the PV cells is greatly reduced, resulting in
a better MPPT.

22
 2 Basic Circuits

2.3.3 MPPT techniques

After expanding on the PV system topology, this section is looking deeper

into existing MPPT techniques. In literature, a vast variety of different
techniques is discussed [31, 126]. Some techniques are used widely and es-
pecially the perturb and observe (P&O) algorithms are extensively used in
commercial systems [126]. This chapter shows some commonly used MPPT
techniques in section 2.3.4. Before this, general optimization and selection
criteria for MPPT techniques in 2.3.3 and the possible measurement and
steering options in 2.3.3 are shown.

Selection and Optimization Criteria

For the selection of a MPPT concept and algorithm, there are different
criteria which have to be taken into account. A major criteria is the tracking
efficiency
PPV
ηmppt = (2.4)
PMPP
which is often valued in % [141, p.112]. For fluctuating irradiance or when
the current and voltage ripple of the DC-DC converter are taken into ac-
count, the instantaneous tracking efficiency has to be averaged for a specific
amount of time to determine ηmppt = avg(ηmppt ). The MPPT tracking
speed fmppt is another important criterion [120]. It indicates how often the
operating point is updated by the MPPT. Even if this does not directly
correspond to the capability to track dynamic changes of the MPP, it is
a good indicator for this [120]. The implementation complexity should be
kept low to avoid unexpected behaviour of the MPPT [128]. In addition
to this, the complexity correlates to the average power consumption of the
MPPT concept, which is desired to be as low as possible. However, a trade
off to the tracking efficiency is necessary, because more complex or energy
hungry implementations allow for a higher tracking efficiency. Especially
for larger sized PV systems this can justify additional MPPT complexity.
The weight of the different criteria is highly depending on the application.
Similarly to the topology consideration, the cost efficiency is of major inter-
est for the end user, different trade-offs are necessary for different applica-
tions. The expected irradiance characteristics, and therefore the occurring
static and dynamic shading, have a high impact on the design of the MPPT

23
 2 Basic Circuits

concept [128, 154]. Another criteria is the general MPPT performance in

respect to tracking efficiency and speed [92, 128]. Another influence is the
characteristics of the PV modules. Especially the existence of bypass diodes
requires an additional global MPPT to find the real MPP [128]. Finally,
the overall controlled power is of importance too. This is because in a sys-
tem, where the MPPT controls a high amount of power, the benefit of the
more accurate MPPT, of a more complex and energy hungry MPPT, can
exceed the cost of the additional power.

Measurements and Steering

To operate the PV system in its MPP, the MPPT has to be able to monitor
and affect the PV operating point. In the following, different options for
these tasks are introduced.

Measurement Options There are multiple possibilities on which param-

eters the MPPT can be based, and which need to be measured. Since the
objective of the MPPT is to maximize the harvested power, the measured
values should be an indicator for the power of the PV module [17]. An
obvious option is to directly determine the power by measuring VPV and
IPV and multiplying these values. This can be done analogously or, when
both values are digitized, digitally [12, 120]. Another possibility is to either
monitor the current or the voltage for an estimation of the MPPT, often
utilizing a pilot cell [41]. However, it is possible to determine the MPP
without an absolute measurement of any of the values. Instead, the rela-
tive or dynamic behaviour of VPV and IPV can be utilized to determine
the MPP [126, 154]. Beside VPV and IPV , the measurement of Isc , Voc ,
Iout , Vout , the irradiance or even the temperature can be used to track the
MPP [126].

Steering Options The MPPT needs a possibility to steer the power con-
verter to a desired input operating point [17]. Therefore, communication
between the MPPT and the power converter, in most cases a switched
DC-DC converter, is necessary, as illustrated in figure 2.16. For this com-
munication interface there are many different options. PWM signals are
widely used for MPPT systems with DC-DC converters [72, 85, 128, 154].
Thereby, the duty cycle of the DC-DC converter is directly controlled by

24
 2 Basic Circuits

the MPPT, which generally requires control loop stabilization. If the DC-
DC converter features an integrated control, other signals can be used for
the steering. Therefore, voltage, current and digitally controlled DC-DC
converters exist [17, 49, 118, 128].

Power
MPPT
Voltage Converter
Current
PWM
Digital

Figure 2.16: Communication options.

2.3.4 Presentation of different MPPT techniques

Research has proposed a vast amount of different MPPT techniques, which

highly differ in accuracy, speed, complexity and flexibility. However, some
techniques are found to be used more often than others. To select a tech-
nique for the implementation of an energy harvesting integrated circuit
(IC), a selection of different MPPT techniques is shown in the following
starting with very simple ones. After this, the most commonly used tech-
niques are presented [128]. Very complex MPPT techniques like intelligent
fuzzy logic or artificial neural network based MPPTs, Gauss-Newton or evo-
lutional MPPTs are not considered because the aimed power per MPPT is
too low to justify the high additional effort [126, 128].

Indirect MPPT Indirect MPPT strategies use known parameters, like the
VI characteristic of the PV modules for the tracking. Two such techniques
are the fractional short-circuit current (FSCI) and the fractional open-
circuit voltage (FOCV) technique [31, 126]. Both techniques utilize the
approximately linear correlation of one of the base values of the PV cell
with its MPP. For FSCI, the short-circuit current Isc of the module is
determined. From the VI characteristic of the PV cell follows

IMPP ≈ Ksc · Isc (2.5)

with a constant, dependent factor Ksc . Similarly, the FOCV technique

utilizes the open-circuit voltage Voc to estimate the MPP. Therefore, the

25
 2 Basic Circuits

relation

VMPP ≈ Koc · Voc (2.6)

with a constant but cell dependent factor Koc is used, which again follows
from the VI characteristic. The measurement of Isc or Voc can be done
by periodically sampling of the complete module. Alternatively, pilot cells
can be utilized reducing the tracking loss due to the measurement and
increasing the tracking speed [41, 107].
The two shown indirect MPPT techniques offer a low tracking performance
at very low cost and complexity. The resulting tracking speed can be
relatively high since the measured values can be constantly monitored and
directly applied to the PV cells. However, they are very inflexible since
Ksc or Koc have to be redetermined for every application.

Hill Climbing / P&O MPPT

For hill climbing and perturb and observe (P&O) techniques, the operation
point of the PV module is changed by a perturbation in constant cycles and
the resulting power is measured and evaluated to approach the system to
the MPP. They only distinguish in the parameter, which is perturbed, the
duty cycle of the DC-DC converter for hill climbing and the input current
or voltage for perturb and observe (P&O) [31, 128]. On behalf of this,
they show equal behaviour and envision the same fundamental method.
Therefore, they are mostly regarded as the same technique [31, 126]
Figure 2.17 shows a flow chart of a basic P&O algorithm [128]. The ab-
solute value of the perturbation ∆ is either constant and selected during
the development or dynamically adjusted [122]. The algorithm periodically
measures VPV (k) and IPV (k) to determine PPV (k) = VPV (k)·IPV (k). This
power is compared to the stored power of the last measurement PPV (k −1).
If the comparison

PPV (k) > PPV (k − 1) (2.7)

is true, the perturbation ∆ of the last cycle was in direction of the MPP,
and thus in the desired direction. In this case, the perturbation ∆ can be

26
 2 Basic Circuits

added to determine the next control input

x(k + 1) = x(k) + ∆ (2.8)

of the DC-DC converter. If the condition is false and PPV (k) < PPV (k−1),
the perturbation went into the wrong direction. Thus, the direction needs
to be changed first, which is done by the inversion of ∆. Subsequently, x is
perturbed as in the other case. After the perturbation the algorithm waits
for a time span Tp to give the system time to settle to the new operation
point before the routine starts over again.

start

sense Vpv(k)
and Ipv(k)

determine
wait Tp
Ppv(k)

no
Ppv(k) > Ppv(k-1)

inverse
direction yes
Δ=-Δ

x(k+1)=x(k)+Δ

Figure 2.17: Flow chart for the standard P&O technique.

This tracking technique is considered conventional and widely used in com-

mercial products [128]. It achieves a good tracking performance at rela-
tively low complexity. However, the technique faces multiple limitations.
Due to the constantly applied perturbation, the operation point is fluctu-
ating around the MPP in steady state. This fluctuation, even at ideal mea-
surement conditions, can exceed the two possible operating points which
neighbour the MPP [128]. Moreover, the basic algorithm can track ei-
ther accurately or at a high tracking speed. Thus, a trade-off has to be
done between these aims. Another limitation is the erratic behaviour when
the irradiance changes too fast for the MPPT to keep track [128]. This
can especially impact the tracking efficiency when the irradiance changes
ramp-wise.

27
 2 Basic Circuits

To overcome these limitations, algorithms with an adaptive step size ∆ and

sampling period Tp have been developed [120, 122]. Here, the step size is
de- or increased based on the tracking history of the MPPT. To adapt to
the sampling period, the steady state of the DC-DC converter is detected
and knowledge on the transient response of the DC-DC converter is used.
However, this comes at the cost of increased complexity and higher sam-
pling rates of the ADC, which is required for the digital implementation.

Incremental Conductance

The InCond technique is in principle equivalent to the P&O technique [112].

However, since it solves the tracking problem from a different perspective,
it is often considered as a separate technique. It utilizes the characteristic
of the power curve of the PV cell that its slope is zero at the MPP, positive
at the left and negative at the right of the MPP [31, 47]. This condition
is
⎧
dPPV ⎨ = 0 at the MPP
> 0 left of the MPP (2.9)
dVPV
< 0 right of the MPP
⎩

expressed as a formula. To evaluate this condition, for the InCond tech-

nique, equation 2.9 is extended to

dPPV d(VPV · IPV )

= (2.10)
dVPV dVPV
dIPV
= IPV + VPV · (2.11)
dVPV
which is done using PPV = VPV · IPV . For the condition for the MPP,
dPPV
dVPV = 0 follows

IPV dIPV
=− (2.12)
VPV dVPV
as another criteria for the MPP. This can be interpreted as

G = −dG (2.13)

28
 2 Basic Circuits

with the large-signal conductance G = VIPVPV

and the small-signal conduc-
dIPV
tance dG = dV PV
. This condition that in the MPP the conductance equals
the incremental conductance is the basic condition of the InCond technique.
In combination with 2.9 and VPV > 0 follows
⎧
⎨ = 0 at the MPP
G + dG > 0 left of the MPP (2.14)
< 0 right of the MPP
⎩

which is evaluated in the InCond algorithm to find the MPP [128].

Figure 2.18 shows the flow chart of a basic InCond algorithm [128]. The
MPPT is able to control the DC-DC converter to set the input voltage to
VPV . After the start, first VPV (k) and IPV (k) are measured. From these
and the stored value from the last measurement, dVPV (k) and dIPV (k) are
calculated and G(k) + dG(k) is determined. If the result is positive, the
current perturbation ∆VPV points into the correct direction and the MPPT
approaches the MPP. Thus, VPV (k+1) = VPV (k)+∆VPV is the next value
for the DC-DC converter control. If the result of the comparison is negative,
the MPPT inverses the perturbation direction ∆VPV = −∆VPV before the
perturbation step is applied. After the perturbation is applied, the MPPT
waits for Tp until the system settles before the algorithm starts over again.

start

sense Vpv(k)
and Ipv(k)

determine
dVpv(k),dIpv(k), wait Tp
G(k)+dG(k)

no
G(k)+dG(k) > 0

inverse
direction yes
ΔVpv=-ΔVpv

Vpv(k+1)=Vpv(k)+ΔVpv

Figure 2.18: Flow chart for the basic InCond technique.

29
 2 Basic Circuits

There are implementations, which add a condition that keeps VPV constant
when G(k)+dG(k) = 0 [47]. This can avoid the fluctuation of the operating
point around the MPP and can increase the tracking efficiency. However,
this only is valid if the influences, due to noise and quantization errors,
are negligible and the environmental conditions are constant, which is not
the case for a practical realization [28, 128]. Instead, the shown flow chart
changes the direction of the perturbation when G(k) + dG(k) = 0, whereby
a constant perturbation is applied to VPV . Thus, similar trade-offs as for
the P&O technique exist.

Ripple Correlation Control

A MPPT technique, which provides fast MPP convergence, is the RCC [31,
58]. This technique does not impose an artificial perturbation to VPV .
Instead it utilizes the inherent input ripple of the DC-DC converter. From
the VI characteristics of PV cells follow the two similar criteria
⎧
dPPV dVPV ⎨ = 0 at the MPP
· > 0 for VPV < VMPP (2.15)
dt dt
< 0 for VPV > VMPP
⎩

and (2.16)
⎧
dPPV dIPV ⎨ = 0 at the MPP
− · > 0 for VPV < VMPP (2.17)
dt dt
< 0 for VPV > VMPP
⎩

with the correlations of PPV to VPV and IPV [73]. The time integral [62]
of these signals can directly be used to control a DC-DC converter [73].
With PPV = VPV · IPV follows
(︃ )︃
dPPV dVPV dIPV dVPV dVPV
· = VPV + IPV · (2.18)
dt dt dt dt dt

and
(︃ )︃
dPPV dIPV dIPV dVPV dIPV
− · = − VPV + IPV · (2.19)
dt dt dt dt dt

which can be evaluated by a circuit. Alternatively, the small signal values

of VPV and IPV , vPV and iPV which can be generated by high-pass filters,

30
 2 Basic Circuits

can be used giving

pPV · vPV = (VPV iPV + IPV vPV ) · vPV (2.20)

which can be evaluated equally to equation 2.15 as shown in [73]. Fig-

ure 2.19 shows the block diagram of such an RCC MPPT implementa-
tion [73]. It combines both criteria 2.15 to increase the input signal and to
operate stable in both saturation regions of the PV cells. The combination
of equations 2.18 and 2.19 is completely rebuild with analogue circuits.

Vin
DCDC

R1
Vout
d
VPV dt
R2
∫
-1 d
dt
Rshunt

Figure 2.19: Schematic illustrating the principle of the RCC technique.

The technique shows a good transient performance with very high tracking
speeds. However, this comes at the cost of big and energy demanding
analogue multipliers. In addition to this, the used components have to be
able to handle the instantaneous values of VPV and IPV , which requires
frequencies above the converter switching speed. Thus, this technique is
challenging for DC-DC converters with high switching frequencies.
Another implementation, based on RCC, is shown in figure 2.20 [6, 7]. It
avoids the analogue multiplications by utilizing analogue preprocessing and
an XOR gate, which performs a multiplication of the signs of the derivatives
of pPV and vPV .
R1 and R2 set the voltage

Vmeas,V = αVPV (2.21)

31
 2 Basic Circuits

Vin
DCDC

Vout

VPV
correlation

-Vmeas,I d Vcorr SGN

dt RES
∫
d SGN
dt
Vin
Rvar R1

-1 Vmeas,V

R2

preprocessing

Figure 2.20: Modified MPPT based on RCC [6].

R2
with α = R1 +R2 . The analogue preprocessing adjusts Rvar in a way that

−Vmeas,I = Vmeas,V (2.22)

and thus
VPV
Rvar = α · (2.23)
IPV
which, due to the low-pass filter, can be considered constant for the corre-
lation. Since Rvar is in the direct path of IPV , Vmeas,I is selected as small
as possible to reduce the resistive losses at Rvar . Thus,

VPV ≈ Vin (2.24)

can be used in the following. The correlation processes

Vmeas,I = Rvar · IPV (2.25)

and Vmeas,V . The high-pass filters of the OP decouple the input signals
from the DC values and enforce that Rvar ≈ const. can be used. The

32
 2 Basic Circuits

derivative [63, 78] of the output of the OP is

d
Vcorr = (Vmeas,V + Vmeas,I ) (2.26)
dt
d
= (α · VPV + α · IPV · Rvar ) (2.27)
dt (︃ )︃
dVPV VPV dIPV
=α· + · (2.28)
dt IPV dt

of which the sign is determined giving

(︃ (︃ )︃)︃
dVPV VPV dIPV
sign (Vcorr ) = sign α · + · (2.29)
dt IPV dt
(︃ )︃
dVPV VPV dIPV
= sign (α) · sign + · (2.30)
dt IPV dt
dVPV
sign IPV · dt + VPV · dIdtPV
(︁ )︁
= sign (α) · . (2.31)
sign (IPV )

For all relevant operation points

VPV > 0 V (2.32)

IPV > 0 A (2.33)
and α>0 (2.34)

is true, which can be used to simplify equation 2.31 to

(︃ )︃
dVPV dIPV
sign (Vcorr ) = sign IPV · + VPV · . (2.35)
dt dt

The XOR gate performs a one bit multiplication giving

(︃ )︃ (︃ )︃
dVPV dIPV dVPV
RES = sign IPV · + VPV · · sign (2.36)
dt dt dt
(︃(︃ )︃ )︃
dVPV dIPV dVPV
= sign IPV · + VPV · · (2.37)
dt dt dt

which directly corresponds to equation 2.18. Since based on equation 2.18,

only the sign is used for the MPPT, the time integral of RES can be used
to control a DC-DC converter as shown in figure 2.20.

33
 2 Basic Circuits

With a slight modification, this MPPT technique can be extended by an ar-

tificial introduced perturbation. In this case, RES is sampled synchronously
to the DC-DC converter switching. This is necessary since the wanted in-
put signal is no more the inherent ripple at the PV cell. By the artificial
perturbation, the demands on the analogue preprocessing can be reduced
since the required bandwidth corresponds to the frequency of the pertur-
bation and not the switching frequency of the DC-DC converter. Another
dV
advantage of this adaption is, that the sign of dVdtPV , and thus meas,V
dt is
known so the correlation is further simplified.

34
 Chapter 3
Power Management Unit

The trend towards increasingly complex and smart integrated power elec-
tronics is accompanied by an increasing complexity of on-chip power supply.
In order to control the effort of external power management, an increasing
part of it is integrated on the chip. Therefore an ASIC, in most cases,
requires a power management unit (PMU), which provides the necessary
voltages to the chip [44]. This chapter approaches the integrated PMU,
designed for an integrated gate driver IC which is introduced in the fol-
lowing. Therefore, the general requirements and constraints of a PMU
and especially the start-up and undervoltage lockout (UVLO) of the cir-
cuit are elaborated on in section 3.1. After this, a concept for the PMU
is selected in section 3.2. This concept is implemented in a 180 nm high
voltage BCD technology. The following sections detail on the implemented
circuits of LDOs (3.3), the DC-DC converter (3.4) and the start-up control
(3.5). Measurement results of the implementation are given in section 3.6
and finally, further improvements are shown in section 3.7.
The PMU is developed for an integrated smart gate driver IC for insulated-
gate bipolar transistors (IGBTs) and power MOSFETs. Gate drivers are
used to switch power switches e.g. in electronic vehicles where they are

35
 3 Power Management Unit

a main topic of research [116]. They enable an increase of the switch-

ing efficiency, the reduction of EMI and can provide additional safety fea-
tures [110]. The therefore required precise control of the gate current and
monitoring of other parameters is then the purpose of the integrated gate
drivers.
Figure 3.1 shows the block diagram of the integrated smart IGBT gate
driver [102]. It features a gate shaping output stage with adjustable tim-
ing [110], miller clamping [27], a short circuit detection [27] and a gate mon-
itoring functionality. The programmed and synthesized digital control logic
receives the timing parameters for the switching event of the MOSFET via
an serial peripheral interface (SPI) interface. Based on these parameters, it
sets the edge control and the output stage. The edge control generates ac-
curately timed control signals for the output stage, which then adjusts the
driving strength as specified, during the switching of the MOSFET. How-
ever, the gate driver IC requires the different supply voltages V10V = 10 V,
V5V = 5 V and V1.8V = 1.8 V for operation. These are provided by the PMU
out of the externally connected stable V15V = 15 V. V5V supplies the low
side preamplifiers in the output stage as well as the integrated bandgap ref-
erence (BG). V1.8V supplies the digital control logic and auxiliary analogue
on-chip circuitry. V15V , V5V and V1.8V are buffered by external capacities
in order to reduce the voltage ripple caused by the synchronous digital
part and the switching of the output stage which, by principle, produce
strongly pulsed loads currents. Finally the bandgap reference, in addition
to a common 1.2 V reference [152], provides the high side reference voltage
V10V which is required as a current sink for the switching of the high side
preamplifiers of the output stage and is not buffered externally [102]. The
transistors available for this are able to switch 5 V and, thus, V10V is ref-
erenced to V15V resulting in the requirement of V10V = V15V − 5 V = 10 V.

Figure 3.2 shows the output stage. Two pre drivers amplify and level shift
the digital signals ENPMOS and ENNMOS to Vctrl,PMOS and Vctrl,NMOS .
These voltages control the gates of the power MOSFETs M1 and M2 which
switch Vout . This leads to the switching signals shown in figure 3.3.
For the design of the PMU it is of great importance to know the require-
ments and behaviour of the loads. Since the switching events are the
main events of the gate driver IC, most load characteristics can be de-
rived from these. The switching frequency of the external power switch is
fsw = 100 kHz or less and the effective capacitance is Cload ≈ 70 nF. Since

36
 3 Power Management Unit

V15V gate driver IC

V10V
V5V
Aux
PMU
Output
stage
BG
V1.8V

Edge
Digital Control
IC Control Switch
SPI Monitoring

Figure 3.1: Block diagram of the complete gate driver IC.

V15V
V15V
Vctrl,PMOS
ENPMOS M2
V10V Vout
V5V
Vctrl,NMOS
ENNMOS M1

Figure 3.2: Output stage of the gate driver IC.

37
 3 Power Management Unit

Vout is supplied out of V15V ,

Qsw,out ≈ Cload · V15V = 1.05 µC (3.1)

is the approximate charge per cycle. Consequently the required average

current of V15V is

I15 V ≈ Qsw,out · fsw = 105 mA (3.2)

neglecting the additional currents from the miller plateau [79]. In fact,
this will increase the average current significantly. Since V15V is supplied
externally to the chip, the current is not directly relevant for the PMU.
Nevertheless, this current is drawn highly pulsed which will cause strong
switching noise which should be considered during the design of all circuits.

15
Vctrl,pmos
Voltage [V]

10
Vctrl,nmos
5

Vout
0

Time
Figure 3.3: Graph of a switching event.

The current consumption of V10V is dominated by the switching of M2

from figure 3.2. Simulations show a demand for charge of Qsw ,M2 = 7.1 nC
′
for each switching cycle which would lead to I10 V ≈ 0.71 mA. However,
because of the high side driver structure of the p channel MOSFET (PMOS)
output stage which is shown in figure 3.4, this current is not pushed into
V10V . Instead, the gate of the output transistor is discharged by a PMOS
transistor connected as source follower and thereby conducting the charge
directly to GND. Thus, V10V only needs to take up the current from the
pre drivers which leads to a charge of Qsw ,pmos = 280 pC per switching

38
 3 Power Management Unit

cycle. This leads to

I10 V ≈ Qsw ,pmos · fsw = 28 µA (3.3)

for the approximate average current in V10V . The demand for charge out of
V5V for each switching cycle is Qsw ,nmos = 6.9 nC and the average current
consumption

I5 V ≈ Qsw ,nmos · fsw = 0.69 mA (3.4)

follows equivalently whereby here, the current is drawn directly out of V5V .

V15V V15V
Vctrl,PMOS,pre
ENPMOS
Vctrl,PMOS
M2
V10V
Vout

Figure 3.4: High side driver of the PMOS output stage from figure 3.2.

The current consumption of V1.8V does not directly depend on fsw . Instead
the current consumption of the digital part dominates which has a switching
frequency of fsw ,dig = 100 MHz. Here it is not possible to directly derive the
required average current. From former projects at IAS, a rough estimation
of the current consumption based on the clock frequency and the digital
complexity leads to I1.8 V ≈ 10 − 20 mA.
To obtain a safety margin, the values from table 3.1 are chosen for the
design of the PMU. Since the currents of all supply voltages are highly
pulsed, external capacities are required to stabilize the supply voltages
to avoid excessive noise on all supplies. Nevertheless the remaining high
frequency noise has to be considered during circuit design. However, it
must be considered that V10V only sinks current from M2 and does not
need to provide an outgoing current to any of its loads. Moreover, it is
used exclusively by CMOS drivers so a lot of noise is acceptable at this
supply. In addition to this, [152] shows a technique for a low impedance on
chip reference voltage and thus, an external capacitance is not required.

39
 3 Power Management Unit

Supply Average charge Special requirements

voltage current per pulse
V15V 250 mA ≈ 2.5 µC externally supplied to IC
highly pulsed load
V10V 50 µA ≈ 280 pC used as current sink
highly pulsed load
V5V 1.0 mA ≈ 7.1 nC highly pulsed load
V1.8V 25 mA ≈ 100 pC highly pulsed load

Table 3.1: Requirements and behaviour of the different supply voltages.

3.1 Undervoltage Lockout Basics

During operation electrical circuits pass through several operation modes.
Even if designed to operate at low supply voltages, electrical circuits need
a certain minimum input voltage to operate correctly [115]. If this volt-
age is not available, undefined behaviour can occur because of e.g. wrong
reference generation, malfunctions in logical circuits or power transistors
switched on and off wrong or only partially [13, 115]. If the circuitry is
not damaged and the undefined output cannot cause harm to anything,
undefined behaviour might be acceptable in some cases. However, to avoid
undefined behaviour when this voltage is not available, an UVLO function
is necessary [50, 115].
Figure 3.5 illustrates the different operating modes which occur during the
start-up and shut-down of an ASIC. During the start-up, the ASIC is in
an off operation below a minimum voltage of Vf +,min , which has to be
ensured by the UVLO. Above this voltage, it is undefined whether the
ASIC is already functional or still switched off up to Vf +,max . Between
this voltage and Vp,min , the ASIC is functional but not yet running at full
performance. This is achieved at voltages above Vp,min . Voltage drops
can occur during operation, whereby the likeliness is depending on the
application. In case that the functionality can not be continued during
these drops, the UVLO has to switch the circuit back to an off operation.
When the chip is already running, the borders of functional and undefined
behaviour can shift downwards to Vf −,max and Vf −,min . This accounts for
the shut-down and voltage drops of the ASIC, if the supply already was
available.

40
 3 Power Management Unit

Vp,min

Vf +,max
Voltage

Vf −,max

performance

performance
Vf +,min

functional

functional
undefined
Vf −,min

undef.
drop
off off

Time
Figure 3.5: Operating modes of an ASIC.

An input voltage level violation can occur at different times during circuit
operation:
• when the circuit is switched off,
• at the start-up of the circuit,
• before the operation [98, 102],
• during regular operation in form of voltage drops [138] and
• at the end of operation when the circuit has to be shut down because
the input voltage is switched off or the voltage source is no longer
able to supply the load [140].
For many systems the rise of the input voltage during circuit start-up can
be considered to happen in a specified amount of time which is necessary to
charge applied capacitances. However the slope can show unexpected non
linear behaviour. In contrast to this, there are systems which by principle
do not have an external supply applied to the circuit in a proper way.
Instead their supplies have an undefined and potentially very slow slope like
e.g. solar power energy harvesters [9] or for battery powered devices [14,
140].

41
 3 Power Management Unit

3.1.1 Conditions and Requirements

The UVLO has to deal with uncertain conditions. Its main tasks are to
protect the other circuitry from damages and to put the PMU into position
to ensure a proper function if the supply conditions are sufficient. Therefore
the UVLO and the PMU interoperate closely with each other. The precise
conditions may differ for each application but in general some possible
uncertainties can be stated.
During start-up the input voltages can not be considered at a specified
level [98]. In many cases it might be acceptable to assume that the input
supplies are switched off and, thus, at 0 V [98]. However this may not be
true for other cases like energy harvesting systems. Following this, the
slope of the supply voltage is not generally defined. There might be guar-
anteed rise times but in energy harvesting applications, the transition to
the functional and performance region is potentially undefined. Another
uncertainty are the exact values of external components. Especially the
buffering capacitances can vary to provide flexibility to the user of the
ASIC. Additionally in a system comprising multiple supply voltages, the
order in which these voltages are generated, especially for externally pro-
vided voltages, is not always known. Finally there are no guaranteed stable
voltages to disable or enable circuits or to clamp nodes to a specific volt-
age which the UVLO could utilize [98]. This also means that there are no
reference voltages or bias currents available.
To achieve its main task, the UVLO is required to fulfil certain tasks. These
closely correspond to the voltage conditions of the ASIC. Firstly, the UVLO
has to ensure the starting of the ASIC in all occurring conditions which
strongly vary between applications. To protect the circuit from damages
it is necessary to avoid high cross currents and overvoltages e.g. in output
stages. These can easily occur if the controlling voltages are not clamped
to a safe level. Therefore the UVLO should provide a reference to other
circuitry, which allows to clamp voltages as early as possible. Parasitic
diodes between the internal wells can also impair the ASIC, if they get
forward biased. Then a parasitic substrate current may occur causing un-
wanted voltage rises, damages to the ASIC or even a latch-up [39]. Thus it
is necessary to control the order in which these voltages are provided to or
generated on the ASIC or to make it tolerant to this. On-chip generated
voltages can therefore be coordinated by the UVLO to reduce the risk of
failure.

42
 3 Power Management Unit

Finally an issue appears if the supplies have to provide high currents during
the start-up. If the supplies are not able to provide this current, these load
currents can throttle the supply voltage at a wrong level. These can occur,
when the main circuitry gets active and internal capacitances are charged
or high cross currents e.g. in CMOS inverters occur.

Circuits for the Start-up

Some simple circuits and techniques can frequently be used to set nodes to
a specific voltage when the ASIC is in off operation. To ensure a safe state
of the circuitry during the start-up, it will often be necessary to inhibit
the signal transmission to power switches. For this a NAND gate as shown
in figure 3.6 with one input at a RESET can be utilized. This ensures a
stable state of OUT at Vsup after Vsup exceeds Vth of the PMOS transistors.
Equivalently an AND signal can be used for this.

Vsup

RESET IN
OUT
RESET
IN
IN

RESET

Figure 3.6: NAND to inhibit signal transmission.

To reliably switch off a MOSFET during the start-up the clamp shown in
figure 3.7 can be used. The n channel MOSFET (NMOS) transistors are
switched on by RESET clamping Vg to GND. The AND gate prohibits a
high cross current by concurring signals of RESET and IN. After the start-
up Vg can be bound to IN by setting RESET to zero and switch RESET
to logical high. In this circuit, RESET does not need to be at digital high
but only at a sufficient voltage to switch on NMOS.
A RESET signal is generated by the circuit in figure 3.8. The current
through the resistor sets RESET to a voltage determined by the transistors
wired up as diodes. The voltage can be modified by the dimensioning of the
transistors and the number of diodes in series to ensure a sufficient level.

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 3 Power Management Unit

RESET Vg
IN
RESET
RESET

Figure 3.7: Inhibiting signal.

After the start-up it can be switched off by a RESET signal to enable a

regular operation.

Vsup

RESET

RESET

Figure 3.8: Generate a RESET signal at off state.

Another circuit of interest is the standard cross coupled level shifter [60].
During the start-up it is desired that it flips to a defined output state
before the differential input signal is available. This can be assured by an
asymmetric width to length dimensioning of the transistors as shown in
figure 3.9. The resulting asymmetric leakage current ensures that the level
shifter starts in a definite output state, even if the input voltages are not
available.
Vsup
1/6 1/1

OUT OUT

IN 6/1 1/1 IN

Figure 3.9: Level shifter that flips to desired state during start-up.

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 3 Power Management Unit

3.1.2 UVLO Concepts

After evaluating the conditions and requirements, which an UVLO has to

fulfil, different UVLO concepts are discussed. Depending on the conditions,
the circuitry is exposed to and the purpose of the ASIC, different concepts
are suitable. For prototypes that are operated in a laboratory, external
power sources in combination with a reset signal to disable different cir-
cuits can be applied to the ASIC. Thereby no extra power management is
necessary on ASIC, but the circuits must still be set to a stable and safe
operation which can be done utilizing the reset signal. However this is not
suitable for more complex systems and products where the ease of use is
relevant.
If the input supply is generated by a stable voltage source the UVLO only
needs to manage start-up and shut down of the circuit. In this case different
assumptions like a fully discharged ASIC at start-up or defined voltage
ramp up times, can be made. Here a self starting power management
without major voltage monitoring and blackout management can be used
for the start-up of the ASIC [98, 102]. Depending on the function, a special
shut down routine might be necessary.
A last class are systems with fluctuating input powers like in energy har-
vesting or battery powered systems [9]. These need a robust UVLO which
gets active before and independent from the main circuits. Ideally, this
UVLO only requires a very small amount of power so it can endure short
blackouts and get active sufficiently early. Depending on the application,
it has to monitor a different set of voltages and currents.

3.2 Selection of PMU Architecture

To develop an architecture for the PMU, a concept for the start-up und
UVLO has to be chosen first. Therefore it es necessary to determine the op-
erating conditions and requirements of the planned gate driver IC. Firstly
there is only the single external supply V15V which provides power to the
chip. Thus the PMU has to generate all other required supplies out of
V15V as previously mentioned in the beginning of this chapter. The cur-
rent requirements of V15V are not of interest for the PMU because it is
externally supplied to the ASIC. Consequently, the main supply the PMU
has to generate is V1.8V . Following table 3.1, it has to provide an average

45
 3 Power Management Unit

current of I1.8 V = 25 mA. Due to the high conversion ratio of VV1.8V

15V
= 8.33,
an implementation as LDO is not suitable because of the low resulting ef-
ficiency [132, p. 905]. Instead a DC-DC converter, in this case a buck
converter, is desirable for this supply.
At V5V an average current of I5 V = 1 mA is required. From a perspective
of efficiency, a DC-DC converter would be ideal too. However the cost for
this increase in form of additional pins and an external inductor would be
the same as for V1.8V , I5 V is only a 25th of I1.8 V , and the conversion ratio
is nearly a third. Thus the possible increase of efficiency is significantly
lower and an LDO is a good trade-off for the generation of V1.8V .
The current sink generating V10V only needs to be able to sink I10 V =
50 µA. Again this is not enough to justify the use of a DC-DC converter and
a resistive generation is the most reasonable choice. This can be supplied
directly by the bandgap reference in an elegant and efficient way [152].
Even if the full charge from M2 in figure 3.2 had to be drawn to V10V , this
trade-off would not change.
To increase the system efficiency, it is possible to sink the current not
directly to GND but instead conduct it to V5V . Since the biggest part of
the high side switching current is conducted as shown in figure 3.4, the
biggest effect can be achieved by discharging Vctrl,P M OS to V5V instead to
GND. Thereby the highest reduction at minimum effort is achieved.
Since the currents are drawn in strong pulses, additional external buffering
has to be applied. The pulses at V5V and V1.8V require charges of 7.1 nC
and 100 pC, which can not realistically be buffered by on chip capacities.
Therefore external capacities are required for these supplies. The pulses
at V10V draw charges of 280 pC which also cannot be buffered on chip.
But in contrast to the pulses of V1.8V , these pulses occur at a much lower
timescale of several ns and not hundreds of ps. This enables an on chip
implementation that avoids external capacities at the cost of increased volt-
age bouncing [152]. Since this supply is only used for the switching of the
high side drivers which are tolerant to such a voltage bouncing, no external
capacitance is required.

3.2.1 Selection of UVLO concept

The external voltage V15V is provided to the chip out of a stable supply
which rises from 0 V to 15 V in a time of tsu = 10 ms at start-up. Therefore,

46
 3 Power Management Unit

the UVLO only needs to manage the start-up and shut down. Because the
energy stored during operation is not high enough to damage the chip
during shut down, the focus of the UVLO is to manage the start-up as
discussed in section 3.1.1.
In this chip V5V and V1.8V closely operate together. To avoid forward
biased diodes between these voltages as mentioned in section 3.1.1 they are
successively generated. Since the diodes are blocking from V5V to V1.8V
which is necessary at regular operation, V5V needs to be generated first.
Thus it is necessary to enable this LDO to start-up autonomously.
To make use of the bandgap reference for the generation of V5V , it is nec-
essary that the bandgap reference starts operation jointly with V5V . This
can be achieved, in case that it is always active and supplied out of V5V .
Thereby it asynchronously starts when V5V rises and can provide a refer-
ence voltage to the LDO. To ensure a reliable operation, this requires a
close examination of the interoperability of these two circuits, and thus the
bandgap reference is considered part of the PMU. The generation of V10V
is not that critical and can be done independent of the other voltages. A
qualitative resulting voltage sequence is shown in figure 3.10.

V15 V

V10 V
Voltage

V5 V

V1.8 V

Time
Figure 3.10: Qualitative start-up voltage sequence.

To achieve a better efficiency, it is desirable to supply the buck converter

control out of V1.8V . Here a comparable performance of the control can
be achieved with considerably less energy. Because this is not possible
during the start-up, an auxiliary LDO for V1.8V is added. This LDO hands
over the voltage generation after the start-up. Thereby the need of a more
complex and potentially less robust control which is able to ramp up the

47
 3 Power Management Unit

voltage during the start-up is overcome too. The lower efficiency of an

LDO compared to a buck converter is no problem here since the chip is
not powered down regularly during operation, and thus the lower efficiency
during the start-up can be neglected.
The resulting block diagram of the PMU is shown in figure 3.11. It features
the LDO for V5V with start-up capabilities, the bandgap reference, the
auxiliary LDO for V1.8V and the buck converter. The control coordinates
the start-up by enabling the LDOs and manages the hand over from the
LDO to the buck converter.
V15V

SU
V5V
LDO
Vref Bandgap
V10V
Reference

LDO

CTRL
DC
V1.8V
DC

Figure 3.11: Block diagramm of the PMU architecture.

3.2.2 Bandgap reference

Since the bandgap reference closely interacts with the LDO for V5V , it is
briefly described here. The bandgap reference core providing a high side
V10V = Vsup − 5 V reference, developed in a former project [152] is ex-
tended to provide an additional 1.2 V low side reference. Figure 3.12 shows
the block diagram of the developed bandgap reference. A proportional to
absolute temperature (PTAT) core generates an internal reference current
which is proportional to the temperature [152]. This current is delivered
to three blocks:
• a high voltage complementary to absolute temperature (CTAT) load,
• a low voltage CTAT load and

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 3 Power Management Unit

• a start-up detection.
The output of the CTAT loads are buffered with different output buffers
providing the temperature stabilized V10V ≈ 10 V and Vref = 1.19 V.
A standard voltage to current (V to I) converter, comprising a current
source [132, p.774] and a current mirror [132, p.292], generates a tempera-
ture stable reference current Iref out of the low voltage reference Vref [35].
This reference current is then fed into a current mirror which provides the
required reference currents to the ASIC.

PTAT
core
LV CTAT Output Vref V to I Iref Current n
Iref,n
load buffer converter Mirror

HV CTAT Output
V10V
load buffer

Start-up
BGactive
detection

Figure 3.12: Block diagram of the bandgap reference.

Figure 3.13 shows a detailed schematic of the bandgap reference [4, p. 157
ff.]. The PTAT core is build of the bipolar junction transistors (BJTs) T1
and T2, whereby T1 is build of 8 instances of T2. The stacked current
mirrors M1 to M4 enforce the same current through T1 and T2. Thus
the difference between the base emitter voltages is applied to R1 , which
determines the current in both branches to
VT · ln 8
Ibranch = (3.5)
R1

with VT = kqe b ·T
which is directly proportional to the absolute tempera-
ture [93, p.390]. This current is mirrored by M5 and M7.
At M5 the PTAT current is fed into a CTAT load. M6 acts as a voltage
clamp to protect M5 from an overvoltage. The BJTs T3 to T6, together
with R4 form an CTAT load which delivers four times the standard bandgap
reference voltage [4]. In this case, however, this voltage is referenced to the
supply V15V resulting in V10V = V15V − 4 · 1.2 V = 10.2 V which is close
enough to the specified 10 V. T8 and T9 are the push-pull output stage for

49
 3 Power Management Unit

V10V [132, p. 869]. The BJTs are biased by diodes, whereby only T7 needs
to be added to the circuit. The push pull configuration of the output stage
ensures a strong and very fast driving capability [152].
At M7, the PTAT current is mirrored by M8 into M9, M10, M14 and M15.
M14 feeds the current into a CTAT load build of T10 and R3 . Since T3
to T6 are equally sized as T10, the resistor needs to be R3 = R44 . M15
supplies the buffering OP providing Vref at the output.

V15V
R4

T3

T4

T5
T8
T6
V10V
T7
T9
PTAT core V5V start-up detection LV CTAT load
M6
T1 T2 M8 M9 M10 M14 M15

R1
Vref,pre
M13 Vref
M1 M2
M11 BGactive T10
M5 M7

M3 M4 R2 M12 M14 R3

HV CTAT load

Figure 3.13: Schematic of the bandgap reference.

The described structure operates fully asynchronous to other circuitry. The

core starts to ramp up the PTAT current together with V5V following the
exponential slope of the BJTs and the sub threshold operation of the MOS-
FETs. This results in an immediate increase of Vref,pre which is relatively
steep at first and flattens afterwards due to the resistive part. The value of
Vref is thus limited by the performance of the output buffer which starts
operation between 1.2 V and 2.4 V depending on the process corner. When
the output buffer gets active, a first reference voltage and, at the same
time, a reference current are generated which both are not yet at the tar-
geted values. At a voltage between 1.35 V and 3.35 V, the exponential slope
fo the PTAT current leads to a further increase of Vref,pre and, since the
output buffer is already operating, Vref . At a sufficient supply voltage

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 3 Power Management Unit

between 3.0 V and 3.76 V the output voltage is at a level above 1.15 V,
where all circuits are functional. From that voltage it increases slowly up
to the targeted voltage 1.19 V. The BGactive signal rises between 2.0 V and
3.43 V. It is obvious that the signal does not indicate a correct bandgap
reference voltage. However the signal indicates that the reference current
is available and the reference voltage will continue with a steep slope. This
is because it is activated after Vref is rising due the exponential current
slope at the resistor. With this signal, the UVLO circuit is able to manage
the start-up.
For the UVLO it is necessary to know, whether the bandgap reference has
a minimum output voltage for the start-up management. If this is the case,
the UVLO knows that V5V is high enough for simple circuitry to operate
and to be biased by a reference current. Therefore the start-up detection
generates a signal, which indicates that the output voltage is at least partly
available. This is done by checking the PTAT current whether it is above
a specific level. Therefore the current is fed to R2 . If VR2 is high enough
to enable M12, the CMOS inverter consisting of M13, M14 toggles. This
sets BGactive to logical high. M11 is added to increase the required VR2 .
Simulations show that in the nominal case, BGactive gets logical high at
Vref = 550 mV and V5V = 2 V

3.3 Linear Voltage regulators

As described in section 3.2, the PMU comprises two different LDOs. It
would be possible as well to select another linear regulator topology since
the input and output voltages are far off each other, and a linear regulator
with a low dropout is not really essential [148] [132, p. 905]. However the
topology of an LDO is selected, because of it’s well known implementa-
tion.
Figure 3.14 shows the core of an integrated LDO [53, 74, 95]. The input
voltage Vin is applied to the series transistor M1, through which the re-
quired current flows to Vout . Cbuf is applied to buffer the Vout for current
demands, which are drawn too fast for the control loop to react. The out-
put voltage Vout is divided by the resistive voltage divider R1 and R2 . An
OP compares the divided voltage to a reference voltage Vref and controls
the gate of M1, whereby the current through M1 is adjusted to the required
value. Thereby the output voltage is controlled to Vout = Vref · (1 + R R2 ),
1

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 3 Power Management Unit

and thus the output voltage can be adjusted by the selection of R1 and R2
and is independent of Vin [132, p.898 ff.].

M1 Vout
Vin

Cbuf
R1

Vref

R2
LDO

Figure 3.14: Principle of an LDO.

For a high Vin , the OP needs a special output stage so the OP itself can
be implemented in low voltage MOSFETs, which allow for a higher perfor-
mance. Figure 3.15 shows a possible implementation. The OP controls the
gate of M3 and thereby adjusts Iadj . This current then flows through M2,
which is connected as a current mirror to M1, whereby M1 can be driven
very fast. To reduce the current loss, the mirroring ratio between M1 and
M2 is selected as high as possible.

M1 Vout
Vin

Cbuf
M2
Iadj
R1

M3 Vref

R2
LDO

Figure 3.15: Schematic of the core of the LDO.

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 3 Power Management Unit

3.3.1 Self Starting 5 V LDO

For the sequential start-up, the 5 V LDO needs to be able to start up

independently, if V15V is applied to the ASIC. Therefore an additional start-
up circuit extends the basic LDO from figure 3.14 as shown in figure 3.16.
The input voltage is the external supply V15V and the output voltage is
V5V . Via M4, the additional start-up current can be added to Iadj . R3
limits this additional current to a maximum of VR15V 3
but in practice Vgs,2
and Vds,4 reduce VR3 , and thus IR3 . This current is mirrored by M1
with a ratio of 201 and charges Cbuf . So R3 has to be selected in a way
that the resulting current is able to supply all circuits during the start-up.
Otherwise it is possible that the LDO deadlocks at a false voltage where
the circuitry draws up the whole start-up current.
The capacitive voltage divider determines Vg when V15V rises to Vg =
V15V · C1C+C1
2
and thereby activates M4. For a high robustness against
different rise times of V15V , it is important that the maximum gate source
voltage of M4 is not exceeded even if V15V is provided almost immediately.
Thus C1 and C2 are dimensioned in a way to set M4 to it’s maximum
gate source voltage when V15V reaches its target voltage. To be able to
switch off M4 once the additional start-up current is no more necessary,
M5 can discharge Vg controlled by Vso . This allows the LDO to start up
without a remaining direct current (DC) once the start-up is finished. An
uncontrolled current could lead to V5V exceeding its maximum permissible
voltage. However the maximum start-up time is limited due to leakage
currents which continuously discharge C1 and C2 . Therefore even if M5 is
designed for low leakage, the LDO needs a sufficiently steep slope of V15V
in the range of tens of ms.
During the start-up a handover between the uncontrolled start-up current
and the control loop of the LDO occurs. A challenge for this is the lack
of a stable reference voltage and current of the OP during the start-up as
shown in section 3.1. However the bandgap reference starts asynchronously
with the set up of V5V as described in section 3.2.2. Thereby, after V5V rise
to a voltage between 1.2 V and 2.4 V, depending on the corner, a reference
current and voltage are provided to the LDO. Even if the references are
not yet at their correct values at first, the OP starts operation and tries
to adjust the gate of M3 to rise V5V to the desired level, which brings the
references nearer to the targeted values. When M3 starts conducting a
significant amount of current, this results in a positive feedback such that

53
 3 Power Management Unit

V15V M1 V5V

Cbuf
start-up circuit
M2
C1 Iadj
R1

Vg R3

M3 Vref
Vso M5 M4
C2 R2
LDO

Figure 3.16: Schematic of the LDO with start-up circuitry.

V5V rises quickly. As shown in figure 3.17, for a fast start-up, and thus
small rise times of V15V , the initial delay of charging Cbuf delays the start
of the OP so V5V then directly rises to the targeted value. For a moderate
start-up, the LDO gets active before V15V is high enough to supple V5V at
its target voltage, so the positive feedback increases V5V until it is limited
by V15V and the minimum dropout voltage of M1. During a slow start-up,
the start-up current already is sufficient to bring V5V to V15V . Then the
slope of V15V limits V5V and the start of the control loop is not visible in the
slope of V5V . However, this poorly predictable behaviour does not impair
the function of the LDO to reliably start up if the start-up circuit is not
switched off too early and Vref does not show significant overshooting.

fast start-up

moderate start-up
Voltage

slow start-up

•
Time
Figure 3.17: Different start-up behaviour for different start-up times.

54
 3 Power Management Unit

Start-up detection

To achieve a correct performance of the LDO, it is critical that M4 is not

switched off too early or too late, especially because the start-up circuit can
not be switched on again due to the capacitive activation. Thus, the main
criteria is that the feedback loop has to be properly working. For this, a
start-up detection circuit is necessary ensuring a Vso signal which reliably
keeps low until the control loop is active. However, it is no problem if the
start-up circuit is active in parallel to the control loop as long as V5V is
below the final voltage.
There are two basic possibilities to detect whether the control loop is prop-
erly working, a direct and an indirect detection. For a direct detection the
state of the OP can be monitored. This can be done by checking whether
the gate of M3 is driven by the OP, which is the case when some reference
current is available and Vref is above the feedback voltage of the OP [98].
The drawback of this solution is that it is not reliable since the positive
feedback from Vref to V5V is not always given when the feedback loop is
first activated. Thereby, the start-up might be stopped prematurely caus-
ing failure to the complete ASIC.
An indirect start-up detection can be achieved by monitoring V5V . If the
OP is designed to be functional at a relatively low input voltage, its oper-
ation is limited by the references from the bandgap reference on which it
relies. The bandgap reference is active in all process corners at a voltage
above 2.4 V. So the range for switching off the start-up circuit is between
3.35 V and the target voltage of 5 V. Despite this absolute reference ap-
proach, it is sufficient when the start-up circuit is switched off after the
control loop of the LDO is in position to control V5V without a deadlock.
A monitoring that directly compares V5V to Vref is challenging because it
depends on the reference voltage provided by the bandgap reference. Since
this voltage is not available at the start-up, additional criteria are required
for this approach. To keep the circuit as simple as possible, an independent
voltage monitoring is implemented as detection circuit, which is shown in
figure 3.18. At start-up, M5 and M6 are switched off and Vg is capacitively
activated as described before. Thereby M7 conducts keeping Vd7 low and
M6 switched off. M8-10 do not conduct, where C3 ensures this for M9 and
M10. The detection whether V5V is high enough works on the principle
that M8 only starts to conduct when the voltage drop over R2 , VR2 , is high
enough. At this point, the current through M8 discharges C3 and flows

55
 3 Power Management Unit

through M9. This current is mirrored by M10 until it gets higher than the
current through M11 so Vso rises, which activates M5, discharging Vg , and
thereby deactivates the start-up circuit. M11 is designed as a current mirror
to the lowest diode transistor, so IM 11 is determined by the mirroring ratio.
Since this ratio is selected in a way that M11 only conduct a small portion
of the current this is roughly the case when VR2 = V5V − Vcmp ≳ Vth,M 8 .
M7 conducts during the complete start-up, so Vcmp is determined by the
transistors connected to form metal oxide semiconductor (MOS) diodes
where a combination of NMOS and PMOS diodes is used to reduce the
substrate effect. As long as V5V is too low to conduct a significant current
through the diode transistors, these are in weak inversion operation [68,
p. 27]. This current does not lead to a significant voltage drop across R2 ,
and thus Vcmp ≈ V5V . When V5V is high enough, the diode saturates and
starts to conduct a relevant current. This leads to a voltage drop across
R2 , and thus VR2 increases. At V5V ≈ Vdiode + Vth,M 8 , VR2 exceeds Vth,M 8
so M8 starts to conduct current which activates M5, and thus deactivates
the start-up circuit. This happens at a voltage between 1.9 V and 3.1 V,
depending on the process corner. Since this is not sufficient for the absolute
approach, many simulations were performed to prove a successful start-up
in interaction with the LDO. Further possible improvements of the start-up
detection are shown in section 3.7.
To switch off the start-up circuit once the start-up is done, a cross coupling
from Vg to the diode current branch is implemented via M6 and M7. M7
is switched off together with Vg . This causes Vd7 to increase, activating
M6, which further discharges Vg . It can occur that the discharging of Vg
is inhibited. This results from the cross coupling and M7. When Vg falls,
the drain source resistance of M7 increases and Vd7 rises, which reduces
VR2 . Thereby the current through M8, M9 and M10 is reduced and the
current through M11 is increased. This can lead to a throttling of the
start-up detection. However, since Vg is only charged capacitively, it can
not increase once V15V is at the targeted voltage. In addition to this, when
V5V rises, this will always lead to M6 conducting, which finally deactivates
the circuit. Thus, in normal operation of the LDO, neither the start-up
circuit nor the start-up detection draws any quiescent current and Vg is
clamped to ground by M6.

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 3 Power Management Unit

V5V

C3 M9 M10
V15V
R2
start-up circuit
R3
M8 C1
Vg
Vcmp M4
M5 M6 C2
diode Vso

M11

Vd7

M7

start-up detection

Figure 3.18: Schematic of the start-up detection circuitry.

3.3.2 Auxiliary 1.8 V LDO

The auxiliary LDO, which supplements the buck converter, requires no

special start-up circuitry. Therefore, the standard configuration from fig-
ure 3.15 is used. Figure 3.19 shows the schematic of the LDO. It com-
prises the previously described output stage build of M1 to M3. The OP,
consisting of M4 to M7 and the current reference, is build of a standard
differential stage which compares Vref to Vf p,LDO,1.8V , the output of the
feedback divider R1 and R2 [4, p.203]. To put the PMU control into po-
sition to coordinate the start-up of the supply voltages M8 to M10, which
can enable and disable the OP, are added to the circuit. As long as the
enabling signal EN is at low state, M9 inhibits a current through M2 and
M1. Additionally the OP is disabled by M8, which stops the bias current.
Finally M10 clamps Vg3 to a low voltage to set the OP to a defined state.

57
 3 Power Management Unit

M1 Vout
V15V V5V

Cbuf
M2
Iop
R1
EN M8

Vfb,LDO1.8V
M4 M5 Vref

Vg3
M3

EN R2 EN
M9 M10 M7 M6

Figure 3.19: Schematic of the auxiliary 1.8 V LDO with enable circuitry.

3.4 DCDC Buck Converter

The DC-DC buck converter is developed to supply the 1.8 V main supply
V1.8V with an expected maximum average current of 25 mA. The auxil-
iary LDO handles the start-up of V1.8V , so the buck converter can rely on
all supply voltages. Therefore it is possible to implement the converter
control with 1.8 V transistors which offer a better performance than their
5 V equivalents. The buck converter is enabled by a signal from the PMU
control.

3.4.1 PFM Control

The basic topology of a buck converter is introduced in section 2.1.1. Since

the targeted average current and voltage are relatively low the converter is
a low power converter [129]. For those a PFM control technique, resulting
in a DCM operation, is suited best to obtain a high efficiency [129]. In
contrast to a PWM control, in this mode the output is charged by defined
pulses, and the frequency in which these occur is modulated [106, 129, 151].
Despite a DCM results in output voltage ripple [30, p. 107 ff.], the higher
efficiency and ease of implementation outweigh this additional noise, which

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 3 Power Management Unit

is small compared to the heavy noise caused by the functionality of the

ASIC.
Figure 3.20 shows the implementation of the buck converter. It is imple-
mented as a voltage mode hysteresis control, because of the inherent sta-
bility and it’s area and energy efficient implementation [23, 24][118, p.34].
In general, the output is monitored with a comparator, which starts a con-
verter pulse coordinated by this control. This pulse pushes an amount
of charge to the capacitance Cbuf of V1.8V , increasing the voltage slightly
above the target voltage. After this the output is supplied out of Cbuf , and
the voltage decreases until the next pulse is triggered.
The comparator C1 starts the converter pulse by comparing the feedback
voltage Vf b,buck which is generated in the PMU control detailed in sec-
tion 3.5.2, to the reference voltage Vref . When Vf b,buck falls below Vref
the output of C1 gets high. This triggers the output of the SR flip-flop 1
ENHS , which enables the PMOS transistor M1 of the power stage charg-
ing the inductor L. In parallel, ENHS enables the comparator C2, which
is disabled in the meantime to reduce the current consumption via flip-
flop 2. Since the delay in this control chain is small, V1.8V quickly crosses
back above the trigger voltage of C1 so the output of C1 is reset to log-
ical low which in sum results in a short pulse of the comparator output.
M1 is switched of by the output of the delay of 100 ns, which triggers the
reset input of flip-flop 1 resetting ENHS . Since the current keeps flowing
in the inductor, the parasitic capacitance at Vsw , Csw , is discharged until
the parasitic bulk drain diode of M2 conducts. The second comparator C2
compares the switch pin voltage Vsw to GND during the falling edge of Vsw .
This comparator needs to withstand the complete voltage range of Vsw but
does not require a high accuracy since the input amplitude is sufficiently
high. It is described in detailed in section 3.4.2. If Vsw gets below GND,
the output of C2 gets logical high which triggers the SR flip-flop flip-flop
3 setting ENLS . Thereby, the low side transistor M2 is activated, which
redirects the current from the parasitic diode to the drain source channel
reducing the voltage drop, and thus the losses during this phase. At the
same time ENLS deactivates C2 to reduce the current consumption and
activates the third comparator C3, which determines the switch off of M2.
If C3 detects a voltage of Vsw very close to GND, it switches off M2, which
ends the DC-DC converter’s current pulse. The remaining charge is again
conducted through the parasitic diode of M2, and until the next pulse the
output is supplied out of Cbuf .

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 3 Power Management Unit

M1 VSW
V15V V1.8V
HS pulse L
Vfb,buck ENHS
S Q
Vref C1 FF 1 ENLS Driver
Delay M2 Cbuf
R Q
100ns
power stage
VSW
S Q
C2
FF 3
ENHS R Q
S Q
FF 2
R Q C3

LS pulse

Figure 3.20: Block diagram of the implemented buck converter.

Since the PMU control activates the converter after the V1.8V LDO gener-
ated V1.8V , it does not need a special start-up control routine. However,
the converter has to be set into a defined state before its operation, which
is done by an EN signal. For this the SR flip-flops have an additional
not depicted RESET input, which sets the outputs to a defined state of
logical low. Moreover, the input signals of the driver ENLS and ENHS ,
and the outputs of the comparators are inhibited by a clamp, as shown in
section 3.1.1, to ensure that M1 and M2 are switched off. To activate the
circuit, the EN signal only needs to be set to logical high. However, two
conditions must be fulfilled to enable a reliable operation. Firstly, V1.8V
must be available. It needs to be at a value higher than the trigger value of
C1, because only by this it is ensured that the control generates the defined
charge pulses. Secondly, V15V must be above 10 V. This is required by the
PMOS high side driver, which switches the gate of M1 between V15V and
V10V . Because of the charge reuse from V10V in V5V , there are parasitic
well diodes between V10V and V5V . So switching against V10V should be
avoided before it is above V5V . Since V10V is designed to be always 5 V
below V15V , this leads to a minimum supply of V15V > 10 V.
The control operates well during the light loads for which it is build. In
principle, the converter is able to supply a higher current demand at the
output than the targeted 25 mA. As long as the buck converter continues
in DCM operation mode, the control works properly. But if the demand
at the output gets too high, the charge pulse will not deliver the necessary
amount of charge to V1.8V . In this case, V1.8V is below the trigger voltage
of C1 causing an immediate following pulse. This output pulse of C1 is

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not necessarily reset quickly after the activation of M1 since V1.8V may be
significantly below the trigger voltage of C1. This leads to a situation where
both inputs of flip-flop 1 are at logical high. In this case, ENHS remains at
logical high, and thus M1 remains conducting, increasing the current in L,
until V1.8V is above the trigger voltage of C1 resetting its output. That way
the currents through M1, M2 and L exceed their specified values. Moreover,
the control can get unstable and show unpredictable transient behaviour.
Even if V1.8V was controlled relatively close to its target value, the voltage
would fluctuate and the ripple heightens.

3.4.2 High voltage Comparator

The high voltage comparator is developed to be used as C2 in figure 3.20.

It has to detect whether M1 is switched off and the current is running
through the parasitic diode of M2. For this, it compares Vsw with GND
and triggers the output when Vsw gets below GND. Since the comparator
is activated when Vsw is at V15V , the input has to withstand this voltage
without being damaged. Therefore, the input stage of figure 3.21 features
the two transistors M1 and M2, which have reversely directed parasitic
diodes. Moreover, M2 can withstand a high Vgd . The input stage checks,
whether Vds of M2 is high enough to conduct a current through R and the
output inverter M3, M4 is triggered switching OUT to logical high. M2
is operated with switched drain and source which results in a less good
performance. However, the performance is sufficient to detect whether
the current of the buck converter flows through the parasitic diode. Since
it is still possible for small negative voltages to occur in the circuit, all
transistors are build of 5 V transistors, although the supply is only at V1.8V .
To switch off the circuit, M5-M7 are inserted, which enforce a stable voltage
at all nodes and set OUT to logical low.

3.4.3 Improved charge reuse of current sink

To increase the system efficiency of the ASIC, the charge from the cur-
rent sink V10V could be reused in V1.8V . Therefore, the buck converter
could get an additional input as shown in figure 3.22. By adding M3, the
buck converter gets a multiple input multiple output (MISO) configuration
with two inputs and a single output. This extension enables a potential
increase of the system efficiency, when V10V sinks a significant amount of

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V1.8V

R EN M7 M3
M6 OUT

M1 EN M4
M5

M2
ENB
VSW

Figure 3.21: Schematic of the high voltage comparator C2.

charge and the ratio between the additional input and the output voltage
is high [100].
However, the preliminary tests of this concept only show a small effect of
this architecture. This is mainly caused by the small amount of charge of
a maximum of 1 mA which is conducted to V10V . Another reason is the
possibility to reuse the charge in V5V , where much less effort has to be made
to use 50 % of the energy. Moreover, the concept would only work if V10V
was buffered externally which should be avoided for this ASIC. Finally,
the complexity of the control will become much higher, if the multiple
input multiple output (MISO) concept is applied. Therefore, it is not
implemented in the ASIC.

M2 L
V15V V1.8V
VSW
M3
V10V
C1
Control and
V1.8V Gate Driver M1

Integrated DC-DC Converter Control

Figure 3.22: MISO principle for the buck converter [100].

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 3 Power Management Unit

3.5 PMU Control

The PMU control coordinates the interoperation of the different circuits
during start-up, and therefore undertakes the tasks of the UVLO. In addi-
tion to this, it provides the feedback voltages for the LDOs and the buck
converter, where an additional trimming of the output voltage is imple-
mented. As described in section 3.2.1, the UVLO only needs to manage
the start-up of the system. Therefore, the supply voltages are monitored by
a power good detection. A logic control activates the LDOs and the buck
converter depending on the monitored voltages. This logic operates across
the different voltage domains of V5V and V1.8V to enable an efficient con-
trol. Finally, some debug features are implemented, which allow a start-up
of the ASIC, even if the implemented control does not function properly.

3.5.1 Start-up Flowchart

The flowchart of the start-up routine is depicted in figure 3.23. It is devel-

oped to attain the voltage sequence of figure 3.10, and illustrates at which
conditions the LDOs and the buck converter are activated. The rising of
V15V activates the LDO, which generates V5V . At what time V5V is at the
targeted value is determined by the combination of a valid V5V and Vref .
This prevents a false positive detection by a wrong value of Vref . When
this determination becomes true, the control activates the LDO generating
V1.8V . The moment where the buck converter is activated is now deter-
mined by a combination of V1.8V and V15V monitoring. To start the buck
converter at a feasible state, V1.8V has to be at the targeted voltage. In
addition to this, the operation of the buck converter requires V15V > 10 V
as described in section 3.4.1. To obtain a safety margin, the limit is selected
to V15V > 12 V. Once this is achieved, the buck converter is activated and
the LDO generating V1.8V is switched off.

3.5.2 Power Good Detection

The power good detection provides the information, which voltages are
available to the control logic. As previously described, it is not required
to manage supply voltage drops since a sufficient external power supply is

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V15V starts
rising

5V LDO
starts operation

V5V ok no
&
Vref ok
yes
activate
1.8V LDO

V1.8V ok
&
no
V15V > 12V

yes
activate
Buck Converter
deactivate
1.8V LDO

Figure 3.23: Flowchart of regular start-up sequence.

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 3 Power Management Unit

ensured. Its main task is to enable the control logic to coordinate the start-
up routine. In addition to this, the voltages are continuously monitored
and the outputs are provided to the SPI for digital readout.

Power Good V5 V

The monitoring of V5V is shown in figure 3.24. M1-3 together with the OP
and the feedback divider form the LDO from figure 3.15. R1 of the feedback
loop of the LDO is split into R11 and R12 , giving the additional feedback
voltage Vfb,high . This voltage is compared to Vref by the additional com-
parator, resulting in AVAIL5 V . A potential offset between the closed loop
OP and the comparator can thereby be compensated, since the comparator
triggers at a voltage of V5V , which is slightly below its final voltage. Thus,
R12 is relatively small compared to R11 because only a voltage drop in the
range of the input offset voltage is required.

M1 V5V
V15V

Cbuf
M2 R11
Vfb,high
AVAIL5V
R12

M3 Vref
V5V monitoring
R2

Figure 3.24: Voltage monitoring of V5V .

AVAIL5 V is not sufficient to determine, whether V5V is at a good level.

During the start-up, glitches can happen because of a poor Vref and an
already operating comparator. Therefore BGactive , which is available from
the bandgap reference, is combined with AVAIL5 V in an AND conjunction
to determine PGV5 as shown in figure 3.25.

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 3 Power Management Unit

AVAIL5V
PG5V
BGactive

Figure 3.25: Calculation of PGV5 .

Power Good V1.8 V

Figure 3.26 shows the voltage monitoring of V15V and V1.8V . For this
monitoring, it can be assumed that the bandgap reference is active and
Vref is always available when V1.8V is available. During a regular start-
up this always applies, since V1.8V is only generated after V5V is available.
So the only exception to this is the signal AVAIL1.8 V , which is generated
independently of the bandgap reference and indicates a sufficient V1.8V .
The main output P G1.8 V should indicate that the generation of V1.8V is
finished and a handover to the buck converter is possible. Following from
the start-up routine, V1.8V has to be available and V15V has to be above
12 V. Since the reference voltages are only valid when V1.8V is available,
this condition has to be tested independently of the bandgap reference.
The V15V monitoring is realized by the voltage divider R1 and R2 , whose
output voltage is compared to Vref by the comparator C1. The output
signal PG15 V becomes logical high, when V15V is above 12 V.
The independent reference generates Vref,so , which is between 1.02 V and
1.30 V, and thus far off the accuracy of the bandgap reference voltage Vref .
However it is sufficient to detect a voltage at which the synchronous digital
part is functional.
The monitoring of V1.8V comprises the feedback divider R4 to R7 with the
taps Vfb,LDO1 .8 , Vfb,buck and Vfb,avail . R4 and R7 have the highest values so
the taps are relatively close to each other. These multiple taps are required
to compensate for input voltage offsets of the comparators and feedback
voltages, so the signals are set in the correct order. Vfb,LDO1 .8 is directly
fed to the V1.8V LDO to economise a second voltage divider in this LDO.
This voltage is the lowest in the feedback divider and, thus, results in the
highest output voltage.
The comparator C2 compares Vfb,avail to Vref,so , so AVAIL1.8 V indicates
that V1.8V is at least available. This signal can be used to enable the SR
flip-flop. Finally, Vfb,buck is compared to Vref in the control of the buck
converter resulting in CMPbuck . Reusing this signal has the advantage,

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that no additional offset voltages have to be taken into account. An AND

gate combines CMPbuck and PG15 V and sets P G1.8 V , the output of the
SR flip-flop, if the flip-flop is enabled by AVAIL1.8 V . An SR flip-flop is
used because CMPbuck is periodically reset during the normal operation of
the buck converter. Thus, once P G1.8 V is set, it can not be reset again
except by switching off the ASIC. However this is acceptable, since the
supply of the ASIC is expected to be available once the ASIC has started
operation.

V1.8V V1.8V monitoring

independent
V15V monitoring
reference R4
Vref,so C2
V1.8V AVAIL1.8V
V15V Vfb,avail
R5
R3 Vfb,buck Buck
R1
Vref CMPbuck
Vref Vref,so S Q PG1.8V
C1 R6 PG15V
PG15V
Vfb,LDO1.8 '0' R Q
EN
R2 R7
AVAIL1.8V

Figure 3.26: Voltage monitoring of V1.8V and V15V .

3.5.3 Debug and Backup Features

Although modern electronic design automation (EDA) tools enable a very

accurate simulation of the implemented circuits, unexpected behaviour of
the ASIC can always occur. To mitigate the risk of a failure in the PMU
obstructing the function of the whole ASIC, additional backup techniques
are implemented. In addition to this, trimming circuits and the readout
of multiple control signals are implemented to allow debugging the output
voltages.
One possibility to trim the output voltages it is to modify the feedback path
of the supply generations. Figure 3.27 shows the principle which allows
to inject a current into the feedback path, whereby the supply voltages
can be trimmed. The resistive feedback divider R1 and R2 generates the
feedback voltage Vf b out of Vsup , which is controlled by the OP in a way
that Vf b = Vref . By M1, the reference current Iref is mirrored to the
weighted pull-down trimming network illustrated by M2. TRIM n switches

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the mirrored currents via M3. Thereby, a trimming current Itrim is injected
into the feedback divider. This results in a supply voltage
R1
Vsup = Vref · (1 + ) + Itrim · R1 (3.6)
R2
assuming that the feedback loop is stable. The pull-up trimming network
is implemented similarly.

Vsup
trim
pull-up
R1
Itrim Vfb

R2 Vref
Iref TRIMn M3

M1 M2
trim ×n
pull-down

Figure 3.27: Trimming of the feedback paths.

Beside the trimming functionality for the supply voltages, backup features
are added to the system. The principle is that they allow for an external
application of the internal generated supply voltages. This enables a mea-
surement of the ASIC in case that one of the LDOs or the buck converter
shows malfunctions. Therefore the voltages need to be available at an ex-
ternal pin and the control needs a possibility to inhibit the on switching
of the LDOs and the buck converter. Since the supply voltages are all
externally buffered, the first condition is already fulfilled. For the second
requirement, the control logic features a disable input for the LDOs and
the buck converter. These inputs are set via SPI and, thus, only valid if
V1.8V is sufficient to allow an operation of the synchronous digital part.
The control logic is depicted in detail in the next section 3.5.4. A feature,
which disables V10V , is not implemented since V10V is not generated by a
control loop, but straight forward by a bandgap reference with a push-pull
output buffer.
There are two anticipated error classes. A malfunction only of the buck
converter or a malfunction of one or both of the LDOs. If only the buck

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converter is not working, the start-up routine can be used until the buck
converter is activated. This easily can be avoided by limiting V15V to 11 V.
Thereby the second condition for the enabling of the buck converter is not
valid, and thus the LDO will be kept active.
If one of the LDOs shows a malfunction, it is not possible to run the start-
up routine, since the LDOs can only be deactivated after V1.8V is available.
Instead, it is possible to slowly ramp up V1.8V and V15V to 1.8 V both at
the same time. Thereby, the parasitic diode of the pass transistor of the
V1.8V LDO is not forward biased and V5V is not generated, since the leakage
prevents the LDO from starting when V15V rises too slow. However, even if
the V5V LDO starts, V5V will not get beyond 1.8 V, so the start-up routine
is not continued. Given V1.8V = 1.8 V, the synchronous digital part is
functional, and thus the SPI can be used to set the disable inputs of the
LDOs and the buck converter. When these are set, the supply voltages can
be provided externally.
A subsequent handover from an external supply to the internal LDO is
possible. Therefore, the external supply needs to be set to a value, which is
definitely above the voltage, to which the LDO controls the supply. In this
case, the LDO detects a too high voltage and even if activated, does not
conduct charge to the supply. Now the external supply can be detached and
the LDO takes over control. If the external voltage was in a range where
the LDO activated the pass transistor, a high current could flow through it,
possibly damaging the ASIC. A Handover to the buck converter is possible
too. Therefore, first the control has to be given to the V1.8V LDO. If then
the buck converter is activated, it will become active and take over the
control from the LDO.

3.5.4 Logic of the Control

The asynchronous logic of the PMU control aggregates the power good
signals to generate enable signals for the LDOs and the buck converter,
enforcing the specified start-up routine. In addition to this, it enables the
debug features, especially the possibility to switch off the LDOs or the
buck converter. In order to fulfil this, the logic operates in multiple voltage
domains. Since V5V is available first during the regular start-up, most of
the logic is implemented in the V5V domain. The V1.8V domain is necessary
for the backup features from section 3.5.3, especially to switch off the V5V
LDO before V5V is generated or available.

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The input signals from the SPI which are SPI DISLDO5 V , SPI DISLDO1.8 V ,
SPI DISbuck , are provided in the V1.8V domain. The power good detection
provides the signals AVAIL1.8 V , PG5 V and PG1.8 V . Except for PG5 V and
PG1.8 V , these signals are provided in V1.8V domain and need level shifters
to shift them to the V5V domain.
The output signals are the enable and disable signals for the LDOs and
the buck converter. ENLDO5 V and ENLDO1.8 V enable the LDOs and are
in the V5V domain. DISLDO5 V disables the start-up of the V5V LDO. Since
this is required, if only V1.8V is available, this signal is set in V1.8V domain.
ENbuck enables the buck converter, whose control is implemented in V1.8V
domain. To securely switch off the buck converter during the start-up,
when V1.8V is not yet stable, the additional signals ENbuck@5V and DISbuck
are implemented. Since the disable signal is required to be active if both,
only V1.8V or only V5V , is available, it is in a mixed domain corresponding
to the maximum of V1.8V and V5V .
The logical conjunctions are implemented straight forward. AVAIL1.8 V is
connected to the disable signals via an AND or NAND gate so the LDOs
and the buck converter can only be switched off if the digital part pro-
vides valid signals. ENLDO5 V is set to logical high, if it is not disabled
by SPI DISLDO5 V . A capacitance ensures, that the output of the NAND
gate rises together with V5V before it actively conducts current. Equally,
DISLDO5 V is set to logical low, if it is not activated by the SPI. Similarly fo
ENLDO5 V , a capacitance ensures the correct output state before the AND
gate gets active.
The signals for the buck converter directly interrelate and only differ in
polarity and voltage domain. The buck converter is activated, if PG1.8 V
is logical high and the buck converter is not disabled via SPI. Finally,
ENLDO1.8 V activates the V1.8V LDO, if PG5 V is logical high, the LDO is
not deactivated via SPI and the buck converter is not active. Thar way, the
handover from the LDO to the buck converter is handled smoothly during
the start-up.
DISbuck has to inhibit the signal transmission in the buck converter control
via a transmission gate [147] if both, only V1.8V or only V5V , is available.
Therefore, an auxiliary supply of an inverter Vaux is generated as depicted
in figure 3.29. The two PMOS transistors are cross coupled and their bulks
are connected to Vaux , as this is supposed to be the maximum of V1.8V
and V5V . The cross coupling makes M1 conduct if V5V is higher than V1.8V
resulting in Vaux ≈ V5V , which is the case during regular operation. Vice

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V5V

ENLDO5V

SPI_DISLDO5V
DISLDO5V
AVAIL1.8V
1.8V domain

PG5V
ENLDO1.8V
SPI_DISLDO1.8V
AVAIL1.8V ENbuck@5V
PG1.8V
SPI_DISbuck ENbuck
AVAIL1.8V 1.8V domain
Vaux
DISbuck
mixed domain

Figure 3.28: Control logic for start-up.

versa, if V5V is lower than V1.8V , M2 conducts leading to Vaux ≈ V1.8V .

This is the case if the digital part is switched on for debugging. So Vaux ≈
max(V5V , V1.8V ). Thus Vaux can be used to invert the V5V input signal
ENbuck@5 V to DISbuck .

3.6 Measurements of the PMU

The smart gate driver IC was implemented in the 0.18 µm high voltage
(HV) CMOS technology supplied by Austria Mikro Systeme (AMS). The
die has a size of 2.83 mm · 2.35 mm and is bonded in a Quad Flatpack
No-Lead (QFN) 36 package [75]. Figure 3.30 shows the micrograph of the
ASIC. Most of the bonds are required to the supplies and outputs of the
segmented output stage. The ground connection is given by the exposed
die pad and connected with several down bonds. The bonds in the lower
left are connected to the synthesized digital part and provide an SPI and
other required digital IO pins. The bonds in the lower middle of the die
are connected to the PMU and provide the external pins of V1.8V , V5V and
Vsw .
Figure 3.31 shows a zoomed in micrograph of the ASIC. The red frame
marks the PMU, which covers an area of about 450 µm × 650 µm. The

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V5V V1.8V

M1 M2

Vaux

ENbuck@5V DISbuck

Figure 3.29: Generation of auxiliary supply voltage.

Figure 3.30: Micrograph of gate driver IC.

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Figure 3.31: Micrograph of the PMU of the gate driver IC.

power transistors of the output stage of the buck converter are clearly
visible at the right-hand side. At the left-hand side, parts of the bandgap
reference are visible in the irregular structures. Most of the other circuitry
is covered by the top metal routing of V1.8V and V5V .
For the measurement of the gate driver IC, a PCB was developed by
Christoph Lüdecke from the project partner Institute for Power Electronics
and Electrical Drives (ISEA). It features a power supply, the power tran-
sistor, which is to be switched, a digital clock oscillator and an interface
to a microcontroller, which allows communication with and control of the
ASIC.
To measure the PMU, only the connection to an external power supply
and the buffering capacities were soldered onto the PCB. Thereby V15V
was only buffered with a small capacitance to allow a fast rising edge at
start-up. The other supplies were buffered as simulated with Cbuf ,5 V =
100 nF and Cbuf ,1.8 V = 4.7 µF. In addition to this, measurements with
Cbuf ,1.8 V = 100 nF were made, which was possible because the digital
part was not activated. However, the buck converter measurement shows
that the capacitance is too low for the operation of the buck converter
as seen in figure 3.37. Therefore, another measurement with an increased
Cbuf ,1.8 V = 4.8 µF was performed. An additional required 3.3 V input
voltage, which supplies the IO-ring was externally supplied. All digital

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inputs, including the oscillator input, were connected to GND and the
outputs were unconnected. Thereby, the function of solely the PMU with
as less interference as possible was measured.

3.6.1 Measurement 1 V15V = 10 V

As the buck converter is a potential cause of failure, first only the operation
of the LDOs was measured. To achieve this, the external supply V15V was
only ramped up to V15V = 10 V. Since the capacitive start-up is expected to
work better at short rise times of V15V , a steep input slope is chosen. Doing
this start-up, the LDOs should be activated and start to generate their
output voltages. In contrast to this, the buck converter is kept switched off
since V15V < 12 V as described in section 3.5.2.
Figure 3.32 shows the results of this measurement. The slope of V10V rises
with a steepness of 14.8 V ms−1 . V10V is capacitively coupled to V15V and
follows at first as intended. V5V is activated early and at V15V ≈ 3 V, the
control loop gets active, which rapidly brings V5V close to V15V , where it
keeps following until the final voltage V5V = 5.17 V, which is inside of the
production tolerance of the ASIC. At the same time, V5V rises rapidly, V10V
drops indicating that the bandgap reference gets active. As it is not able
to reach the targeted voltage of V10V = V15V − 5 V at first, it follows V15V
after a supply voltage of V15V ≈ 6 V. Due to the small external capacitance,
V1.8V starts fluctuating. At the time V5V crosses 4.8 V, the V1.8V LDO is
activated and rapidly generates V1.8V .
The observed behaviour of the supply voltages compares well to the in-
tended and expected sequences. V5V and V1.8V show the slope of the mod-
erate start-up shown in figure 3.17. V10V behaves similar as described in
figure 3.10. Thus both implemented LDOs as well as the bandgap reference
operate as expected.
Figure 3.33 shows a detailed view of the start-up of V1.8V . It is clearly
visible that V1.8V does not directly approach the target voltage. Instead,
a kickback occurs at a voltage of around V1.8V ≈ 0.8 V. This most likely
is caused by the big integrated digital part. When the supply voltage is
sufficient to activate the digital gates, they will all flip to the intended reset
states. Since this happens at different threshold voltages, the settling can
take up much longer than at full supply voltage. In addition to this, the
cross currents of the logical gates during their input transition increase the

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10 V15 V
V1.8 V
V5 V
8
V10 V
Voltage [V]

0
−0.5 0 0.5 1 1.5 2
Time [ms]

Figure 3.32: Measurement with V15V = 10 V.

current demand, which especially at slow transients is relevant. However

the LDO is able to supply the required power, and after the digital circuits
are settled V1.8V continues to increase until the final voltage of V1.8V ≈
2.0 V. This is slightly above the targeted value of 1.8 V, which is expected
for the output voltage of the LDO as described in section 3.5.2.

3.6.2 Measurement 2 V15V = 15 V

After the LDOs were successfully tested, measurements with a supply of

V15V = 15 V were performed to test the buck converter. It should become
active after V5V and V1.8V are generated and V15V > 12 V. Figure 3.34
shows V15V , V5V and V10V for this start-up, not mentioning V1.8V and the
buck converter. The supply voltages are still accurately generated. In this
measurement, the connection of V10V = V15V − 5 V is clearly visible. V10V
even follows V15V during the slight decrease until the steady state.
Figure 3.35 shows V15V , V5V , V1.8V and Vsw during the start-up. In this
measurement, a load resistance of Rload = 100 Ω was added to V1.8V .
Thereby an additional current of Iload = 18 mA is applied to the auxiliary
LDO and the buck converter. This should test whether the buck converter

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 3 Power Management Unit

1.5
V1.8 V [V]

0.5

0
0.22 0.23 0.24 0.25 0.26
Time [ms]

Figure 3.33: Detail view of V1.8V .

15
Voltage [V]

10

5
V15 V
V5 V
V10 V
0
0 1 2 3 4
Time [ms]

Figure 3.34: Start-up for V15V = 15 V.

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 3 Power Management Unit

is able to supply a load in the range of the designed load of 25 mA. Since
the already drawn internal currents are unknown, this resistance was cho-
sen. In addition to this, the buffering capacitance at V1.8V was increased
by 4.7 µF to then 4.8 µF. This was necessary, because the voltage ripple of
V1.8V , caused by the buck converter, was higher than desired as shown in
figure 3.37.
The slopes of V15V and V5V equal the slopes from figure 3.34. In contrast
to measurement 1, V1.8V ≈ 0 V before the LDO gets active. This is a result
of the increased buffering capacitance. At the beginning, Vsw equals V1.8V
as expected. At a voltage of V15V ≈ 12 V, the control activates the buck
converter, which starts switching. This is visible in the heavy switching of
Vsw . Since the switching frequency is very high, the different cycles are not
visible in this figure. However, V1.8V remains constantly controlled, despite
the load, which shows the correct performance of the buck converter.

15 V15 V
V1.8 V
V5 V
Vsw
Voltage [V]

10

0
0 1 2 3 4
Time [ms]

Figure 3.35: Measurement with V15V = 15 V showing Vsw .

3.6.3 Buck Converter Measurements

To look in detail into the function of the buck converter, figure 3.36 shows
a single switching cycle of the buck converter. Out of an idle state a pulse

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 3 Power Management Unit

of ≈ 100 ns charges the inductor by connecting Vsw to V15V . The increas-

ing voltage drop across the path transistor is visible at the trace as Vsw
slightly drops below V15V towards the end of the pulse. The pulse is ended
by disconnecting Vsw from V15V . This causes Vsw to drop below GND and
the inductor is discharged. In this period, Vsw is relatively close to GND,
which indicates that the discharge transistor is switched on. Thus the im-
plemented high voltage comparator, described in section 3.4.2 functions as
intended. At the end of the cycle, the path transistors of the buck con-
verter are both switched off. Now the remaining energy in the inductance
degrades, due to parasitic resistances during the ringing, until Vsw settles
to V1.8V . The observed cycle very well matches the cycle as it was designed.

15 V15 V
V1.8 V
Vsw
10
Voltage [V]

0
4.003 4.004 4.005 4.006
Time [ms]

Figure 3.36: Detail of buck converter converter cycle.

To illustrate the function of the PFM control of the buck converter, fig-
ure 3.37 shows two cycles, which were unintentionally measured with a too
low capacitance. However, they nicely illustrate the PFM control. With
the applied capacitance of Cbuf ,1.8 V = 100 nF, the charge pulse of each cy-
cle increases V1.8V up to 4.4 V. During the discharge of the inductor, V1.8V
remains relatively constant due to the steadily conducted current. After
the buck converter returns to idle mode, V1.8V quickly decreases until it
becomes low enough to trigger the next switching cycle. Since this V1.8V

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 3 Power Management Unit

operates the connected transistors far off their specified voltage range, the
behaviour is not characterized by the simulation models any more. How-
ever, a breakdown can not be recognized. This most probably does not
happen because most of the ASIC is switched off and the electrostatic
discharge (ESD) protection takes most of the charge. Thereby, no high
currents damaging internal transistors are induced. Nevertheless, a signif-
icantly increased ageing during this operation is probable.

15
V15 V
V1.8 V
10 Vsw
Voltage [V]

0
4.0 4.001 4.002 4.003
Time [ms]

Figure 3.37: Buck converter cycle showing the control functioning.

Figure 3.38 shows Vsw for two different load states. The blue trace depicts
the measurement from figure 3.35 with a load resistance of Rload = 100 Ω,
and thus a load current above Iload > 18 mA. The red trace depicts a
measurement without an external load. The different load states clearly
appear in the different frequencies. Without a load, a switching frequency
of fsw ≈ 19.6 kHz is observed. In contrast to this, with the applied load
resistance, the observed frequency is fsw ≈ 258 kHz. Thus, the switching
with the external load is more than thirteen times faster. Since at a PFM
control the switching frequency is directly proportional to the load [129],
the internally drawn current can be determined to Iinternal ≈ 1.5 mA.
In multiple extra measurements, the start-up of the circuit was successfully
tested for different rise times trise . Up to a rise time of trise ≈ 30 ms, the
start-up functioned properly. However, the used supply source was not able

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 3 Power Management Unit

15 Rload = 100 Ω
no external load

10
Vsw [V]

0
3.93 3.94 3.95 3.96 3.97 3.98 3.99 4
Time [ms]

Figure 3.38: Different buck converter cycle lengths.

to run a specific ramp. Instead, the input voltage ramped up very steeply
at first and much slower after V5V approaches 5 V as already visible in
figures 3.32 and 3.35. Nevertheless, the principle functioning of the PMU
and especially the successful start-up of the circuit was shown up to this
trise . Moreover, the proper operation of the LDOs, the buck converter and
the coordinating PMU control is shown by the measurements.

3.7 Further Improvements of the Start-up LDO

The dependency on the rise time of the supply is the major limitation for a
secure start-up of the V5V LDO, as described in section 3.3.1. At too high
rise times, the capacitive activation is throttled by leakage currents, which
causes the PMU, and thus the ASIC to not start. Especially for higher
temperatures the leakage current exponentially increases, so a failure at a
restart after an operation of the ASIC might occur. To overcome this limi-
tation and to be able to use the start-up concept in a PV energy harvesting
ASIC, a leakage based start-up circuit is described in section 3.7.1. An im-
proved start-up detection utilizing already implemented signals is shown
in section 3.7.2. Finally, another start-up detection, based on a provided

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 3 Power Management Unit

reference current is shown in section 3.7.3. The circuits are shown and
tested at the example of the V5V LDO. Nevertheless, they can be applied
to a generalized LDO with self start-up capability.

3.7.1 Leakage activated start-up circuit

The basic principle of the improved start-up circuit is to utilize the leakage
current of a switched off transistor. Figure 3.39 shows the LDO with the
new start-up circuit. The LDO and the current injection are not changed
with respect to section 3.3.1. The improvement is made in the generation
of Vg . Instead of a capacitive activation of M4, a continuous leakage current
is generated by M6 and conducted to the MOS diode composed of D1 − 3.
This gives a voltage Vg , which activates M4. The leakage current mainly
depends on the temperature, which can be assumed equal for the small
start-up circuit. Thus, only the mismatch of the transistors limits the
reproducibility. Since the MOS diode transistors can be matched to M4,
Vg is always sufficient to conduct the start-up current through R3 . As in
the previous version, the start-up circuit can be switched off via M5 and
Vso . For this, the same start-up detection circuit as previously described
can be used.
The leakage current, which is used in this concept, keeps flowing after the
start-up is finished. However, the leakage current is in a range of several
nA to pA, and thus very small. Moreover, a comparable leakage current
occurs at all transistors and wells in the ASIC, so the additional leakage
may be acceptable in most cases. Since the leakage current no more limits
the rise times of the supply, the ASIC will start with any start-up time of
the supply. This highly improves the reliability of the PMU under unsure
conditions. However, since Vg is no more capacitively charged, the self
throttling of the start-up detection might become an issue. For this, the
start-up detection would require further investigation. First simulations
show a reliable start-up behaviour of the concept for all circumstances and
very high rise times showing the potential of the leakage utilization.

3.7.2 Improved start-up detection

To reduce the circuit overhead, it is desirable to simplify the start-up detec-

tion. This can be done by combining the information whether the bandgap

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 3 Power Management Unit

V15V M1 V5V

Cbuf
start-up circuit
M2
M6
R1
R3

Vg M3 Vref
M4
D3 R2

LDO
Vso M5 D2

D1

Figure 3.39: Improved start-up circuit for the LDO with leakage activation.

reference is active and whether V5V is at the targeted level, similar to the
power good detection. In this case logical gates can not be used for an
AND conjunction of BGactive and AVAIL5 V since there is no supply volt-
age for them. Instead, they can be combined by two stacked transistors in
series.
Figure 3.40 shows the tested implementation of this start-up detection. The
LDO and start-up circuit are the same as the leakage based start-up circuit,
the V5V monitoring is equal to section 3.5.2. Transistors M5 and M7 realize
the required AND conjunction of BGactive and AVAIL5 V to clamp Vg to
GND, once the start-up is finished. This start-up detection was simulated
showing a good performance in all relevant process corners.

3.7.3 Start-up detection with reference current

In case that a reference current Iref is available during the start-up, a start-
up detection utilizing this current is possible. Such a reference current can
be generated by an UVLO circuit, which is active before the start-up of the
LDO. Another possibility is a coarse reference current based on a resistor
connected to the main supply voltage.

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 3 Power Management Unit

V15V M1 V5V

Cbuf
start-up circuit R11
M2
M6
Vfb,high
AVAIL5V
R3 R12

Vg M3 Vref
M4
V5V monitoring
D3 R2
AVAILV5V
M5 LDO
D2

BGactive
M7 D1

Figure 3.40: Start-up circuit for the LDO with improved start-up detection.

Figure 3.41 depicts an implementation of a reference current based start-

up detection [146]. The LDO and start-up circuit are equal to the leakage
based one in section 3.7. The start-up detection is based on a monitoring of
the state of operation of the OP. The end of the start-up is detected, when
the output of the OP is not overdriving M3 any more which indicates that
the divided voltage of V5V gets near Vref , and thus V5V gets near its target.
For this, the OP has to be designed in a way that its output is at V5V when
it is inactive. The detection is done by comparing the current of M7 to the
reference current mirrored by M8 and M9. If the output of the OP is far
enough below V5V , the hypothetical current through M7 will become higher
than the reference current. Thereby Vso is drawn to V5V enabling M5. To
avoid a false Vso at low V5V , M5 is matched to M3. Thereby, the start-up
circuit can only be deactivated when M3 is able to conduct a current and
the control loop is only limited by the OP.
To get a more controlled start-up, the leakage current of M6 can by replaced
with a reference current mirror. Thereby, the current through the diodes
is not exponentially depending on the temperature any more. However,
in this concept, in addition to the leakage current, the reference current
for the detection keeps flowing throughout the whole operation time of the
ASIC. Since this current is limited and well known, this can be acceptable
depending on the application.

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 3 Power Management Unit

Simulations show a good performance of the concept. A sample imple-

mentation shows a reliable performance in all corners and Monte Carlo
simulations. This is achieved even for an application in an LDO generating
1.8 V, where the headroom for the decision whether the start-up is finished
is significantly smaller than for a 5 V supply.

V15V M1 V5V

Cbuf
start-up circuit M2
M6
R1
R3

Vg M3 Vref
M4
D3 R2

Vso LDO
M5 D2
V5V start-up
M7 detection
D1
Vso Iref

M8 M9

Figure 3.41: Start-up detection for the LDO with given reference current.

84
 Chapter 4
Energy Harvesting ASIC

In section 2.3 and chapter 3, the basic architectures of a PMU, the start-
up and the MPPT are presented. This chapter gives detail on the imple-
mentation and the chosen architecture in an ASIC in the 180 nm bipolar-
CMOS-DMOS (BCD) technology from Taiwan Semiconductor Manufac-
turing Company (TSMC). First in section 4.1 the MPPT topology and
MPPT technique are selected. The derived system design is detailed and a
block diagram is given in section 4.2. Subsequently, design considerations
of the DC-DC converter are discussed in section 4.3, based on the topology
selection. However, this circuit was implemented by Michael Hanhart, so
the level of detail is not as high as in other sections. The implementation of
the PMU is expound in section 4.4, based on the experience from the first
implemented PMU from chapter 3. The implementation of the selected
MPPT technique into an ASIC is discussed on in section 4.5. Section 4.6
gives details on the actual circuits of some blocks and finally simulation
results are given in section 4.7.

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 4 Energy Harvesting ASIC

4.1 Selection of MPPT Concept

The intended application of the PV system drives the selection of the topol-
ogy as well as the MPPT technique. According to section 1.1, the PV
energy harvesting system should be applicable to BIPV as well as IIPV.
Especially for IIPV, much shading and very fast changes of irradiance due
to passing cars are expected. BIPV faces similar challenges when applied
at low heights. However, even the application in small sized PV modules on
rooftops yields in inhomogeneous irradiance conditions from shading and
orientation mismatch. These will mainly change due to the weather and
clouds or shading from static objects and the direction of the sun.

Topology

To select a topology, the different topologies presented in section 2.3.2

are compared in table 4.1. The given application requires a high shad-
ing tolerance. A high efficiency and flexibility at as low cost as possible
are beneficial. Following from these requirements, the substring buck and
-boost topology are the most promising topologies. Both feature a high
shading tolerance and flexibility at an average complexity and a sufficient
efficiency. However, the boost converter has a lower input current ripple
and reduced resistive losses when compared to the buck converter, as de-
scribed in section 2.3.2. Therefore, the boost converter is selected for the
implementation.

Topology Complexity/ Efficiency Shading Flexibility

Cost Tolerance
String Inverter low high low low
Micro Inverter medium medium medium medium
Module/ Submod. medium medium medium medium
Optimizer
∆ Concept high medium high low
Virtual Parallel high medium high medium
Substring Buck medium medium high high
Substring Boost medium medium high high

Table 4.1: Comparison of topologies.

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 4 Energy Harvesting ASIC

MPPT technique

The MPPT technique for the PV system should be able to interoperate well
with the boost converter. For the implementation of the boost converter,
the cost should be as low as possible while maintaining a high efficiency.
To reduce the size of external components, save costs and achieve a high
energy density, a high switching frequency is desired. Therefore, the MPPT
has to handle these switching frequencies. A high tracking performance at
low cost is also desirable. Moreover, the MPPT has to be fast enough to
keep track to rapid irradiation changes caused by passing cars. As a simple
interface between the MPPT and the boost converter, the control of the
boost converter should maintain an input voltage, which can be adjusted
by the MPPT. Table 4.2 shows an overview of the presented MPPT tech-
niques. Due to the poor tracking efficiency, the very simple techniques are
not suitable in the given application. Despite being well known and widely
used, the modified RCC technique with an artificial imposed perturbation
seems the most promising. Without the need for big computation power or
very fast ADCs, it offers a potentially very cost and energy efficient imple-
mentation. Another advantage is current sensing with a variable resistor.
Thereby, an accurate sensing even at low currents is possible, what is usu-
ally limited by the small current measuring shunt resistor. Since mainly the
relative behaviour of VPV and IPV is evaluated, there is no need for their
absolute values. This further reduces the requirements of the implemented
circuits.

MPPT Complexity/ Tracking Tracking Flexibility

Technique Cost Efficiency Speed
FSCI low low high low
FOCV low low high low
P&O medium high low high
InCond medium high medium high
RCC medium-high high high medium
modified RCC medium high high high

Table 4.2: Comparison of MPPT techniques.

The block diagram is shown in figure 4.1. The analogue preprocessing is

not altered in comparison to the modified RCC technique from figure 2.20.

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 4 Energy Harvesting ASIC

However, the correlation of Vmeas,V and Vmeas,I is significantly changed.

The MPPT control introduces an perturbation on VPV . Thereby, the corre-
lation can be spread across multiple switching cycles, reducing the required
bandwidth of the analogue circuits. Since now the sign of dVdtPV is known,
the sensing of VPV is not necessary any more, minimizing the measure-
ment path of the correlation. For a successful operation, it is important
that the frequency of the perturbation is still above the bandwidth of the
preprocessing to avoid interference.
Using these adaptions allow for a boost converter operation with a small
input current and voltage ripple. Moreover, it is possible and beneficial
to perform the correlation and the preprocessing at time discrete steps.
Thereby, a big share of the processing can be moved to the digital domain
increasing flexibility and power efficiency. Especially the integrators can
be implemented very efficiently in the digital domain. Since the sampling
is done synchronously to the boost converter switching, the sensitivity to
the switching noise will be lowered by a carefully timing of the sampling.
Therefore, it should apply in a moment where the boost converter does not
switch its outputs as for example during the minimum on time. In total
this can be considered an InCond technique where the basic condition is
evaluated as in an RCC MPPT.

Vin Boost
Converter

Vout
correlation
VPV ∫

d
∫
-Vmeas,I SGN MPPT
dt
CTRL
perturbation
Vin
Rvar R1

-1 Vmeas,V

R2

preprocessing

Figure 4.1: MPPT from figure 2.20 with adapted perturbation.

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 4 Energy Harvesting ASIC

4.2 System overview

In the previous section, the topology was selected to use a submodule boost
converter together with a combination of InCond and RCC techniques for
the MPPT. Based on this, the requirements on the ASIC are detailed and
the system block diagram is developed.

4.2.1 Requirements

As previously mentioned, the ASIC is dedicated for a use in a PV energy

harvesting system. Due to the submodule boost converter topology, only a
small number of solar cells is connected to each ASIC. An inhomogeneous
and quickly changing irradiance is expected due to the application in BIPV
and IIPV systems. The MPPT should be able to accurately find the static
MPP, which leads to a high required static tracking efficiency ηmppt,stat .
Each offset from the MPP directly results in a loss of potentially harvested
power. Therefore, a tracking efficiency of ηmppt,stat = 99.9 % is desirable
for static conditions. Dynamic changes of the irradiance will reduce the
achieved tracking efficiency due to the limited reaction time of the MPPT.
However, the dynamic slopes of passing bikes or cars, a tracking perfor-
mance of ηmppt,dyn > 99 % should still be achieved [154].
For a wide area of application, the boost converter has to be compati-
ble to standard silicon solar cells. Based on this, a nominal input volt-
age of Vin,nom = 10.5 V corresponding to 19-20 solar cells in series, is
selected [1]. To be able to support all irradiation and temperature con-
ditions and to obtain a flexibility of usage, an input voltage range of
Vin,min . . . Vin,max =ˆ 7.5 . . . 18 V is selected. This gives some flexibility
on the exact number of cells in series. The maximum input voltage ripple
should be as low as possible. Nevertheless, some ripple is inherently present.
For a triangular input peak to peak ripple of Vin,∆ = 0.3 V the thereby
caused losses are about 0.054 % [127]. At a ripple of 0.2 V, the losses are
reduced below 0.024 %. However, reducing the ripple comes at the cost of a
higher inductance or switching losses and the losses at 0.054 % are already
small enough to achieve ηmppt,stat . Therefore Vin,∆,nom = 0.3 V should be
maintained in the nominal case. In more extreme cases, a higher ripple is
tolerable. The switching frequency in this trade-off is fsw = 300 kHz.

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 4 Energy Harvesting ASIC

The maximum input current Iin,max = 9.5 A is selected. This is necessary

to operate the short circuit current of commercial modules of Isc = 9.08 A
and leave some space for the increase at higher temperatures [1]. However,
due to the changing irradiance, the converter should have a good efficiency
at input currents down to at least 5 % of Iin,max .

Specification Symbol Value

Static tracking efficiency ηmppt,stat 99.9 %
Dynamic tracking efficiency ηmppt,dyn 99 %
Input voltage, nominal Vin,nom 10.5 V
Input voltage range Vin,min to Vin,max 7.5 . . . 18 V
Input voltage ripple Vin,∆,nom 0.3 V
in nominal case
Input current, maximum Iin,max 9.5 A
Input current, good eff. Iin,min ∼ 0.4 A
Output voltage, nominal Vout,nom 30 V
Output voltage range Vout,min to Vout,max 10 . . . 50 V
Switching frequency fsw 300 kHz
Power switches external MOSFETs allowed
Cost as cheap as possible
Efficiency as high as possible
Control Variable input voltage Vin

Table 4.3: Specifications for the boost converter.

Since the converters are connected in series, the string voltage is distributed
to the different submodule power optimizers according to the individual
available power. Therefore the output voltage range determines the possible
shading tolerance. Since relatively much shading is expected, a shading tol-
erance of 80 % is desirable. A minimum output voltage of Vout,min = 10 V
should not be deceeded to leave some space for the boost converter for oper-
ation. To achieve the desired shading tolerance, a maximum output voltage
of Vout,max = 50 V is required. The nominal output voltage is selected to
Vout,nom = 30 V since a better efficiency can be achieved at smaller voltage
gains and Vout,max is only required at high mismatch conditions. Since the
input voltage is below the nominal voltage when the input power is low,
the low Vout,min does not limit the regular operation. However, at a higher
nominal input voltage of e.g. 14 V or very cold temperatures, the shading

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 4 Energy Harvesting ASIC

tolerance can decrease.

In comparison to internal power MOSFETs, external MOSFETs show bet-
ter switching performance since their technology can be optimized solely
for the application in power MOSFETs. To utilize this, the boost con-
verter should feature gate driver outputs which are able to drive external
MOSFETs in the power stage. A high efficiency of the boost converter is
desired. However, the cost should be kept as low as economically possible.
In contrast to commonly used boost converters, the ASIC has to control
the input voltage of the ASIC. This simplifies to set the operation point of
the PV cells and to adjust it to the MPPT. Thereby, the output voltage
gets variable which allows a series connection of the ASICs. An overview
of the developed specifications is given in table 4.3.

4.2.2 Block diagram

Figure 4.2 shows the block diagram of the ASIC to give an overview on
the implemented system. It mainly splits up into three different functional
blocks:
• Boost converter
• Power management unit (PMU)
• Maximum power point tracker (MPPT)
which are discussed in detail in the following sections. The boost converter
converter steps up the input voltage of the ASIC Vin decoupling the input
and output impedance. It consists of the power stage, the gate drivers and
the boost converter control. Two external power NMOSFETs switching
Vsw represent the power stage which controls the current through the in-
ductance L. Gate drivers switch the external power MOSFETs on and off.
For the high side switch, a bootstrap driver is implemented. The current
is sensed by the external resistor Rsense during the charging phase of the
boost converter. The resulting differential voltage Vsense,I feeds the control
with the current information. The boost converter control ensures a stable
operation in all states of operation. Therefore it features a CCM, a DCM
and a start-up control. An additional overvoltage protection takes action
when the output voltage exceeds the specified limits.
The MPPT features an external MOSFET operated in its ohmic region as
variable resistor for the current sensing. This MOSFET is controlled by

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 4 Energy Harvesting ASIC

Vout
Vin ≈ VPV
Cout
Cin CLK1M2
UVLO SPI
Boost Converter
V5V,drv V5V,drv Vbs
LDO
VPV CDRV V5V,ana RG,HS
LDO
V1.8V 1.2V Cbs
L
LDO BG
PMU
C1.8V Vsw
Boost RG,LS
CTRL
Vsense-
Vg,meas CTRL Vsense,I,+
MPPT
DAC Rsense
Vsense,I,-
Vsense+ MPPT

Figure 4.2: Block diagram of the ASIC.

the MPPT which is based on the selected technique. This basic, mainly
analogue, technique from figure 4.1 is modified into a mixed-signal imple-
mentation. The control of the boost converter by the MPPT is performed
by a DAC which converts the digital signal from the MPPT to the analogue
input of the boost converter.
The PMU provides all supply voltages which are required by the ASIC
out of Vin ≈ VPV , which is externally applied and generated by the PV
sub module. In addition to this, a bandgap reference provides an internal
reference voltage of Vbg ≈ 1.2 V. V1.8V = 1.8 V supplies the digital con-
trol and some other circuitry which is implemented with 1.8 V MOSFETs.
V5V,drv = 5 V is considered a noisy voltage because it supplies the output
drivers which cause high current peaks during the switching. These two
voltages are externally buffered to reduce the noise and to enable them for
the current demands during the switching of the digital circuits and the
output buffers. Finally, V5V,ana = 5 V is only an internal supply which
supplies noise sensitive circuits.
An additional SPI interface is implemented in the digital part. It allows to
modify the behaviour of the ASIC during runtime.

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 4 Energy Harvesting ASIC

4.3 Boost Converter

Different possible implementations for the boost converter, especially the
control circuits are mentioned in section 2.1.2. From the different control
techniques, the peak current control shows the highest potential for the
continuous conduction mode (CCM) due to their high control speed and
good stability. Following the specifications duty cycles of more than 50 %
are required. Therefore, an additional slope compensation is required. For
the discontinuous conduction mode (DCM), a PFM control with variable
pulses which base on Vin and Vout is selected. An analogue implementation
of the control avoids a high frequency digital clock which reduces the power
consumed by the digital control of the MPPT. Moreover, the operation
in a real steady state results in more accurate input signals and reduced
sub harmonic noise, which would be coused by a time discrete sampling.
To utilize the better efficiency at high input powers, the converter should
be able to operate in CCM. However, it is desirable to keep the external
components and, especially, the inductance L small. This results in an
increased current ripple, and thus a transition to the DCM at already
relatively high input currents. So the converter has to operate in CCM as
well as in DCM. Therefore, a mode boundary detection and a transition
control are necessary.
The values of the external components are calculated based on the volt-
age and current ratings in table 4.3. The selection of the external MOS-
FETs and the inductance L is a complicated trade-off between resistive and
switching losses. Simulations show that the NVMFS5C645NL [48] with an
Rds,on of Rds,on = 5.7 mΩ together with an inductor of L = 8.2 µH and
RL = 9.6 mΩ enable a high efficiency for a large range of converter power.
Therefore, these elements are selected as a trade-off.
The input capacitance mainly affects the input voltage ripple. The current
2·Vin
ripple in the nominal case during CCM is I∆ = 3·L·f sw
= 2.8 A. With this,
the input capacitance can be calculated to
I∆
Cin = = 15.5 µF (4.1)
2 · fsw · Vin,∆,nom

and thus Cin = 15 µF is selected. The output ripple is much less critical
since it does not affect the tracking performance. However, the capacitance
should not be too low, to avoid a high ripple when the converters are
stacked. Therefore a Cout = 10 µF is selected.

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 4 Energy Harvesting ASIC

Figure 4.3 shows the resulting block diagram of the boost converter. It fea-
tures the power stage including the inductance L, the MOSFETs and the
output drivers described in section 4.2.2. The input to the control is the
current, measured by the sense resistor Rsense . It generates the differential
measurement signal Vsense,I which is amplified and provided to the control.
This signal is modulated by the slope compensation, which adds an addi-
tional ramp [20]. The resulting signal is compared to the reference Vea by
a comparator. The switching logic coordinates the switching of the output
stages. A DCM detection monitors the internal state and determines the
mode boundaries. Based on this, the control mode is changed. An addi-
tional ramp emulation is implemented for the DCM. It generates a ramp
which imitates the current through L to determine the correct moment to
switch off M2 when there is no measured information on the actual inductor
current. Additional to the mode changes, a soft start-up is implemented.

Vout
ASIC – Boost Converer Control
V5V,drv Vbs
Cout
RG,HS
M2
Vin

R1 Cbs
Switching L VPV
CTRL Ictrl Vfb Logic Vsw
DAC Vea
Vbg RG,LS
from MPPT R2 M1
DCM
Detection
Ramp
Emulation

Vsense,I,+
Slope
Rsense
Compensation
Vsense,I,-

Figure 4.3: Block diagram of the implemented boost converter.

The main feedback of the control loop is on the left and feeds back Vin
through the feedback divider. The difference of the resulting Vfb and the
reference Vbg is amplified by the error amplifier closing the voltage control
loop. This gives Vea , the reference for the inner control loop. Since the

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 4 Energy Harvesting ASIC

error amplifier is implemented as an operational transconductance amplifier

(OTA), the compensation of the control loop can be implemented with the
shown RC network at Vea . The CTRL DAC draws a current Ictrl which
alters the feedback voltage Vfb and is controlled by the MPPT. This results
in
R1
Vin = Vbg · (1 + ) + Ictrl · R1 (4.2)
R2
when the control loop is closed and Vfb is controlled to Vbg . In the imple-
mentation R1 = 1.2 MΩ and R2 = 300 kΩ are selected. With a reference
voltage of Vbg = 1.2 V, this results in an set voltage of VPV = 6 V when no
current is applied by the DAC.
In addition to the mode changes, the boost converter control has some
more features. Firstly, a start-up control is implemented, which gradually
increases the inductor current when the converter is switched on. Moreover,
an overcurrent and output overvoltage protection is implemented to protect
the ASIC from damage. Especially an overvoltage at Vout can easily occur
in cases when a high power mismatch between the modules is present.
To limit the duty cycle a minimum on time is implemented. Even if this
limits the minimum conversion ratio, it guarantees a proper switching with
reasonable switching slopes.
The implementation of the boost converter directly affects the requirements
and possible performance of the MPPT. First of all, the control speed of the
boost converter limits the tracking speed of the MPPT. Even if the MPPT
operates with a higher measurement frequency, the reasonable update fre-
quency should be significantly below the control bandwidth. Otherwise
limit cycle oscillations can limit the MPPT performance [139]. Moreover,
the boost converter control provides a trigger signal, at which the switching
noise is small which is used for the synchronous sampling of the MPPT.
Directly before the end of the minimum on time, the noise from the on
switching is settled and the off switching is still inhibited. At this time,
the noise is reliably small. Therefore the trigger signal is actuated at this
moment.

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 4 Energy Harvesting ASIC

4.4 Power Management Unit

As already described in chapter 3, the power management unit (PMU)
provides the required supply voltages to the ASIC. In addition to this, the
implemented PMU controls the start-up and provides the reference voltages
and currents. The concept of the implementation follows a slightly different
approach as in chapter 3. It is necessary since the application of the ASIC
has no guaranteed steep curve of Vin but instead a very slow ramp during
sunrise. An UVLO supplied by a pre LDO constantly monitors the input
and supply voltages. An additional pre bandgap reference generates a first
reference voltage and current which activate a 5 V LDO. This supplies the
main bandgap reference which provides the reference voltage and current
to the other LDOs starting these. The possibly resulting cross currents
have to be endured. This concept allows for a robust start-up since the
LDOs can use the pre supply and in any case have a reference current and
voltage. However, it comes at the cost of a constantly drawn current which
has to be kept low.
Figure 4.4 shows the block diagram of the PMU. It is supplied by Vin ,
the main supply of the ASIC. The UVLO generates a power good (PG)
signal which indicates that all supplies are available. This signal can be
used by the digital part to determine that the ASIC can start operation.
To enable a proper functioning during the start-up, a pre LDO generates
V4.5V,pre . Moreover, a pre bandgap reference generates Vbg,aux and Iref ,pre .
The more accurate references are generated by the 1.2 V bandgap reference
out of V5V,ana . The PMU features three main LDOs, the
• V5V,ana LDO
• V5V,drv LDO and
• V1.8V LDO.
An additional auxiliary pseudo LDO is implemented to provide multiple
decoupled supply voltages V4.2V,aux and V5.6V,aux . Despite the main boost
converter, no further switched DC-DC converter is implemented. Since all
supplies have a relatively low power demand, the benefit of an additional
buck converter does not compensate the cost for the external inductance.

The V5V,ana LDO is enabled by the temporary reference current Iref ,pre . It
is only internally buffered and supplies noise sensitive circuits which pull

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 4 Energy Harvesting ASIC

Vin Iref,pre
UVLO V1.8V,dig
PG
V1.8V,ana
LDO
pre V4.5V,pre LDO
BG Vbg,aux 1.8V
pre Iref,pre
1.2V V4.5V,pre
Bandgap V4.5V,pre
Iref,pre V5V,drv
LDO
V5V,ana
LDO 5V DRV
5V ANA
Iref
×n

×n

AUX V4.2V,aux,n
LDO V5.6V,aux

Figure 4.4: Block diagram of the PMU.

a continuous current. V5V,drv is intended for pulsed loads as the output

drivers and considered very noisy. It is externally buffered to suppress
low frequency noise. Nevertheless, voltage peaks caused by the bond wire
inductance will occur at every switching of the output driver. The V1.8V
LDO generates the externally buffered V1.8V . This voltage is split into a
noisy V1.8V,dig and a calm V1.8V,ana , which are decoupled by the bond wire
inductances. V1.8V,dig supplies digital circuits and has voltage peaks dur-
ing the switching current pulses of these circuits. The less noisy V1.8V,ana
supplies more noise sensitive circuits which are only affected by the remain-
ing switching noise on V1.8V which is strongly suppressed by the external
capacitance. For an even better decoupling, an optional external inductor
can be applied between the buffering capacitors. The V4.2V,aux voltages
have high variations in the absolute voltages and a poor load regulation.
They are intended for circuits, which have high demands to supply noise
but would introduce too much additional noise to V5V,ana . Therefore, they
have to be tolerant for the resulting supply voltage uncertainty and the
self induced noise. V5.6V,aux is required in the push pull output driver of
the MPPT controlling Vg,meas to drive it up to 5 V which is described in
section 4.6.2.

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 4 Energy Harvesting ASIC

4.4.1 UVLO

The UVLO is shown in figure 4.5 and features three main parts:
• pre starting LDO
• pre starting bandgap reference
• voltage monitoring
At the start-up, the pre starting LDO generates a voltage of roughly
V4.5V,pre = 4.5 V. At the rise of Vin , the current through the diodes D
causes a rise of Vint and VLDO,pre . Rsu,1 and Rsu,2 limit the current. The
current mirror M1-M3 splits the current flowing through Rsu,2 into the
three branches according to the mirror ratio. Thereby OP1 and OP2 are
reliably biased. M4 is interconnected as a source follower which forces
V4.5V,pre to follow VLDO,pre [68, p.136 ff.]. OP1 drives the gate of M5
which is able to draw current from VLDO,pre . This reduces VLDO,pre and
thus enables the control of V4.5V,pre . The increase of VLDO,pre activates
M4 and V4.5V,pre is generated to a voltage based on the diodes D and Vin .
This voltage is potentially higher than the target voltage and requires the
operation of OP1 to avoid damage. Before VLDO,pre exceeds a tolerable
voltage, it is sufficient to activate the pre starting bandgap reference which
provides reference voltages to the pre starting LDO and other circuits. The
output of the bandgap reference core Vbg,pre is buffered by OP3 which pro-
vides Vbg,aux to the ASIC. OP3 is supplied by V4.5V,pre . To have a buffered
reference voltage during the start-up, OP2 which is supplied out of Vint , is
added and generates Vref ,pre . With this reference voltage Vref ,pre , OP1 has
an early reference voltage and can start control activating M5. However,
M5 is only allowed to get active when OP1 sees a reference voltage. Other-
wise it would try to set V4.5V,pre to zero or the currently available Vref ,pre
inhibiting the start-up.
The pre starting bandgap reference is not meant to be used as the main
reference. It is optimized to require a small current and therefore shows
much more noise then the main bandgap reference, which is described in
section 4.4.2. Nevertheless Vbg,aux is used as a reference before the main
bandgap reference has a stable output voltage. The implementation is a
standard bandgap reference core which utilizes a 1 to 8 bipolar transistor
pair provided by the technology [152]. The DC current is designed to be
very small to enable the operation at as low available power from the PV
cell, and thus as low irradiance, as possible.

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 4 Energy Harvesting ASIC

Vin
Rsu,1 VLDO,pre
M4
Rsu,2 Vint

M1 M2 M3

Iref,pre1
D Vfb R1
M5 R2
OP1 V4.5V,pre
V4.5V,pre
Vsup,n
pre starting LDO Iref,pre2
OP2 Vbg,pre
PG
voltage
Vref,pre OP3 CMP monitoring

core pre bandgap Vbg,aux

Figure 4.5: Block diagram of the UVLO.

The voltage monitoring compares the different on-chip supplies Vsup,n and
the main reference voltage to Vbg,aux . Therefore the voltages are accord-
ingly scaled by resistors. The comparators are implemented as clamped
push-pull comparators as discussed in [4, p.466]. A hysteresis is added
as shown in [4, p.476]. This allows to provide stable and non bouncing
status signals for all supply voltages. The PG signal is then the logical
AND conjunction of all status signals. Simulations show a good behaviour
and stability to process variations. The overall current consumption of the
UVLO is about 16 µA including the voltage reference and monitoring.

4.4.2 Bandgap Reference

The main bandgap reference provides a temperature stabilised low noise

reference voltage Vref,1.2V = 1.2 V and the necessary reference currents
Iref ,n to the ASIC. The schematic of the bandgap reference is shown in fig-
ure 4.6. The core is supplied by V5V,ana and generates the unbuffered weak
reference voltage Vbg,1.2 V . OP1 buffers this reference and generates Vref ,int .
An analogue multiplexer (MUX), feeds either this Vref ,int or Vref,aux from
the UVLO to Vref,1.2V based on the PG signal. Thereby Vref,1.2V has an
acceptable reference voltage at the start-up and an accurate reference when
the power supply is available.

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 4 Energy Harvesting ASIC

V4.5V,pre
V5V,ana M2 M3

Vbg,1.2V OP2
M1 Current
Iref,n
OP1 Iref Bench
PG
core RV2I
Vref,int
Vref,1.2V
Vref,aux

Figure 4.6: Block diagram of the bandgap reference.

A VI converter transforms the reference Vbg,1.2 V to a proportional refer-

ence current Iref . This is done by OP2 which controls the voltage across
RV 2I to Vbg,1.2 V . Since RV 2I is a temperature compensated resistor, the
resulting current Iref is very stable to temperature changes. However, it
still is influenced by production tolerances. For this, a trimming capabil-
ity is implemented, which allows to reduce this error. Iref is conducted
through M1 and mirrored by M2 and M3 to the current bench. This cur-
rent is transformed to the according supply voltages, generating the re-
quired reference currents Iref ,n , which are then provided to the circuitry.
Since V4.5V,pre supplies M2 and M3, these currents are available during
the start-up. Thereby the current bench is able to generate currents very
early. The bandgap reference uses a current of 25 µA, neglecting the output
reference currents.

4.4.3 LDO 1.8 V

The 1.8 V LDO generates V1.8V which is split into V1.8V,ana and V1.8V,dig
as described in section 4.4 [146]. The schematic is shown in figure 4.7. It
features a start-up detection as described in section 3.7.3. The bond wire
inductances Lbond decouple the on-chip supplies from the external voltage.
In contrast to that implementation, the start-up and the main feedback
loop are altered. In the main feedback loop, the output of the OP drives
the 1.8 V rated transistor M4 which is protected against high Vds by M3.
Thereby, M4 is slightly faster and can be matched to the output transistors
of the OP.
The start-up circuit utilizes Iref,pre1 , the reference current from the UVLO,

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start-up circuit LDO

Vin

M8 M7 M2 M1
V1.8V,dig Lbond
Iref,pre1
Vg V1.8V,ana Lbond
M5 M3
D2 R1 Cbuf
VSO
M6
R3
D1 M4
Vref,1.2V
R2

V1.8V,ana

M11
VSO Iref,pre2

M10 M9
start-up
detection

Figure 4.7: Block diagram of the 1.8 V LDO.

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 4 Energy Harvesting ASIC

to overcome the usage of the leakage current. The current mirror M7, M8
mirrors Iref,pre1 into the node Vg , where D1 and D2 cause a voltage which
activates M5. This replaces the utilization of a leakage current, as shown
in figure 3.39, by a well defined and temperature stable reference current.
The current limitation of the introduced start-up current is now limited
by R3 , which is located at the source of M5. Thereby the voltage across
R3 is approximately the same as across D1 when M5 and D2 are carefully
matched and depending less on Vin .
The start-up detection is not changed in comparison to figure 3.41. M11
starts to conduct after the overdrive of the OP. Thereby, VSO rises and
switches off the start-up circuit. The main feedback loop is limited by
the gate-source voltage of M3 which has to exceed Vth . To prevent a shut
down of the start-up circuit before M3 allows a current in its branch, M6 is
matched to M3 and designed to have a higher Vth . The constant currents
Iref,pre1,2 keep continuously running after the start-up. Therefore each
draws 200 nA which can be tolerated.
The current efficiency of the 1.8 V LDO strongly depends an the load cur-
rent. Without a load, a current of about 8 µA is required. However, this
is increased with higher load currents since then, a higher current through
M2-4 is necessary. At a load current of 1 mA, the current efficiency is above
97 % and at the maximum current of 10 mA, it is approximately 98.7 %.

4.4.4 LDO 5 V Drive

The LDO for V5V,drv is shown in figure 4.8. It features a basic structure
similar to the core for the LDO depicted in figure 3.15. The main difference
is that M3 from the core LDO is split into M3 and M4 with an added Rlim .
This is done to protect the 5 V transistor M4 against high voltages and to
utilize the better performance of the symmetric 5 V MOSFETs. Rlim is
introduced to limit the peak currents in the pass transistor M1. Otherwise
very high current peaks would occur during the voltage drops caused by
the switching of the output stage.
The LDO features another concept for the start-up. Before V5V,drv is avail-
able, the OP is supplied via M5 which is controlled by V4.5V,pre and in-
terconnected as a source follower [68, p.136 ff.]. Thereby the OP has a
sufficient voltage to operate at the start-up. After V5V,drv is high enough,
a diode conducts current from this voltage to the OP.

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 4 Energy Harvesting ASIC

Vin

M2 M1

V5V,drv
V4.5V,pre M5 M3

Cbuf
Rlim R1
VLDO,sup

M4
Vref,1.2V
R2

Figure 4.8: Block diagram of the 5 V LDO for the output drivers.

The control circuit requires a constant current of 3.6 µA for the feedback
divider and the OP. At high output currents, the current efficiency is lim-
ited by the mirroring ratio of M2 and M1. At the expected load of ≈ 5 mA
for normal operation at CCM and fsw = 300 kHz, the current efficiency
gets up to 99.2 %.

4.4.5 LDO 5 V Analogue

Different supply noise sensitive circuits are supplied by V5V,ana . In par-

ticular, the error amplifier, the current sense amplifier, the slope compen-
sation and the ramp emulation from the boost converter control require
a good power supply rejection ratio (PSRR) [84]. Therefore, the LDO
which generates V5V,ana needs to provide a high PSRR. As a compromise,
the attached circuits have to drain a very constant current which does
not quickly change. Otherwise, the noise introduced by the bond wire in-
ductance would significantly reduce the achieved PSRR. Without quickly
changing load currents, the requirements to the size of the buffering capac-
itance is heavily reduced. This allows the use of a solely internal buffering
capacitor which also reduces the influence of introduced noise through the
coupling of adjacent bond wires or off-chip.
Figure 4.9 shows the schematic of the implemented LDO. It combines three

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 4 Energy Harvesting ASIC

cascaded LDOs to achieve a high PSRR. All three stages have a similar
structure which equals the V5V,drv LDO from section 4.4.4. The first pre-
liminary LDO transfers Vin reduces Vin to V6.5 V,prereg ≈ 6.5 V via the pass
transistor M6. This enables the use of better performing 8 V MOSFETs
for M1 and M5. V6.5 V,prereg is further reduced by the second preliminary
LDO to V6 V,prereg ≈ 6 V. This LDO provides a PSRR enhancement by
the additional active stage. Finally the main LDO controls the last pass
transistor M1 and thus the absolute voltage of V5V,ana . For the start-up,
the OPs are supplied via M7, similar to the V5V,drv LDO from section 4.4.4.

M6 V6.5V,prereg M5 V6V,prereg M1
Vin

M9 M8 M2

V4.5V,pre M7 M3 V5V,ana

Rlim1 R1 Rlim2 R3 Rlim3 R5

VLDO,sup

Vref,1.2V Vref,1.2V M4
Vref,1.2V
R2 R4 R6

LDO pre1 LDO pre2 LDO main

Figure 4.9: Block diagram of the 5 V LDO for constant loads.

Without a load, the LDO drains 27.6 µA from the supply to power the
feedback loops. At the maximum output current of 400 µA, the current
400 µA
efficiency is still only ηi = 537 µA = 74.4 %. This low value results from
the kaskading of three stages and the small mirror ratios of M6 M9 = 20,
M5 M1
M8 = 10 and M2 = 10 which are selected for a better PSRR performance.
However, these losses are tolerabel since the absolute power losses are small
in comparison to the losses of the complete ASIC.
Figure 4.10 shows the PSRR provided by the LDO at its output [84]. The
PSRR for three different load currents after each of the stages of the LDO
is shown. It is clearly visible that the PSRR is above the lower orange line

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 4 Energy Harvesting ASIC

at 60 dB for all frequencies. Thus, the LDO is able to provide a P SRR >
60 dB for a large output current range as required by the supplied circuits.

250
Iload = 10 µA
Iload = 100 µA
200 V6 V,prereg Iload = 400 µA
PSRR [dB]

150

V6.5 V,prereg
100 V5 V,ana

50

0 0
10 101 102 103 104 105 106 107 108 109
frequency [Hz]

Figure 4.10: Achieved PSRR at different load currents.

The graph shows how each of the stages adds PSRR. The first preliminary
LDO provides a good PSRR for DC variations but only a small PSRR at
higher frequencies. The second LDO creates similar additional PSRR at all
frequencies. Finally, the main LDO only adds PSRR at higher frequencies
around 2 MHz.
Another characteristic, the two different mechanisms achieving the PSRR,
is also visible in the graph. At high frequencies the PSRR is provided by
the buffering capacitance which is approximately Cbuf ≈ 279 pF. These ca-
pacitances have a low equivalent series resistance (ESR) due to the on-chip
implementation which offers good performance up to very high frequencies.
At low frequencies the PSRR is achieved by the control loop performance of
the LDO which adjusts V5V,ana according to the deviation from the target
voltage. At medium frequencies, these two mechanisms superimpose each
other. This results in the minimum of the PSRR at medium frequencies,
where both effects only partly have an effect.

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4.4.6 Auxiliary LDO

The V5V,ana LDO is only able to supply loads which drain a constant and
continuous current. Otherwise, the backlash to the supply voltage would
be too big because of the small buffering capacitance and limited band-
width of the LDO control. However, some circuits require a good PSRR
and especially no interference from other circuits, even if they have vari-
able and pulsed loads. To avoid such interference with and disturbance of
other circuits on the same supply, an effective decoupling is necessary. One
possibility would be to use an LDO for each of these circuits. Since this
would require much additional space, another principle was implemented
in the ASIC.
If the circuit to supply is not depending to the absolute value of the supply
voltage, an open loop generation of Vsup is possible. This can be done
by a source follower as shown in figure 4.11 [68, p.136 ff.]. The cascode
transistor M2 increases the PSRR and allows the use of a 5 V transistor for
M1 which has a better performance than the high voltage equivalent. The
current source Ibias provides the minimum current load to avoid a poor
biased output if there is no output current.

Vin

Vbias M2

V5V,ana M1

V4.2V,aux
Ibias

Figure 4.11: Source follower principle of the auxiliary LDO.

This circuit generates an output voltage which is V4.2V,aux ≈ 4.2 V in the

nominal case. Due to the lack of a feedback loop, this voltage highly de-
pends on the temperature, process corners and the load current and varies
between 3.9 V < V4.2V,aux < 4.6 V. In this values, the uncertainty of
V5V,ana which has to be added for the absolute value, is neglected. The
load regulation is poor but since typically only a single functional block is

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 4 Energy Harvesting ASIC

supplied with V4.2V,aux , this self disturbance can be considered during the
design process.
This topology allows an efficient generation of the auxiliary supply voltage
V4.2V,aux . For proper functioning, it requires the bias voltage and current.
These are generated as shown in the schematic of the full auxiliary LDO
in figure 4.12. It features n parallel output stages from figure 4.11, which
are all biased from the same bias voltages. In addition to this, an auxiliary
voltage V5.6V,aux is generated with a similar principle. The input reference
current Iref is mirrored into three different branches by M1-3 and M14.
The biasing for the cascode in the V4.2V,aux generation is provided by M13
which is biased with a current and a source voltage at the same voltage as
V5V,ana . Hereby, M13 is the same type as and matched to M16 to provide a
better reference voltage and increase PSRR. To reduce the coupling of Vin
to V5V,ana , the source of M13 is not directly connected to V5V,ana . Instead,
the voltage is duplicated with the cascoded PMOS source follower M9-12.
The bias current of M13 is the by M3-8, twice mirrored reference current
Iref . Whith this double mirroring against Vin , the tolerance against a drain
source breakdown has to be carefully considered. Therefore, M4, M5 and
M8 are implemented as high voltage MOSFETs.
The PSRR of V4.2V,aux depends on the buffering capacitance, the load,
supply voltages, temperature and CMOS corner. The buffering capacitance
of each output stage can be individually adapted for each circuit. Thereby
the PSRR can be tuned differently depending on the specific requirements.
The buffering capacitance of the DM DACs is selected to ≈ 24 pF. Here, in
the nominal case a P SRR = 60 dB is achieved. Corner simulations show a
P SRR > 49 dB for all frequencies below 20 MHz and all occurring process
corners.
The additional voltage V5.6V,aux ≈ 5.6 V is generated for the MEAS DAC,
described in section 4.6.2. This DAC has an output voltage driven by a
push-pull stage and has to be able to go up to almost 5 V. Thus, an-
other V4.2V,aux would not be sufficient and V5V,ana can not be used due
to the load. In addition to this, a supply voltage slightly higher than 5 V
is desirable to leave some headroom for the output stage. This additional
voltage V5.6V,aux is generated by M17-21. The reference current which
is mirrored by the high voltage current mirror from the biasing by M19
and M20 is conducted to M17 and M18. These two transistors are con-
nected as diodes. M21 which is connected as source follower then generates
V5.6V,aux out of Vin . Due to the matching of M21 and M18, the voltage

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Vin
V4.2V,aux
biasing M7 M6 generation M20

M8 M5 M19

M16 M21
M18 V5.6V,aux
×n
M13 M17
V5V,ana V5.6V,aux
generation
M12 M10 M4 ×n
M15 V4.2V,aux,m
M11 M9

Iref
M14
M1 M2 M3 ×n

Figure 4.12: Implementation of the auxiliary LDO.

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 4 Energy Harvesting ASIC

of V5.6V,aux equals the drain potential of M17 which is one MOS diode
voltage higher then V5V,ana . This circuit generates V5.6V,aux in a range of
5.5 V < V5.6V,aux < 6.2 V which is sufficient for the MEAS DAC.

4.5 Implemented MPPT Concept

In section 4.1, a combination of the InCond and RCC technique was se-
lected as the basic MPPT principle. However, the implementation of the
correlation and especially the differentiator needs to be clarified which is
done in the following section. After this, adaptions for an integrated im-
plementation are discussed in section 4.5.2. Finally the conversion to the
MPP of the selected implementation is shown in section 4.5.3.

4.5.1 Principle and Adaptions

For an implementation, the selected MPPT technique in figure 4.1 needs

some clarification. The use of an artificial imposed perturbation requires
a sampling of the state of the PV cell, since the wanted signal is now the
perturbation. In contrast to the basic RCC technique, the input current
and voltage ripple are unwanted noise for the MPPT. This sampling has
to be synchronized to the switching of the boost converter.
The preprocessing can directly be implemented with commonly used cir-
cuits. Vin ≈ VPV can be used because the voltage drop across Rvar is
designed to be very small. The implementation of the correlation and espe-
cially the derivation and the sign function is shown in figure 4.13. A delta
modulator with a clocked comparator is utilized to perform the deriva-
tion [6, 7, 52]. In addition to the derivation, the delta modulator gives
a discretised pulse density modulation (PDM) bitstream at Vsample . This
bitstream can be evaluated very well by an MPPT control like shown in
figure 4.1. The conversion of the concept is shown in section 4.5.3.
This system is very well suited for a discrete implementation on a PCB.
Only a few cheap components are required to achieve a robust MPPT with
a hysteresis control [6, 7]. However, the integration into an ASIC offers ad-
ditional flexibility and requires some adaptions due to the time constants.
The latter is necessary since the low-pass filter in the preprocessing typi-
cally has a time constant in the order of ˜10 − 100 ms. Such high timing

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 4 Energy Harvesting ASIC

Vin ≈ VPV Boost

Converter

Vctrl Vout

VPV delta modulator

Vint ∫
-Vmeas,I Vsample MPPT
CLK CTRL
Vin
Rvar R1

-1 Vmeas,V

R2

preprocessing MPPT

Figure 4.13: System diagram of the selected MPPT.

constants are very challenging for integrated circuits and require a big on-
chip area [19, 57, 117]. The use of DACs which are able to continuously
drive their output can overcome this limitation. In combination with the
sampling, this allows for a flexible MPPT which can operate from very
low up to very high time constants. The higher flexibility allows for more
complex boost converter control techniques as described in section 4.3. In
addition to this, the MPPT control can be implemented as a digital circuit.
This allows for a better tracking and higher efficiencies for a wide range of
input powers and irradiance conditions.

4.5.2 Implementation and MPPT Procedure

Figure 4.14 shows the block diagram of the implemented MPPT [96]. The
preprocessing and the delta modulator are implemented utilizing DACs
as discussed in the previous chapter. Again, Vin ≈ VPV can be used
because the on resistance of the MOSFET is designed to be very small.
The DAC of the preprocessing, the MEAS DAC, directly controls the gate
of the external MOSFET. A control logic steers the MEAS DAC to the
desired state. The analogue inversion of Vmeas,V and the OP of the pre-
processing are implemented with R3 , R4 and the MEAS comparator C1.

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R1 = 555 kΩ and R2 = 2.22 kΩ resulting in an input voltage scaling of

1
α = 251 . This results in a voltage range of 29.9 mV < Vmeas,V < 71.7 mV
considering the specifications from table 4.3. With R3 = R4 ≫ R2 follows
Vcmp = Vmeas,V − Vmeas,I . Adjusting Vcmp to zero, which is done by C1 in
combination with the logic, the MEAS DAC and the MOSFET, results in
Vmeas,V = Vmeas,I and thus the desired inversion.

Vin ≈ VPV Boost

Converter

Vout
delta modulator
VPV
Vint DM
DAC
-Vmeas,I C2
MPPT CTRL
Logic
preprocessing Vin Vsample SDM CTRL DAC
R1
R3 Vcmp R4 Vmeas,V

MEAS
Logic R2
DAC
C1
MPPT

Figure 4.14: Implementation of the MPPT.

The feedback of the delta modulator is implemented using a DAC which is

called the the DM DAC. It is controlled by synthesized logic which evaluates
the result of DM comparator C2 comparing Vint − Vmeas,I to Vmeas,V . The
logic performs the integration and stepwise adjusts the DM DAC until the
input difference of C2 gets minimal. With a sufficient resolution of the DM
DAC, this leads to Vint ≈ Vmeas,V + Vmeas,I . From the linear behaviour of
the DM DAC follows SDM ∝ Vint which can be used by the MPPT control
to find the MPP. The CTRL DAC is the link between the MPPT and the
boost converter. As shown in figure 4.3, it drains a current from Vfb of the
boost converter and thereby modifies Vin .
Due to the sampling of the comparators C1 and C2, interference especially
from switching noise can occur. To minimize these effects, the timing
of the synchronized sampling is carefully aligned to the switching of the
boost converter. Thereby, sampling takes place in a moment with similar
conditions each switching cycle. In the best case, it always takes place in
a moment, where the absence of switching noise is guaranteed. Since this
is the case shortly before the end of the minimum on-time of the boost
converter, this is the ideal moment for the sampling. In this way, the

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noise due to interference and the influence of the inherent ripple of the
PV cell is minimized. This switching limits the sampling frequency of the
comparators to fsw . Since the control bandwidth of the boost converter
and the MPPT tracking speed are much lower then fsw , this does not
significantly affect the tracking performance.

MPPT Digital Control

The implemented digital control consolidates the adjustment and the delta
modulator logic as well as the MPPT control. The tracking procedure
is illustrated in figure 4.15. It can be split into the preparation and the
observation. Before the perturbation is applied to VPV , the gate volt-
age of the MOSFET and thus the resistance of the variable resistor Rvar
is adjusted. Thereby, Vmeas,I = Vmeas,V is achieved and then the DM
DAC is pre-adjusted so the delta modulator starts at an balanced input
level. The corresponding value of SDM is stored by the MPPT control as
SDM,−1 = SDM for the later evaluation. After the preparatory adjust-
ments are finished, the MPPT control perturbs VPV by V∆ . The value of
the perturbing voltage V∆ can be constant or adapted dynamically during
the operation as described in section 4.6.3. The boost converter control
adjusts VPV to the new value and the DM DAC tracks the relative shift
between Vmeas,I and Vmeas,V . After a number of switching cycles, after
which VPV achieved the targeted voltage and the delta modulator is bal-
anced at the input, the shift of SDM is evaluated. Therefore, the difference
of the stored to the final value Sdiff = SDM − SDM,−1 is correlated to the
applied perturbation. Based on the formula 2.9 of the InCond algorithm,
the result can be used to find the MPPT by evaluating
⎧
⎪ = MPP when {︃
⎪ Sdiff = 0
Sdiff > 0 and V∆ > 0
⎪
⎪
< MPP when
⎨
VP V {︃ Sdiff < 0 and V∆ < 0 (4.3)
S < 0 and V > 0
⎪
diff ∆
⎪
⎩ > MPP when
⎪
⎪
Sdiff > 0 and V∆ < 0

The derivation of this condition can be found in the next section. More
details on the implemented algorithm are described in section 4.6.3.
There is a correlation of Sdiff and the distance from the MPP, which follows
from the flattening of the VI characteristic at the MPPT. This is used
in the implemented algorithm to add a proportional P component which

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start

adjust
Vmeas,I = Vmeas,V

pre adjust
DM DAC

SDM,-1 = SDM
perturbVPV

track
DM DAC

evaluate
SDM – SDM-1

Figure 4.15: Flow chart of the MPPT procedure.

reduces the convergence time. Since the size of the perturbation step has a
direct influence to the value too, this component is selected conservatively
to avoid instabilities. Simulations show a good and reliable performance
of this even if no mathematical derivation is shown. To avoid limit cycle
oscillation the algorithm changes the perturbation direction in the case
where Sdiff = 0 [139]. Thereby, a controlled minimum perturbation and
fluctuation is maintained when the measurement resolution is not high
enough to determine the MPP more accurately.

4.5.3 Convergence

To show the convergence of the implemented MPPT to the MPP, first the
continuous system is examined. Subsequently the transition to the actually
implemented time discrete system is performed. Due to the similarity to
the RCC the convergence is shown, based on the calculations for the RCC
technique in section 2.3.4. After this, the input to the MPPT control is
calculated to derive the consequences for the specific implementation of the
code despite the abstract integration which is assumed for the analysis of
the convergence.
The value continuous description of the system is shown in figure 4.13.

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In contrast to the basic RCC technique, this system utilizes an artificial

imposed perturbation. Because of the synchronous sampling, the inherent
ripple of the PV cell is not visible to the MPPT. Thus, only the perturbation
influences the measured signal. As previously shown in equation 2.23, the
preprocessing adjusts Rvar to
VPV
Rvar = α · (4.4)
IPV

with α = R1R+R
2
2
. The feedback loop of the delta modulator controls the
input of the comparator to zero [52]. Neglecting the limitations of the
comparator, this leads to

Vmeas,V = Vint − Vmeas,I (4.5)

and Vint = Vmeas,V + Vmeas,I (4.6)

and considering the integrator to

d
Vsample = β · (Vmeas,V + Vmeas,I ) (4.7)
dt
with the constant β which depends on the integrator. This equals to Vcorr
from equation 2.26 [96].
The comparator is limited in speed and output voltage. In particular, the
comparator of a delta modulator is operated with a clock sampling the
input and the output voltage is limited to the analogue representations of
logical low and logical high. Given that the sampling speed and the volt-
ages are sufficient to track the input signal, Vsample is a PDM bitstream
and equation 4.7 holds for the average of this signal. Thus, the calculations
following equation 2.26 apply to the implementation with a delta modula-
tor. From this, the convergence of the MPPT to the MPP can be achieved
when Vcorr = Vsample · β1 is correlated to the perturbation V∆ and the result
is integrated.
The implementation of the MPPT shown in figure 4.14 is directly derived
from the system in figure 4.13. Since the stability of the system is shown,
the implementation of this is also stable, in case that the DACs have a
sufficient accuracy. However, the implementation of the control in the
digital part of the ASIC offers additional opportunities to optimization.
Therefore it is necessary to know the implications of the result of Vsample
and especially SDM from figure 4.14. This is derived in the following, and

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thereby showing the convergence in another way.

The sampling and the introduced perturbation lead to the InCond tech-
nique. The basic condition is
⎧
⎨ = 0 when VPV = VMPP
GP V + dGP V > 0 when VPV < VMPP (4.8)
< 0 when VPV > VMPP
⎩

as shown in equation 2.14. The target of the MPPT is to evaluate this

condition. From the schematic in figure 4.14 and the MPPT procedure
follows that Rvar is set according to equation 4.4 at the beginning of each
cycle. From equation 2.25, Vmeas,I = Rvar · IPV is known. Following
equation 4.6, the pre adjustment of the DM DAC results in

Vint,−1 = Vmeas,V ,−1 + Vmeas,I ,−1 (4.9)

with the index −1 to mark the pre adjusted values. It is directly propor-
tional to the control word SDM , measured in least significant bit (LSB),
giving

SDM,−1 = γ · (Vmeas,V ,−1 + Vmeas,I ,−1 ) (4.10)

= γ · (α · Vpv,−1 + Rvar · Ipv,−1 ) (4.11)

with a constant coefficient of proportionality of unit [γ] = LSB

V . After this,
VPV is perturbed by V∆ gaining VPV ,0 = VP V,−1 + V∆ . From the resulting
slope of VPV , which is mainly determined by the boost converter control,
follows a change of Vmeas,V and Vmeas,I . The difference of the is tracked
by the delta-modulator giving

SDM ,0 = γ · (Vmeas,V ,0 + Vmeas,I ,0 ) (4.12)

= γ · (α · VPV ,0 + Rvar · IPV ,0 ) (4.13)
= γ · (α · (VPV ,−1 + V∆ + Rvar · (IPV ,−1 + I∆ )) (4.14)

with Vmeas,V ,0 = αVPV ,0 = α · (VP V,−1 + V∆ ) and IPV ,0 = IP V,−1 + I∆ .

The difference of the two states Sdiff = SDM,0 − SDM,−1 results in

Sdiff = SDM − SDM,−1 = γ · (α · V∆ + Rvar · I∆ ) (4.15)

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and with Rvar from equation 4.4 follows

VPV
Sdiff = γ · α · (V∆ + I∆ · ) (4.16)
IPV
Since α > 0 and γ > 0 is always true, the sign of Sdiff only depends on the
remaining fraction. With VPV > 0 and IPV > 0 the evaluation of the sign
function yields in
(︃ )︃
VPV
sign (Sdiff ) = sign V∆ + I∆ · (4.17)
IPV
(︃ )︃
IPV
= sign V∆ · + I∆ (4.18)
VPV
(︃ )︃
IPV I∆
= sign + · sign (V∆ ) (4.19)
VPV V∆
= sign (GP V + GP V,∆ ) · sign (V∆ ) (4.20)

where sign (V∆ ) is known from the induced perturbation. Since V∆ ̸= 0,

rearranging results in

sign (G + G∆ ) = sign (Sdiff ) · sign (V∆ ) (4.21)

which can be set into the basic InCond condition. Using this, the basic
InCond condition can be evaluated leading to equation 4.3
⎧
⎪ = MPP when {︃
⎪ Sdiff = 0
Sdiff > 0 and V∆ > 0
⎪
⎪
< MPP when
⎨
VP V {︃ Sdiff < 0 and V∆ < 0 (4.22)
S < 0 and V > 0
⎪
diff ∆
⎪
⎩ > MPP when
⎪
⎪
Sdiff > 0 and V∆ < 0

4.5.4 Design requirements of the DACs and Comparators

Because of the working principle of the MPPT, the analogue circuits do

not need to be ideal in every aspect. Instead, the system very well can
tolerate a couple of non idealities and requires a very accurate behaviour
only from a few functional blocks. Knowing for each functional block,
which specification requires a high ideality and which specification can be
relaxed greatly reduces the implementation effort. Moreover, the current

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consumption can be reduced, since a high accuracy often causes additional

power consumption.
Considering the preprocessing, the accuracy of the MEAS DAC and the
comparator C1 are examined. The function of the preprocessing is to
adjust Vmeas,I to Vmeas,V . Following equations 4.16 and 4.4, this ad-
justment brings influence of the large signal values of the PV cell to the
measurement output signal Sdiff . An error in this adjustment directly
leads to a wrong MPPT. Simulations show that an adjustment accuracy
of |Vmeas,V − Vmeas,I | < 300 µV results in a sufficient performance of the
MPPT. An offset error of C1 leads to

Vmeas,I = −Vmeas,V − 2Voff (4.23)

with the offset voltage of C1 Voff . This leads to high requirements to

the input voltage offset of comparator C1 to minimize the misadjustment.
Since the output is sampled by the digital part, a latch can be used for the
implementation [94]. The propagation delay should be small enough to
read C1 out in the next clock cycle.
The MEAS DAC adjusts the gate of the sensing MOSFET according to the
comparison of C1. It is operated in a closed loop. Therefore the absolute
output value is uncritical and can be unknown to the control. However, it
still has to get high enough to drive the MOSFET. Therefore the output
range should cover output voltages up to V5V . The main focus is the control
needing to be able to reliably adjust the gate voltage. This leads to the
need of a high resolution of the MEAS DAC with a monotonic output.
However, known non-monotony can be overcome e.g. when a DAC with
overlapping output states is used. Another possible implementation is the
cascading of two or more DACs with overlapping ranges. Simulations show
that an effective resolution of the MEAS DAC of 12 bit enables the desired
adjustment accuracy.
The delta modulator adjusts the DM DAC based on the output of com-
parator C2 so the difference between the inputs of C2 is brought to zero.
As output signal, only the change of the input signal difference of SDM is
used, which follows from the procedure in section 4.5.2. Due to this, the
absolute input offset voltage of comparator C2 is not critical, as illustrated
in figure 4.16. Because of the integrator, Vout is controlled to Vout = 0 V.

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Following this

Vop,− = Vref − Voff (4.24)

holds and Vop,− = Vin + Vint follows from the figure. This leads to

Vint = Vref − Vin − Voff (4.25)

and SDM ∝ Vref − Vin − Voff (4.26)

When the difference between two of these signals is taken, the offset is
cancelled and only the wanted difference remains. Therefore and because
of the comparison very close to GND, a distinct input offset voltage is
even desirable. This is mainly to avoid negative on-chip voltages which
otherwise can occur at the negative input of C2. Another advantage is that
the common-mode voltage is at a higher level, where a comparator works
better. A last reason for a wanted input offset voltage is given when the
DM DAC can only increase Vop,− . In this case, a situation can occur where
the DM DAC is not able to reduce Vop,− far enough, so the delta-modulator
is not able to track the input any more. Similar to C1, comparator C2 is
sampled in the digital part, so the propagation delay should be sufficient
for a readout in the next clock cycle.

Vint / SDM
∫
Vop-
Vin
Voff Vout
Vref

Figure 4.16: A simple closed loop with an OP and an integrator.

The DM DAC is controlled by the digital part and provides the possibility
to change the negative input of comparator C2. Due to the functioning
principle of the MPPT, the absolute output value is not important, as long
as the DM DAC is able to track the changes of Vmeas,I . To avoid adjust-
ments into an unwanted direction, monotony is strictly required during the
tracking of the input. For the pre adjustment a known non-monotony can
be tolerated, similar to the MEAS DAC. From simulations follows that a
LSB step of the DM DAC of VLSB ≈ 50 µV is desirable. A higher LSB,
which corresponds to a lower resolution, results in a degrading tracking

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efficiency especially at lower input powers. To leverage Vmeas,I to Vmeas,V ,

an input range of Vrng = 2 · Vmeas,V is necessary. Considering a potential
offset voltage of C2, the range is extended to Vrng = 2 · Vmeas,V − Voff .
However, this is only necessary for the pre adjustment of the DM DAC.
The accurate tracking only needs to cover a range of Vrng,track ≈ ±1 mV,
which was evaluated by simulations.
The CTRL DAC is the link between the MPPT and the boost converter.
It introduces a current into the feedback node of the boost converter. Since
this node is sensitive to noise, the CTRL DAC should have a decent PSRR
and a low noise. Since it in principle is in a closed loop of the MPPT routine,
the accuracy regarding the absolute output current is not critical. However,
a strict monotony is necessary, since the MPPT algorithm relies on the
knowledge of the direction of the perturbation. To obtain the resolution
of the CTRL DAC, the feedback divider of the boost converter has to be
considered. According to equation 4.2, the LSB current of the CTRL DAC
Ilsb can be calculated out of the minimal desired input voltage change.
From the targeted static tracking efficiency ηmppt,stat of 99.9 % follows a
maximal allowed static offset Voff ≈ 120 mV from the MPP [127]. In theory
this can be achieved with a step size of 240 mV but since this ripple comes
in addition to the inherent input voltage ripple of the boost converter,
additional headroom is necessary. Therefore an LSB step width of 50 mV
is selected for the CTRL DAC. This also nicely corresponds to the required
input voltage range from 7.5 − 18 V if an 8 bit DAC is used. Since the
boost converter has an input voltage of 6 V without an applied current,
6 + (28 − 1) · 50 mV = 18.55 V is the output voltage at the maximum output
current.

4.6 Implementation of the Functional Blocks

This section provides detail to the implementation of the functional blocks
of the MPPT. In particular the implementation of the comparators and the
DACs and some achieved simulation results are shown. Finally the digital
MPPT control is shown.

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4.6.1 Comparators

In the following, the structure of the comparators is shown. After this,

the implementation of the synchronization of the sampling to the boost
converter switching is presented. For the details on transistor level, please
consider the given literature.

DM Comparator

The DM comparator C2 is operated sampled which allows the use of a latch

to generate the output signal. Thereby a high gain and a fast transition
with a stable digital output is ensured. The implementation is shown in
figure 4.17. The differential input signal Vin,+ − Vin,− is first increased by
a preliminary amplifier (preamp) which provides a gain of 44 dB. Thereby
the clocked latch, which is controlled by Φsample,DM , has a decent input
signal.

Preamp Latch
Vin−
OUT
Vin+
Φsample,DM

Figure 4.17: Structure of the DM comparator C2.

The preliminary amplifier (preamp) is implemented as a differential folded

cascode OP. Details on the function are shown in [68, p. 269]. In contrast
to the standard implementation, this preamp has a designed input offset for
the reasons discussed in section 4.5.4. This input offset voltage is achieved
by an uneven weighted differential input pair. Thereby, a nominal offset of
Voff = 37 mV is achieved. Monte Carlo simulations show a Gauss distri-
bution around a mean of µmin = 30 mV with σmin = 6.1 mV at the corner
resulting in the lowest voltages [36]. The highest process corner leads to a
mean of µmax = 51 mV with σmax = 6.7 mV. This ensures a distance of 5σ
to no input offset and a maximal input offset of 91 mV with a distance of
6σ. Finally, the latch is implemented as a standard strong arm latch [94].
The circuit is supplied by V1.8V and draws a current of 4 µA.

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MEAS Comparator

Similar to the DM comparator, the MEAS comparator C1 samples the in-

put signal. Thus, it is implemented using a latch. Due to the required
low offset, discussed in section 4.5.4, an offset compensation is necessary.
Because of the sampling behaviour, an autozeroing technique can be effi-
ciently implemented [4, p. 469]. Figure 4.18 shows the structure of the
implemented MEAS comparator. It compares Vin,− to Vin,+ and gener-
ates the signal OUT as the result of that comparison. For this it features
a preamp consisting of multiple input stages, an offset compensation and
a latch clocked by Φsample,ME . Because of the clocked autozeroing, the
preamps need a sufficient speed to provide a good input signal to the latch
shortly after the autozeroing is finished.

Input Preamp Latch

Switches S1 S2 S3 S4 S5 S6
Vin−
OUT
Vin+

Φsample,ME

OPfb
Offset
Compensation

Figure 4.18: Structure of the MEAS comparator C1.

The first stage of the preamp is S1. It is implemented as a standard differ-

ential stage with mirrored differential output and diode loads [4, p. 400]. It
has a voltage gain of A = 3.4 dB and a gain bandwidth product (GBW) of
GBW = 30 MHz. The switches at the input of S1 are for the autozeroing
and allow to short the input voltages. In this case, one of the inputs keeps
being connected to S1 and the second input is shorted to this. During
normal operation Vin,− and Vin,+ are directly connected to S1. The sec-
ond and third stage S2 and S3 are both implemented as differential stages
with a diode load which allows a high bandwidth with a low current con-
sumption. Such an implementation is shown in [4, p. 490] without an
additional optional feedback compensation. The stages both show a DC
gain of A = 4.3 dB. S2 has a GBW = 65 MHz and due to the different
load, S3 has the smaller GBW = 3.5 MHz.

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The fourth stage S4 is implemented as a standard differential amplifier with

current mirror load as described in [4, p. 202]. In contrast to S1-3, which
were only implemented to add a small voltage gain and instead provide a
relatively low output impedance, S4 adds significant gain of A = 38 dB.
This is achieved providing a GBW of GBW = 296 MHz. The last stage
of the preamp, S5, is meant to provide a relatively low impedance output
to the latch. It is implemented similar to S2 and S3 utilizing a doubled
reference current. Thereby, it achieves a gain of A = 5.3 dB and a GBW =
165 MHz.
In total, the preamp has a gain of Atotal = 55.4 dB and a GBW = 81 MHz.
It achieves a gain of A > 50 dB for frequencies below f < 2.7 MHz. For
small inputs it shows a time constant τ = 95 ns for the output, which is
small enough to drive the latch after the autozeroing is switched off.
The output latch of the comparator is implemented as a strong arm latch [94].
It is controlled by the input clock Φsample,ME and flips to the final output
voltage sufficiently fast.
The offset compensation is implemented using an auxiliary amplifier as pre-
sented in [114, pp.70 ff.] and [143, pp.32 ff.]. A feedback is implemented
via OPfb injecting a current into the output stage of S1. During the au-
tozeroing, the input of S1 is shorted by the switches and the offset of all
stages until S4 is eliminated with the gain off S2-4 and OPfb . For the sam-
pling, the correct state of OPfb is stored at the capacitances. Monte Carlo
simulations for the whole comparator show an offset reduced to a sigma of
σnom = 68 µV in the nominal case and σmax = 106 µV at the worst corner
at T = 150 ◦C. This is enough to fulfil the requirements from section 4.5.4
with a security of 3σ at the highest specified temperature and about 4.4σ
for the typical corner. The circuit is supplied by V1.8V and draws a total
current of 17 µA.

Comparator Sampling

As discussed in section 4.5, the sampling of the comparators is critical. A

time shortly before the end of the minimum on-time of the boost converter
was determined as the best moment for the sampling. To synchronize the
digital part to the minimum on-time of the boost converter, the circuit
in figure 4.19 is used. The signal ENsample is set by the digital part and
CLKboost is provided by the boost converter control with a rising edge about

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10 ns before the end of the minimum on-time. When the comparator is not
meant to sample, ENsample is at logical low and the flip-flop is reset resulting
in Φsample and CC at logical low. When the comparator should sample,
the digital part sets ENsample to logical high. At the next rising edge of
CLKboost , the input of the D-flip-flop is acquired to the output Q resulting
in a rising edge of Φsample . This triggers the latch of the comparator to
sample the current input. After a time of 5 ns, the comparator is flipped
to the final state during a normal event and the conversion complete signal
CC is set.
Φsample

ENSample D Q Delay 5 ns CC
FF
CLKboost F
R

Figure 4.19: Clock synchronization for the sampling of the comparators.

In theory, a timespan of 5 ns would be sufficient for the comparator to flip.

If it needs more time, the inputs are right at the edge and thus both pos-
sible decisions are valid outputs. However, due to the application of the
output signal in a synchronous digital circuit, metastability is a problem
which has to be avoided [34]. It can occur, if the input of the comparator
is that small that the latch takes too much time to flip, especially longer
than the delay time of 5 ns. In this case, the digital part samples an un-
defined input signal which can lead to unpredictable behaviour. However,
the probability of such meta-stable events exponentially decreases with the
time, the comparator is available to flip [88]. In the CCM, the boost con-
verter is operated synchronously to the digital clock. Thereby, the time for
the comparator can be designed to be high enough that the likelihood of
a metastable event is sufficiently low. However, in DCM operation mode,
the boost converter switching is independent from the digital clock. There-
fore, the sampling of the CC signal to determine whether the comparator
has sampled could lead to metastability. To avoid or to greatly reduce the
likelihood of such events, the CC signal is resampled in the digital part.
Thereby, enough time is given to the signals to settle and problems due to
metastability are almost impossible.

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4.6.2 DACs

The DACs are the core of the MPPT and have different requirements to
the output quality and resolution. However, it is possible to share differ-
ent parts between the DACs which then only needs to be developed once.
The implemented 8 bit R2R-ladder is in particular the same for all of the
DACs.

DM DAC

For the operation of the DM DAC strict monotony would be beneficial

to quickly adjust Vsample . A wide input range of Vrng = 2 · Vmeas,V ,max −
Voff ,DMCMP,max = 235 mV is necessary. In combination with the resolution
of VLSB = 50 µV, this leads to a required number of log2 ( 235 mV
50 µV = 12.2 bit).
To achieve this, it is easier to combine two smaller sized DACs with a sig-
nificant overlap instead of implementing a direct 13 bit DAC. The place of
the resulting jump in the output characteristic is well known. By consid-
ering this place in the control, the impact of this can be compensated in a
way that the delta-modulator functions properly.
Figure 4.20 shows the two DACs applied to the delta-modulator. The LSB
and the most significant bit (MSB) DAC should be identical to reduce
the implementation effort. They provide a current at the output, which
is conducted into different nodes, which are connected by the resistors R1
and R2 . The input potential −Vmeas,I is connected to the PV cell and
has a very low impedance. Thus, the negative input of the comparator is
Vcmp,in,− = −Vmeas,I +R1 ·Ilsb +(R1 +R2 )·IM SB . The ranges for LSB and
MSB tracking can be independently selected by R1 and R2 . With values
of R1 = 0.975 kΩ and R2 = 19.5 kΩ the targeted ranges are met as shown
at the end of this section.
Due to the minimal DAC resolution of 50 µV, the noise at the input of
the comparator needs consideration. To reduce high frequency noise, the
capacitance C1 = 7.2 pF is added to the input of the comparator. Together
with R1 and R2 this forms an RC low-pass filter with an edge frequency
of 1.08 MHz for noise from Vmeas,I and 1.13 MHz for noise from the LSB
DAC. In addition to this the output noise of the MSB DAC is suppressed
by the attached capacitance. This keeps the DAC adjustments passing to
the comparator but suppresses noise above the edge frequency. Another
RC low-pass filter consisting of R3 = 511 kΩ and C2 = 3.6 pF is attached

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 4 Energy Harvesting ASIC

DAC
DMLSB
LSB
ILSB DAC
DMMSB
MSB
IMSB
R1 R2 Vcmp,in-
-Vmeas,I
Vsample
Vmeas,V
R3 C C2
1

Figure 4.20: Application of the DM DAC.

to the reference voltage. This suppresses noise above the edge frequency
of 87 kHz, which couples at the distribution of Vref or is generated by the
bandgap reference itself.
During the operation of the DM DAC, the MSB DAC is only used during
the pre-adjustment of the delta-modulator. After the rough pre-adjustment,
the LSB DAC is used for the fine pre-adjustment and the tracking of the
input after the perturbation. To be able to cover the input tracking range
after the pre-adjustment, the LSB DAC has to cover at least 4 lsb of the
MSB DAC. This is equivalent to the upper two MSBs of the LSB DAC cov-
ering this range, resulting in a required resolution of 14.2 bit. To be able to
use two instances of the same DAC for the LSB and MSB, two 8 bit DACs
are used. This leads to a range for the LSB DAC of 255·50 µV = 12.75 mV if
the targeted LSB is applied. This range is sufficient to track the input dur-
ing the accurate tracking, where a range of Vrng,track ≈ ±1 mV is required.
From the full scale range, this leads to a resolution of the MSB DAC of
235 mV
256 = 0.92 mV. The resulting overlap of the DACs leaves enough space
for adaptions, which are made to reduce the implementation effort.
Figure 4.21 shows the principle implementation of the LSB and MSB DAC
of the DM DAC. It uses an 8 bit R2R-ladder as discussed in section 2.2.
Since an output current is desired, the R2R-ladder is altered and used
with a constant voltage at VR2R , which is ensured by an OP controlling
the NMOS M1. The resulting current IR2R is mirrored by M2 and M3 to
the output current Iout .
The adapted implementation of the R2R-ladder is shown in figure 4.22. Due
to the OP, VR2R = Vref is maintained during operation of the DAC. In the
ladder, RMSB = 3R and accordingly the lengthways resistor RMSB,l = 2R

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 4 Energy Harvesting ASIC

V4.2V,aux

M2 M3

Iout
IR2R

M1
VR2R
IN R2R ladder

Vref

Figure 4.21: Block diagram of the LSB/MSB DAC.

are adapted. This leads to a 33 % smaller overall current at the output

without the need for 50 % bigger resistors for the main body of the R2R-
ladder. In addition to this the default state of the switches is changed.
At logical low at the n-th bit of IN, the switch is connected to Vref . The
resulting current is then
Vref IN
IR2R = · (4.27)
3R 128
with the 8 bit binary control word IN. The resistor is selected as R =
66.8 kΩ. This leads to a maximum output current of 11.9 µA. Together
with the values of R1 and R2 from figure 4.20, this leads to effective ranges
of Vrng,LSB = 11.7 mV and Vrng,MSB = 234 mV.
Simulations show an achieved Ilsb = 47.9 nA in the nominal case. Monte
Carlo simulations with 1000 samples at 3 different temperature corners
(−40 ◦C, 27 ◦C, 150 ◦C) were performed. The observed results are shown
in table 4.4. As discussed before, the values for the INL and the maximum
positive DNL have no major impact on the system performance. However,
the results show only small deviations. The DN L+,max is smaller than one
LSB and the absolute value of the INL is below three LSBs.
In contrast to the other values, the maximum negative DNL is not allowed
to get below DN L−,max = −1 LSB to avoid non-monotonicity. The results
show that the maximum value is DN L−,max = −0.39 LSB, which leaves
enough space for worse Monte Carlo simulation points as simulated. In
fact, these results only apply to all simulated input values IN > 4. Because
of the input offset of the OP, a dead zone can occur, where the output

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 4 Energy Harvesting ASIC

V4.2V,aux

M2 M3

Iout
IR2R

R R R RMSB,l = 2R VR2R

2R 2R 2R 2R RMSB = 3R
LSB
IN MSB
Vref

Figure 4.22: Implementation of the DM DAC.

Value Result
DN L+,max 0.35 LSB
DN L−,max −0.39 LSB
IN L+,max 2.1 LSB
IN L−,max −2.9 LSB

Table 4.4: Simulation results for the DAC.

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 4 Energy Harvesting ASIC

current is ≈ 0 A for all values of IN < 4. However, this only limits the DNL
and operation of the system at very small input values, and thus should
not occur during regular operation. In addition to this the criteria for the
DNL is still not violated since the DN L− ≤ −1 LSB for all inputs and
≈ −1 LSB at the critical steps at the beginning.

CTRL DAC

As discussed in section 4.5.4, the CTRL DAC needs a resolution of about

50 mV and a good PSRR. Since it is implemented in the feedback path
of the boost converter as shown in figure 4.3, the size of R1 = 1.2 MΩ
determines the required current LSB of Ilsb = 42 nA. Since this is close
enough to the DACs of the delta-modulator, the implementation can be
reused and only needs slight adaptions to get an output current which
flows into an NMOS of the DAC.
Figure 4.23 shows the implementation of the CTRL DAC. The R2R-ladder,
OP and M1-3 are equal to the DM DAC. The active LDO generating an
auxiliary voltage V3 V,aux = 3 V provides a higher PSRR than the auxiliary
LDO of section 4.4.6. The current through M3 is mirrored by M4 and M5
to the output. An RC low pass filter with three cascaded stages suppresses
noise and provides additional PSRR at medium and high frequencies. It has
three poles at f3dB,1 = 15.7 kHz, f3dB,2 = 142 kHz and f3dB,3 = 809 kHz,
which result from the dimensioning of the filter.

LDO V3V,aux
VPV
3V
M2 M3

IR2R

M1 Iout
Low Pass
VR2R
IN R2R ladder M4 M5

Vref

Figure 4.23: Block diagram of the CTRL DAC.

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 4 Energy Harvesting ASIC

MEAS DAC

The MEAS DAC is used to directly control the gate voltage of the mea-
surement MOSFET. As discussed in section 4.5.4, it only needs a reso-
lution of 12 bit without unknown non-monotonicity. In addition to this,
the maximum output voltage has to go up close to V5V . To achieve this,
the MEAS DAC is built of two 8 bit R2R-ladders as shown in figure 4.24.
Since the bit-width matches to the already used R2R-ladders, the design
was reused, which reduces the layout and implementation effort. The first
LSB R2R-ladder generates a voltage VLSB = Vref · 1+MEAS256
LSB
. This volt-
1
age is converted to Iinj with a transconductance of 3R = 4.99 µS by the
VI converter. This current is injected into the MSB R2R-ladder, which
generates VR2R based on MEASMSB . This voltage is scaled by the output
buffer driving Vg,meas .

VR2R Output
MEASMSB R2R ladder Vg,meas
Buffer
Iinj
VLSB V to I
MEASLSB R2R ladder
converter
Vref

Figure 4.24: Block diagram of the MEAS DAC.

The principle of the current injection to the MSB R2R-ladder is shown in

figure 4.25. The current is injected into the third lengthways node of the
ladder Vl,3 . Thereby it can influence the output comparable to the third
LSB, limited by the maximal injected current. The impedance at this node
is ≈ 32 R. Since the reference voltage of both R2R-ladders is equal, this
leads to a maximum voltage shift of Vinj = 92 Vref . Thus, the maximum
voltage at this node is limited to 11
9 Vref = 1.47 V where the resistors are
properly working.
The impact of the injection to the output can be calculated by superpo-
sition. As the influence of the other switches to VR2R does not change,
only the additional influence of Iinj has to be determined. The previously
calculated influence of Iinj to Vl,3 is divided 5 times. Due to the uneven
R2R-ladder this results in ∆VR2R = 0.0468 · VLSB . This results in the total

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 4 Energy Harvesting ASIC

R R Iinj R 2R
VR2R
Vl,3

2R 2R 2R 2R 2R 3R
LSB
IN MSB
Vref

Figure 4.25: MSB R2R current injection principle of the MEAS DAC.

output voltage of
(︃ )︃
1 + MEASMSB
VR2R = Vref · + 0.0468 · VLSB (4.28)
256
(︃ )︃
1 + MEASMSB 1 + MEASLSB
= Vref · + 0.0468 · (4.29)
256 256
(4.30)

This results in an overlap of ≈ 10 LSB of the MSB DAC and a total LSB
of VLSB = 228 µV which equals a resolution of 12.4 bit.
To achieve the required output voltage range and to reduce the output
impedance, the output buffer of figure 4.26 is used. It scales the input
voltage by a factor of 4 and provides a low impedance output at Vg,meas .
The output stage combines a PMOS and an NMOS source follower which
are operated against the switchable current sources. The OP controls the
feedback voltage divided by R1 and R2 = 3R1 to the input voltage VR2R .

During operation only Ibias,up or Ibias,dn is activated and conducts a cur-

rent. If only Ibias,up is active, M2 is operated as a source follower controlled
by the OP. Because of the feedback divider with R2 = 3R1 , the output is
then controlled to Vg,meas = 4 · Vin . The maximum output voltage in this
case is limited by the maximum input voltage. Since this is ≈ Vref = 1.2 V,
a maximum output voltage of 4 · Vref = 4.8 V is achieved. This is sufficient
to drive the external MOSFET in all occurring cases. The supply of the
output stage V5.6V,aux allows this with a sufficient remaining saturation
voltage for the current source Ibias,up . The minimum output voltage is de-
termined by Vgs of M2. If the output of the OP is at 0 V, Vg,meas = Vgs M2

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V5.6V,aux

M1
Ibias,up

Vg,meas
R2 Rcomp
Ibias,dn
M2
VR2R
R1

Figure 4.26: Output stage of the MEAS DAC.

remains at the output.

Since lower voltages are required for low IPV , the output stage features
M1 and Ibias,dn . If only Ibias,dn is active, M1 is operated as source follower
instead of M2. Thereby, output voltages of Vg,meas ≈ 0 V are realized.
The current in the switchable current sources can be modified during op-
eration. Thereby a high driving capability as well as a low DC current
consumption, if Vg,meas is not changed, is achieved. However, this requires
a new adjustment every time the current is changed, since the resulting Vgs
of M1 or M2 depends on the current. Since Vg,meas is directly connected to
the gate of the measurement MOSFET, a high capacitive load is expected.
Therefore, Rcomp is introduced to stabilize the control loop.

4.6.3 Digital Implementation of Algorithms

The implemented ASIC features a digital control, which consists of a fi-

nite state machine (FSM) and an SPI controller. The finite state machine
(FSM) implements the MPPT algorithm as described in section 4.5.2. Two
additional sub-FSMs control the adjustment of Vmeas,I as well as the pre-
adjustment and tracking of the delta-modulator. The digital part was
mainly implemented using VHDL. A share of the SPI controller is imple-
mented in systemC.

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 4 Energy Harvesting ASIC

MEAS Adjustment

The MEAS adjustment routine has to adjust the on-resistance of the mea-
surement MOSFET until Vmeas,I = Vmeas,V . For this it is able to control
Vg,meas of the MOSFET via the MEAS DAC. Since the MOSFET is in
the direct current path of the PV and thus the ASIC supply, precautions
are necessary to prevent it from switching off. Therefore the implemented
algorithm does not adjust the MEAS DAC using a binary search. Instead,
the target value is approached by limited steps from a high Vg,meas where
the MOSFET is active in all circumstances. To increase the adjustment
speed, a variable step-size is used. It starts at a maximum step, which is
small enough to ensure the external MOSFET to stay conducting. Since
in most cases IPV does not change very fast from one perturbation cycle
to another, an additional tracking routine is implemented. This is meant
to use, after the first adjustment has finished.
The flow chart of the measurement adjustment is shown in figure 4.27. At
the start, which is triggered by the MPPT control, first the required initial
values are determined. If the control is not in the initial adjustment, it only
needs to track the difference from the last operating point. These can be
considered two starting modes, an initial start which performs a full search
and a restart where the adjustment starts at the last operating point. At
the initial start, the increment is set to the start value inc = startINC.
This start value is selected in a way that a single step can never cause
the MOSFET to greatly increase the on-resistance. However, a relatively
high value can be selected, reducing the time to find the correct operating
point. The pulling direction of the output stage is set to pull = up and the
control of the MEAS DAC is set to CTRLmeas = startCtrl. Thereby, the
adjustment of Vg,meas is started new from a safe value. At the restart, only
the increment is set to inc = restartINC and thereby starts the adjustment
from the last operating point. The control values of the MSB and LSB
DACs are combined to a single 16 bit word and handled without regarding
the overlap. Because of the incremental approaching of the target value,
this only can increase the adjustment time if the DACs are frequently
operated at the edge from an LSB to an MSB. This is the cost to achieve
a very robust implementation of the adjustment. As well the absolute
strength of the output stage is associated with the current value of the
increment. Thereby, big steps of Vg,meas can be performed when inc is high
and a low DC current is drawn when inc is small or the MEAS DAC idles
where no big steps are required.

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 4 Energy Harvesting ASIC

start

no in operating
yes
initial point? 1
restart
start
inc = startINC measure trigger CMP
inc = restartINC
pull = up measurement
CTRLmeas=startCtrl

determine yes no CMP ==dir

inc ≤ min out
initial dir ? ?
no yes
adjust
inc = inc / 2 no restart &
CTRLmeas+=dir∙ inc cnt ≥ max
dir = −dir
?
yes
pull==up & yes change pull inc = 2∙ inc
CTRLmeas ≤ min direction

no final set
CTRLmeas
pull==dn & yes
CTRLmeas≥ max

no end

Figure 4.27: Flow chart of the MEAS DAC adjustment routine.

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 4 Energy Harvesting ASIC

After the initialization, first the initial incrementation direction dir is de-
termined by evaluating the comparator once. After this, the main adjust-
ment routine starts. During this the adjustment of CTRLmeas and the
measurement evaluation are alternated, both performing several checks to
improve the behaviour. The adjustment first increases the DAC control
MEASctrl + = inc preventing overflows. Then, two checks are performed
to detect, whether the direction of the output stage has to be changed. If
the output stage is in pull-up mode and the control value is below a min-
imum CTRLmeas ≤ min, the lower limit for pull-up operation is reached.
Vice versa when the stage is in pull-down mode and CTRLmeas ≥ max,
the upper limit for pull-down operation is reached. In both cases, the pull
direction is changed. If the upper limit of CTRLmeas in pull-up or the lower
limit in pull-down mode is reached, the adjustment is aborted and an error
flag is set, which is not shown in the flow chart. In the regular case, where
none of the above is true, the measurement evaluation starts.
During the measurement evaluation, the comparator is triggered first. After
this several evaluations are performed to determine whether the increment
inc has to be changed and whether the adjustment is finished or not. If
the current output value of the comparator CMPout equals the current
direction, the targeted operating point is not yet reached and the next
adjustment could start. Because of the restart mode, another check is
applied to avoid a long adjustment with many very small increases in case
that the new target operating point largely differs from the current point.
In the restart mode, the increment inc is doubled every time, a counter,
counting the number of successive incremental steps, exceeds a specified
limit cnt ≥ max. This binary exponential backoff like increase prevents the
described long adjustment.
If the current output value of the comparator CMPout does not equal the
current direction, Vg,meas has stepped over the target operating point. In
this case, the incrementation direction has to be changed, given that the
increment is not already at it’s minimum value. At the same time as the
direction is changed, the absolute increment value is halved. Thereby, the
approximation is nearly as with a binary search once the first change in
direction occurred resulting in a fast convergence. After the adaption of
dir and inc, the next adjustment is started. In case that the increment is
at the specified minimum, the adjustment is finished and CTRLmeas is set
to the average of the last two states.

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 4 Energy Harvesting ASIC

DM tracking

The operation of the delta-modulator is split into two sub processes as

shown in section 4.5.2. It has to determine Sdiff based on which the MPPT
algorithm is performed. Therefore the pre-adjustment is started before the
perturbation and the tracking is started after it.
The flow chart of the DM DAC adjustment is shown in figure 4.28. At
the start of the pre-adjustment, the LSB and MSB DAC are initialized to
DMLSB = 80x0 and DMMSB = 00x0. Then two similar SAR routines are
performed for the MSB and the LSB pre-adjusting the input as accurate as
possible. In each step of these SAR routines first the next bit is set. After
this, the output of the comparator is evaluated and the bit is cleared when
the output got too high. Otherwise the routine is continued with the next
bit until the LSB of DMMSB is evaluated. Subsequently the same is done
for DMLSB until the adjustment is finished.

start start
adjustment tracking

DMLSB = 80x0
inc = coarse
DMMSB= 00x0

Tracking
SAR Routine Routine
DMMSB set next bit =0 =1
CMP=?

=1 DMLSB+=inc DMLSB−=inc
clear last bit CMP=?

=0 no #steps>max
?
is LSB no yes
of DMMSB
?
yes
inc = fine

SAR Routine Tracking

DMLSB Routine

adjustment tracking
finished finished

Figure 4.28: Flow chart of the DM DAC adjustment routine.

The tracking of the changes caused by the perturbation is performed by

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incremental steps in a coarse and a fine mode. Initially the increment is set
to the predefined coarse value. After this the actual tracking is performed.
Therefore, the output of the comparator is continuously evaluated and
DMLSB is changed depending on this result. This is done in a fixed number
of steps. After this, the increment is set to the predefined fine value and
the tracking is started again. At the end Sdiff can be calculated by the
difference DMLSB,final − DMLSB,preadj . This value is used by the MPPT to
determine the next perturbation step.

SPI

To modify the behaviour of the ASIC in the laboratory in order to achieve

the maximum performance, an serial peripheral interface (SPI) is imple-
mented [76, pp. 291 ff.]. It allows to dynamically set and read registers in
the digital control of the ASIC during runtime. Even if the communication
speed is not high enough to directly close control loops, many parameters
for the operation can be changed on the fly. This allows a strong control of
the behaviour of the ASIC. In addition to this, additional debug capabili-
ties are added for an increased control. The SPI was implemented reusing
the code from other projects maintained by Jonas Meier. The register list
was generated with help of the “Digital InterFace Generator” (DIFG) tool
developed at the IAS [61]. The SPI runs up to a fifth of the system clock
speed and simulations show the intended function.

4.7 Simulation Results

This section shows simulation results for the implemented MPPT. Unfor-
tunately, measurements of the ASIC cannot be shown. Due to delays in
the project, the planned final tape-out was shifted to a later date multiple
times. Hence, the ASIC was not available for measurements for this thesis.
Instead, system simulations of the MPPT are shown. In particular, the
• static tracking efficiency,
• dynamic tracking response on an input power step as well as
• tracking efficiency for different irradiance profiles

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 4 Energy Harvesting ASIC

are presented. Especially the simulation of the irradiance profiles require

simulations for long times. Due to this and the high system complexity,
these simulations can not be performed on schematic level in reasonable
simulation time. Instead, models for the different functional blocks are
implemented together with Fabian Speicher, which reproduce the different
functions. Thereby the simulation speed is greatly improved and the per-
formance of the system can be evaluated. Possible differences between the
schematic simulations and the modelled system can be estimated roughly
by the comparison of the results of the profile simulations to the static and
dynamic simulations. Especially the behaviour during the initial settlement
can always be examined. For the second comparison, a step is inserted at
the beginning of the profile simulation.
The tracking speeds are determined considering the boost converter in
CCM for a better comparison. If the mode changes to DCM the determined
tracking speeds reduce linearly according to the switching frequency. This
correlation comes from the switching synchronization of the comparator
triggers. However, the simulated average efficiencies keep unchanged and
only the tolerance to fast changes in the irradiance is affected.

4.7.1 Static Tracking Efficiency

To evaluate the static tracking efficiency, the MPPT was simulated with in
the test-bench shown in figure 4.29. Here, the boost converter is modelled
only for it’s input voltage. This is done by a current controlled voltage
source (CCVS) with a transimpedance of 1.2 MΩ, which is controlled by
the output current of the CTRL DAC. The output of this CCVS in com-
bination with an additional DC voltage of 6 V gives the boost converters
input voltage. This directly imitates the voltage control of the boost con-
verter from figure 4.3. The dynamic behaviour of the boost converter is
modelled with the RC low-pass with an edge frequency of ≈ 32 kHz. This
model neglects the inherent input voltage ripple caused by the switching of
the boost converter. This allows the evaluation of the performance purely
of the implemented MPPT without performance losses due to other parts
of the system.
To evaluate the MPP tracking efficiency for static input irradiance values,
transient simulations were performed. Figure 4.30 shows the resulting PV
voltage VPV for a schematic level simulation as well as a model based sim-
ulation. The graph shows the initial finding of the MPPT. After this the

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 4 Energy Harvesting ASIC

1.2 MOhm ∙ Ictrl

VPV 6V

Vsense-
Vg,meas R Ictrl
CTRL
MPPT DAC
C Vref
Vsense+

Figure 4.29: Test-bench to simulate the MPPT.

fluctuation around the MPP at a static irradiance is visible. Thereby still

wrong decisions occur where VPV is increased even if it is already above
the MPP. These limit cycle oscillations can not be completely avoided even
if the code tries to reduce their occurrence as described in section 4.5.2.
However, they do not result in significant efficiency losses. The measured
MPP tracking efficiency ηmppt was determined integrating the instanta-
neous ηmppt at the steady state from 5 − 10 ms.
As the schematic level simulations are used to determine the static MPPT
performance, the model based simulation is used for the munch longer sim-
ulations of irradiance profiles from section 4.7.3. The traces in figure 4.30
show a good performance of the models. Even if they required a different
number of perturbation cycles to find the MPP, they show similar charac-
teristics at finding it and the resulting performance in the steady state is
very accurately modelled. Thus, the implemented models can be used to
approximately evaluate the system’s performance.
Table 4.5 shows the results for static input irradiance values. The available
power, resulting MPP voltage and MPP tracking efficiency as well as the
average current consumption of the MPPT are shown. The simulation show
a very high MPP tracking efficiency ηmppt of about 99.9 % and above for
a wide input range from 10 − 100 % of the nominal input irradiance. Even
for an input irradiance of 5 % the tracking efficiency is at ηmppt = 99.78 %.
Other works show tracking efficiencies in a range of 98 − 99.9 % so the
implemented solution is at the upper side of the results [28, 120, 135, 136,

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 4 Energy Harvesting ASIC

10 VMPP
Voltage [V]

VPV ,schematic
7
VPV ,model

0 2 4 6 8 10
time [ms]

Figure 4.30: Comparison of schematic to model for 50 % irradiance.

153].

Rel. Input Available VMPP MPPT Iavg

Irradiance Power Efficiency ηmppt
5% 3.1 W 7.2 V 99.78 % 197 µA
10 % 7.0 W 7.9 V 99.87 % 209 µA
20 % 15.6 W 8.7 V 99.88 % 207 µA
50 % 44.0 W 9.8 V 99.95 % 209 µA
75 % 69.3 W 10.2 V 99.93 % 213 µA
100 % 95.6 W 10.6 V 99.96 % 214 µA

Table 4.5: Summarized simulation results for static input irradiance.

During operation the MPPT requires an average current of 197 − 214 µA.
The differences mainly can be tracked to the input dependent current re-
quirements in the R2R-ladders. Since these currents are generated by linear
regulators out of VPV , the required power can be calculated referring the
input voltage VPV . At the given ηmppt VPV ≈ VMPPT holds which results
in a required power of 1.42 − 2.27 mW. Referred to the input power this
P
equals a maximum of Pmpptin
= 0.46 ‰ at 5 % irradiance and a minimum of

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 4 Energy Harvesting ASIC

0.024 ‰ at nominal irradiance. Concluding from this, the required power

of the MPPT circuits efficiently perform the MPPT and only have a minor
influence to the overall harvested energy.
The observed MPP tracking efficiency is that high that it depends on the
specific operating point and how close the next available voltages of the
boost converter are. To reduce this influence many simulations were per-
formed and the achieved tracking efficiencies are binned by power. The
result of this evaluation is shown in table 4.6 and matches well to the sim-
ulation points shown in table 4.5. The average tracking efficiency is above
99.9 % in all bins and a slightly better tracking efficiency at higher input
powers can be observed meeting the requirements to the static MPPT per-
formance from table 4.3.

Relative Input Power Tracking Efficiency ηmppt

PP V /P0 in % in %
3 − 20 % 99.91 %
20 − 40 % 99.90 %
40 − 60 % 99.94 %
60 − 80 % 99.96 %
80 − 100 % 99.96 %

Table 4.6: Tracking efficiency at different input [96].

4.7.2 Tracking Speed

To test the tracking speed of the MPPT simulations of a rapid change in

irradiance from 50 % to different final irradiance values were performed.
Because of the high control bandwidth of the boost converter of fBW ≈
42 kHz VPV is modelled to be at the configured value all the time. The time
required to reconverge to the MPP was measured to determine a tracking
speed. Figure 4.31 shows the resulting VPV from 5 − 12 ms. Until the
irradiance step at 7 ms all traces shows the same progress. From this point
on they reconverge to the new MPP which is depicted in the dashed lines.
In all four cases the MPPT manages to accurately find the new MPP after a
short time of voltage adjustments. The bigger steps from 50 % to 10 % and
100 % show slightly higher conversion times as expected. The timing of the

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 4 Energy Harvesting ASIC

irradiance step between the pre adjustment and the tracking of the delta-
modulator at a falling perturbation edge is a worst case scenario. Thereby
the power change observed by the MPPT always results in a wrong next
perturbation step increasing the time required for the reconversion. This
is clearly visible especially for VPV ,0.75 and VPV ,1.0 which at first make a
huge step to a lower voltage before approaching the MPP.

11

10
Voltage [V]

8 VPV ,1.0
VPV ,0.75
VPV ,0.25
7 VPV ,0.1

5 6 7 8 9 10 11 12
time [ms]

Figure 4.31: Tracking of VPV for different steps of the irradiance.

The results of the simulations are presented in table 4.7. Six different input
steps were measured covering only small steps as well as big steps. The
observed convergence times range between 0.5 ms and 2.2 ms. They directly
correspond to the relative step size as a higher step results in a higher
convergence time. The convergence of the steps to a higher irradiance
require a longer time, which mainly comes from the big initial step into the
wrong direction. These convergence times do not necessarily need to cover
the maximum convergence time which can occur. However, the simulated
steps are selected from typically occurring scenarios. Thereby they give
a hint on the necessary time, which can be expected during a commonly
occurring step.
As a measure for the tracking losses during the step the average efficiency
from 5 − 12 ms is taken. This timespan starts in a steady state and the
reconvergence covers a significant share. For the step to 10 % this results in

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 4 Energy Harvesting ASIC

an average efficiency of 96.7 % so the high temporary drop to 52 % in track-

ing efficiency is quickly adjusted. For all other steps the average tracking
efficiency keeps above 99 % meeting the targeted dynamic tracking effi-
ciency from table 4.3. The tracking efficiency from 10 − 15 ms is better
then 99.87 % in all cases matching to the static tracking efficiencies from
table 4.5.

Final Value of Time to Efficiency Efficiency

Input Step Reconverge 5 − 12 ms 10 − 15 ms
10 % 1.8 ms 96.7 % 99.87 %
25 % 1.2 ms 99.5 % 99.87 %
45 % 0.5 ms 99.9 % 99.88 %
55 % 1.5 ms 99.6 % 99.91 %
75 % 2.0 ms 99.4 % 99.92 %
100 % 2.2 ms 99.2 % 99.94 %

Table 4.7: Summarized simulation results for an input irradiance step.

4.7.3 Efficiency at Different Irradiance Profiles

To evaluate the dynamic tracking efficiency, the tracking of different irra-

diance profiles is simulated. These model the shading resulting from differ-
ent sources as passing clouds, bikes and cars. Following from the different
speeds of the shading causes, they heavily differ in gradients at which the
shading is applied. Passing cars cause shading gradients of up to 50 %
5 ms [154].
50 %
The gradient for bikes is at about 25 ms and the penumbra of passing clouds
need 2 − 10 s until the full shade applies [56, 154].
Figure 4.32 shows the simulated profiles. In the bike and the car profile the
irradiance of full sunlight is shortly lowered to an irradiance of 50 % with the
specified slopes. This models a scenario where a passing bike or car casts a
shadow on the PV cells. Thereby the total scenario time of the bike profile is
100 ms and of the car profile is 50 ms concerning the different edge steepness.
This scenario is meant to give a very rough estimation to the efficiency
losses due to the fast change in irradiance. The amount of time of the
transients on the complete process of a passing car is overestimated, since
a car at 130 km h−1 takes 125 ms to pass its length of ≈ 4.5 m. In addition

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 4 Energy Harvesting ASIC

cars
to this, the maximum capacity of a street lane is at around 2400 hour [10]
which results in less than one car per second. However, the described
scenario is simulated for a rough estimation and to limit the simulation
time. In addition to the two scenarios, two very slow transient edges model
the influence on the tracking of passing clouds. Because of the limited
80 %
simulation times transients of 190 ms are simulated instead of a time scale
of 2 − 10 s. Thereby the simulated tracking efficiency is underestimated.
Finally the irradiance profile, which is used in the paper [154], is scaled to
the designed full irradiance and simulated for comparison.

100

80
Irradiance [%]

60

Car profile
40
Comparison
Bike profile
20 Slow falling
Slow rising
0
0 20 40 60 80 100 120 140 160 180 200
time [ms]

Figure 4.32: Different simulated irradiance profiles.

Resulting Efficiencies

The profiles were simulated using the developed models. Figure 4.33 shows
the resulting tracking efficiency of the accelerated cloud scenario. It shows
that the tracking efficiency ηmppt > 0.99 = 99 % for the complete slopes
except the initial finding of the MPP and a small part of the falling slope at
≈ 200 ms. The average efficiency for the slopes from 5 − 200 ms is 99.86 %
and 99.93 % for the falling and rising slope respectively. The tracking per-
formance is slightly better at higher input powers, which corresponds to
the static tracking efficiencies. Another reason to this observation is, that

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 4 Energy Harvesting ASIC

at low input powers the change of the voltage is larger relatively seen. In
addition to this, a slightly better performance for the rising edge is visible.

1
Tracking efficiency

0.995

0.99
Falling slope
Rising slope
0.985
0 20 40 60 80 100 120 140 160 180 200
time [ms]

Figure 4.33: Tracking efficiency of the slow slopes.

Figure 4.34 shows the results of the passing car and bike scenario as well as
the simulation performed for comparison. It presents the tracking efficiency
and the absolute achieved power compared to the available power. The
tracking efficiency shows drops at the edges where the irradiance and thus
the available power changes quickly. For the bike scenario these drops are
small and the tracking efficiency remains above 98 %. The drops for the car
scenario are down to 94 %. The biggest drop is visible in the comparison
scenario (Cmp.) where the tracking efficiency is at only 86 % for a short
time. However, these drops occur only for a small amount of the whole
time and the tracking efficiency quickly recovers above 99 % after the rapid
gradient in power is over.
The resulting average efficiencies for each scenario are shown in table 4.8.
The time interval used for each calculation is indicated as well. These
intervals are chosen to not cover the initial finding of the MPP since this
is rarely necessary during operation. In the meantime the PV cells are
operated close to the MPP and the loss in tracking performance under
changes of the irradiance is of interest. The measured average efficiencies
are all equal or above of 99.5 % indicating a very high dynamic tracking
efficiency fulfilling the performance targets from table 4.3. In comparison
to [154], the implemented circuit outperforms the presented state-plane
direct (SPD) MPPT. This even is the case when the initial MPPT finding

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 4 Energy Harvesting ASIC

1
Tracking efficiency

0.95

0.9

0 20 40 60 80 100
100

80

60
P [W]

40 Bike
Car
20 Cmp.
Avail.
0
0 20 40 60 80 100
time [ms]

Figure 4.34: Tracking efficiency of the bike, car and comparison profile.

145
 4 Energy Harvesting ASIC

and an additional loss of 0.06 % due to the input voltage ripple described
in section 4.2.1, is considered.

Profile Average Integrated

Tracking Efficiency Time Interval
Car 99.5 % 5 ms − 50 ms
Bike 99.8 % 5 ms − 100 ms
Rising Slope 99.93 % 5 ms − 200 ms
Falling Slope 99.86 % 5 ms − 200 ms
Comparison 99.6 % 5 ms − 100 ms
99.2 % 0 ms − 100 ms

Table 4.8: Average tracking efficiencies of the simulated scenarios.

In total the implemented MPPT shows a very good MPP tracking accuracy.
The static tracking efficiency was proven above 99.9 % for a wide range of
input irradiance. The recovery time after a step in the input irradiance is
found to be in the range of ms. Finally the performance of different shading
scenarios was simulated and average tracking efficiencies above 99.5 % were
found.

4.8 Appended: Measurement Results

The ASIC was implemented in a 180 nm technology at an area of 2.5 mm ×
2.5 mm. Figure 4.35 shows a micrograph of the die. In the upper third,
the metal lines are visible, which connect the power stage of the DC-DC
converter to the PCB. On the lower left, the digital part is located.
Figure 4.36 shows the PCB, which was developed for the measurements.
Only the circuitry on the left side, limited by the right side of the coil, are
necessary for the operation. The other circuitry is added to configure the
ASIC for different measurements, which are not necessary in a productive
environment.
The available measurement setup only allows to measure static tracking
efficiencies. To increase these, the configuration of the MPPT was ad-
justed. Especially the values configuring the delta-modulator tracking rou-
tine needed adaptions from the values used in simulations. The biggest im-

146
 4 Energy Harvesting ASIC

Figure 4.35: Micrograph of the ASIC.

Figure 4.36: Picture of the measurment PCB.

147
 4 Energy Harvesting ASIC

pact had the increase of time, which was taken for the tracking. Thereby,
the noise is reduced and the update rate is lowered from about 5 k update /s
to 1 k update /s.
Figure 4.37 shows the initial settling of the PV voltage VPV of the ASIC
for available input powers of 45 % and 100 % of the nominal input power.
The source is already active when the ASIC is activated. At this point, the
DC-DC converter rapidly controls the voltage to a set initial level. From
this point on, the MPPT algorithm performs steps in the correct direction,
until the tracking acceleration greatly increases these steps. Once, the MPP
is exceeded, the direction is inversed and VPV fluctuates around the MPP.
This settling is very similar to the simulated settling in figure 4.30.

Figure 4.37: Settling for 45 % and 100 % of the maximum input power.

To determine the tracking efficiency, two measurements were necessary for

each point. First the tracker is simply activated and the extracted power is
measured. Therefore, several single measurements were conducted and the
average was taken. To determine the real MPP, the second measurement
was performed. This MPP at the ASIC, is only roughly set by the solar
cell simulator, and also depends on PCB. To measure the available power
as accurate as possible, it was necessary to not alter the cabling. Instead,
the MPP was measured by sweeping VPV in a debug mode of the chip
and determining the converted power the same way, as in the measurement
with the active MPP.
The resulting measured efficiencies are shown in table 4.9. The achieved
measured efficiency is above 99.6 % reaching up to 99.85 % at an input
power of 5 % of the nominal input power. These results are slightly below
the simulated efficiency above 99.9 %. However the proper functioning for
a very wide range of input powers is clearly achieved.

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 4 Energy Harvesting ASIC

PP V /P0 ηM P P T
5% 99.85 %
10 % 99.8 %
45 % 99.6 %
100 % 99.8 %

Table 4.9: Measured tracking efficiencies.

Considering the measurement accuracy, some aspects should be regarded

more closely. Firstly an additional modelled series resistance in the IO cells
affects the adjustment of the measurement transistor in the pre-processing
as shown in figure 4.38. The additional resistance of about 240 Ω is depicted
below the on-chip pre-processing. Thereby, Vcmp is not adjusted to 0 V, and
thus Vmeas,I is not adjusted to Vmeas,V . Instead Vmeas,I is adjusted to

2Rio
Vmeas,I = Vmeas,V · (1 − ) (4.31)
R2 + Rio
giving a missadjustment of ≈ 20 %. Adding this series resistance to the
simulation results in a 0.4 % drop of the tracking efficiency. Even consid-
ering that the simulations were performed with a two diode model and the
measurement was performed with an open-short-MPP model, measured
efficiencies of 99.85 % should be regarded carefully.
-Vmeas,I
Vin
preprocessing R1≈555kΩ
R3 Vcmp R4 Vmeas,V

MEAS
DAC
Logic R2≈2.2kΩ
C1

Rio~240Ω

Figure 4.38: Impact of IO cell series resistance.

The main possible origin of measurement inaccuracy is the limitation due to

149
 4 Energy Harvesting ASIC

the split measurement of MPP and MPPT. Thereby, the accuracy is limited
by the reproducibility of the setup. Variations due to thermal effects can
easily occur at powers of up to 100 W. In addition to this, the solar cell
simulator seems to be stimulated by the MPPT. Figure 4.39 shows the
measured parameters for a single session with active MPPT. The power
fluctuates between 45.3 W and 45.6 W, which is a range of ≈ 0.7 %. The
average power is 45.47 W with a standard deviation of ≈ 0.06 W which
equals 0.13 %. These variations were not present during the measurement
of the MPP with only the DC-DC converter active. With this uncertainty,
reliable measurements of 99.9 % are not possible. However, the expected
measurement inaccuracies are limited and the results are consistent in all
measurements. Therefore, the measured tracking efficiencies are unlikely
to be far off their real values. Even at the lower power during the 5 %
measurement, where the influence of the temperature should be very small,
a similar tracking efficiency was measured. Concludingly, it is plausible
that the measured tracking efficiency is above 99.5 %. The measured values
could even fit, considering the possibility of a reduced dependency to the
pre-adjustment of the PV model, used by the solar cell simulator.

Figure 4.39: Variations of input power during steady state.

150
 Chapter 5
Conclusion and Outlook

This work shows the implementation of an integrated PV energy harvest-

ing ASIC, featuring an integrated boost converter controller and a maxi-
mum power point tracker (MPPT). The MPPT implements the incremental
conductance (InCond) tracking technique with an analogue preprocessing,
which is based on the ripple correlation control (RCC) technique. To enable
a standalone operation and minimize the required external components an
additional power management unit (PMU) providing all required supply
voltages is integrated too. Such a PMU can also be used in many other
power electronic systems, which steadily gain complexity accompanied by
an increasing number of required supply voltages. To avoid a failure in
the PMU, which would make the measurement of the ASIC impossible,
first the implementation of the PMU in a gate driver IC with similar sup-
ply voltages is investigated. Based on the gained experience, the PMU of
the PV energy harvesting ASIC is implemented. Measurement results of
the PMU of the gate driver IC are given and simulation results of the PV
energy harvesting ASIC are presented.
The exploration for the PMU is performed in a gate driving IC. This appli-
cation is examined as a first example of an integrated smart power electron-

151
 5 Conclusion and Outlook

ics system. The IC requires three additional supply voltages at 1.8 V, 5 V

and 10 V. Because the 1.8 V has the biggest share of current consumption,
a buck converter is implemented for this supply. The other two voltages
are supplied with linear regulators. Because it is used as virtual ground
for a 10 − 15 V voltage rail, the 10 V only needs to be able to function as a
current sink. A complete undervoltage lockout (UVLO) managing different
operating states depending on the availability of an external power supply
are not necessary and only the start-up has to be controlled. Therefore a
start-up control is added to the PMU. In addition to this, the LDO gener-
ating 5 V has a capacitive start-up circuit attached, which makes sure that
the supply is generated independently when the main supply is applied to
the chip. Measurements showing the proper start-up of the chip as well as
the function of the buck converter are given. Finally improvements of the
start-up capability of the LDO are shown to be used in the next ASIC.
The development of the PV energy harvesting ASIC is the main target of
this work. Simulations show that the targeted static and dynamic MPPT
tracking efficiency of > 99.9 % and > 99 % respectively are met. For this the
system requirements and the block diagram are presented. Subsequently
the implemented functional blocks are detailed.
To enable a flexible application, the submodular boost converter topology is
selected. An InCond MPPT, which uses analogue preprocessing to evaluate
the basic tracking condition is developed using the principle of a modified
RCC MPPT technique. Based on these decisions the system block diagram
is developed, which features the boost converter, PMU and MPPT. The
boost converter controls the input voltage at the PV module to a level
which can be adjusted by the MPPT. It was mainly developed by Michael
Hanhart. It features a control for the CCM and DCM operating mode
as well as a soft start-up and a mode change. The switches of the boost
converter power stage are selected to be external because this allows higher
efficiencies and a more flexible application for different current ratings.
For it’s operation the ASIC requires different voltage supplies and a refer-
ence voltage as well as multiple reference currents. The PMU provides all
these to the ASIC. Therefore it features a 1.8 V LDO to supply the digi-
tal part and several other functions. An externally buffered 5 V supply is
implemented for circuits which require a higher voltage headroom for oper-
ation. A second 5 V LDO supplies explicitly analogue loads, which require
a supply with low noise and drain a constant current themselves. Finally
an auxiliary LDO is added, providing multiple output voltages, which are

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 5 Conclusion and Outlook

each exclusively used by a single sub circuit. Thereby the cross coupling is
greatly reduced and thus significant variations in the output current are al-
lowed without disturbing other circuits. To implement this auxiliary LDO
in a small area, this comes at the cost of a poor line regulation and an
absolute voltage between 3.9 V and 4.6 V. Nevertheless this supply is very
well suited for several circuits which cannot be supplied by the analogue
5 V supply because of their current characteristic.
The MPPT implements the InCond technique with a periodical perturba-
tion to detect how the PV operating point has to be adjusted to find the
MPP. The InCond technique is based on the comparison of the DC conduc-
tance of the PV module to its derivative or the small signal conductance.
This condition is evaluated by a delta-modulator, which tracks the reaction
of the PV cell to the perturbation. An analogue preprocessing performs
an adjustment of the detection, thereby bringing the large signal values of
the conductance to the delta-modulator tracking. This allows to relax the
requirements of different analogue circuits, which are operated in closed
control loops and thereby compensate for non-idealities. A mathematical
derivation of the convergence to the MPP completes the investigation of
this new MPPT technique. In the following the implemented comparators
and DACs are shown. As the basic circuits are known from literature, the
focus is set to the relaxed requirements and how these reduce the imple-
mentation effort.
Finally simulation results are presented. From the application follows that
the static as well as the dynamic MPPT performance are of interest. To
evaluate the performance of solely the MPPT the boost converter is mod-
elled as an ideal power converter neglecting the input voltage ripple. The
static tracking efficiency is simulated to be above 99.9 % for a big range
of input irradiance and therefore power. Two more simulation series, the
reaction to a step in the irradiance and a dynamic irradiance profile, are per-
formed to determine the dynamic tracking performance. The simulations
of the reaction to different irradiance steps allows to determine the tracking
speed, how fast the system is reset to the new MPP. This time depends
on the size of the step and is below 2.2 ms for the performed simulations.
Thereby a range of ms can be estimated even in worst case scenarios. The
simulations of different irradiance profiles show a very high performance
above 99.8 % for slow slopes of the irradiance in a time of 200 ms. This
is used as an estimation for the tracking performance for slow changes in
irradiation which are caused by clouds or shade from static objects during
the day. An additional slope was simulated to compare the tracking effi-

153
 5 Conclusion and Outlook

ciency to the paper [154]. The simulation results show that the developed
MPPT has a slightly higher tracking efficiency of 99.2 % or even 99.5 %
in comparison to 99 %, which the state-plane direct (SPD) from the paper
achieves. The simulations with steep slopes of up to 50 % in 5 ms model a
passing car or bike. Here high temporary drops in the tracking efficiency
are observed but due to the fast reconvergence to the MPP, the average
MPPT efficiency is still above 99.5 %.

Outlook
This work has shown the implementation of the PV energy harvesting
ASIC. To make it a useful product that contributes to the efforts to in-
crease the share of renewable energies, there is still a long ways to go. The
final step for the integration into an ASIC could not be completely accom-
plished until the completion of this work for several reasons. Thus, this is
the next step, which has to be performed for a further investigation of the
MPPT technique. After the manufacturing by a third party, the ASIC can
then be measured in the laboratory. If the reproduction of the simulation
results in actual measurements succeeds, the MPPT technique has proven
it’s potential. The next steps would be the integration of the ASIC into
different applications. Starting from the projects at IAS the first test can
be performed in solar tiles reducing the installation effort and increasing
the energy output, or for IIPV. Further application can be in facades, bus
stations, pavements or noise barriers.
The developed start-up techniques for the PMU can be applied to other
smart integrated power electronic systems. Thereby additional experience
with on-chip power management can be gained. The next logical step is
to measure the MPPT ASIC proving the functioning of this concept in a
second IC. After successful evaluation of the operation reliability, a broader
usage in a wide range of different applications is possible. Thereby the effort
to use these ASICs can be lowered, opening more applications for integrated
power electronics.

154
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 Curriculum Vitae

Name Leo Rolff

Academic Degree Master of Science ([Link].)

Education and Professional Experience

09/2015-07/2020 Integrated Analog Circuits and RF Systems lab-
oratory RWTH Aachen University
Research assistant and Ph.D. student

03-08/2014 Rohde und Schwarz GmbH& Co. KG

Development Hardware Platforms
München, Germany
Internship

10/2012-03/2015 RWTH Aachen University

Electrical Engineering, Information Technology
and Computer Engineering
Master studies

10/2009-09/2012 RWTH Aachen University

Electrical Engineering, Information Technology
and Computer Engineering
Bachelor studies

169
Awards, Scholarships
2014 Nominated for “ZukuftErfindenNRW, Der
HochschulWettbewerb”
ProVendis

11/2012-09/2015 Rohde & Schwarz Go for Master Stipendium

scholarship

10/2006-03/2009 Studienstiftung des deutschen Volkes

scholarship

10/2010-09/2012 NRW/Deutschland Stipendium

scholarship

2010-2013 Deans’ List of RWTH Aachen Member

170
 List of Publications

Peer Reviewed Conference Papers

1. S. Dietrich et al. “12.4 A 7.5 W-output-power 96 %-efficiency
capacitor-free single-inductor 4-channel all-digital integrated
DC-DC LED driver in a 0.18 µm technology”. In: 2015 IEEE
International Solid-State Circuits Conference - (ISSCC) Digest of
Technical Papers. Feb. 2015, pp. 1–3.

2. L. Rolff et al. “Multiple input, single output, single inductor

DC-DC converter architecture providing charge reuse by an efficient
high voltage current sink”. In: 2016 18th European Conference on
Power Electronics and Applications (EPE’16 ECCE Europe). Sept.
2016, pp. 1–9.

3. S. Strache et al. “A digital pulse width modulation closed loop

control LDMOS gate driver for LED drivers implemented in a
0.18 µm HV CMOS technology”. In: 2017 IEEE Custom Integrated
Circuits Conference (CICC). Apr. 2017, pp. 1–4.

4. L. Rolff et al. “An Integrated Low Drop Out Regulator with

Independent Self Biasing Start Up Circuit”. In: 2018 25th IEEE
International Conference on Electronics, Circuits and Systems
(ICECS). Dec. 2018, pp. 213–216.

171
 5. E. Schulte Bocholt et al. “Self-Calibrating Digital-to-Time
Converter in CMOS for Advanced Control in Smart Gate Drivers”.
In: 2019 17th IEEE International New Circuits and Systems
Conference (NEWCAS). June 2019, pp. 1–4.

6. L. Rolff et al. “Startup Behaviour of Power Managment Unit for an

Integrated Gate Driver”. In: 2019 15th Conference on Ph.D
Research in Microelectronics and Electronics (PRIME). July 2019,
pp. 53–56.

7. M. Scholl et al. “A 32 MHz Crystal Oscillator with Fast Start-Up

Using Dithered Injection and Negative Resistance Boost”. In:
ESSCIRC 2019 - IEEE 45th European Solid State Circuits
Conference (ESSCIRC). Sept. 2019, pp. 49–52.

8. L. Rolff et al. “An Integrated Incremental Conductance MPPT

based on a Delta Modulator with Analog Preprocessing”. In:
ANALOG 2020; 17. ITG/GMM- Symposium. Sept. 2020.
9. J. Grobe et al. “Design of a Flexible Bandgap Based High Voltage
UVLO with Pre-Regulator”. In: 2020 27th IEEE International
Conference on Electronics, Circuits and Systems (ICECS). 2020,
pp. 1–4. doi: 10.1109/ICECS49266.2020.9294922.
10. L. Weihs et al. “Design of an integrated Maximum Power Point
Boost Converter for PV Submodules”. In: 2021 16th Conference on
PhD Research in Microelectronics and Electronics (PRIME). 2021,
pp. 1–4.

Patents
1. Sebastian Strache et al. “Treiberanordnung fuer einen zu steuernde
Transistor”. German. German Patent Application DE 10 2013 217
902.2 (Roemerstrasse 16 B, 52428 Juelich, Germany). Sep. 9, 2013.

2. Sebastian Strache et al. “Treiberanordnung fuer einen zu steuernde

Transistor”. German. Int. Patent Application PCT/IB2014/002135
(Roemerstrasse 16 B, 52428 Juelich, Germany). Sep. 9, 2014.

172
Monographs
1. Leo Rolff. “Developement of an Integrated Pulsewidth Driver for
Power MOSFETs”. German. Supervisor: Sebastian Strache.
Bachelor thesis. Aachen, Germany: Integrated Analog Circuits and
RF Systems, RWTH Aachen University, 2012.

2. Leo Rolff. “Design, Control and Implementation of a Step-Down

Converter for Power Applications”. German. Supervisor: Eva
Schulte Bocholt. Master thesis. Aachen, Germany: Integrated
Analog Circuits and RF Systems, RWTH Aachen University, 2015.

173
So do all who live to see such times but that is not for them to decide. All
we have to decide is what to do with the time that is given to us.