"A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in ..."

Timothy O. Dickson et al. (2015)

> Home

Details and statistics

DOI: 10.1109/CICC.2015.7338371

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/DicksonLABADPMF15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/DicksonLABADPMF15
Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman:
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC 2015: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.