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ORCIDYufeng Xie 0001
Person information
- affiliation: Fudan University, School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
- affiliation (PhD 2008): Tsinghua University, Beijing, China
Other persons with the same name
- Yufeng Xie — disambiguation page
- Yufeng Xie 0002
![[0009-0005-4640-0119]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0009-0005-4640-0119")
— National University of Defense Technology, College of Intelligence Science and Technology, Changsha, China (and 1 more)
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2020 – today
- 2026
[j10]Shengchao Zhou, Yifan Wang, Hongrui Meng, Yajun Wu, Zizhao Ma, Teng Zou, Tai Min, Shaohao Wang, Yufeng Xie:
A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. 34(1): 48-60 (2026)- 2025
- [j9]Chunshan Wang, Zizhao Ma, Yuxuan Zhu, Chensheng Jin, Dongyu Chen, Chuxin Zhang, Yining Chen, Wenzhong Bao, Yufeng Xie:
Yield Diagnosis and Tuning for Emerging Semiconductors During Research Stage. IEEE Access 13: 78915-78927 (2025) - [c10]Hongrui Meng, Yajun Wu, Shengchao Zhou, Zizhao Ma, Tai Min, Shaohao Wang, Yufeng Xie:
A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration. ISCAS 2025: 1-5 - [c9]Shengchao Zhou, Teng Zou, Zeming Wang, Xianwu Hu, Hongrui Meng, Yajun Wu, Chuxin Zhang, Caihua Wan, Yufeng Xie:
High sensing margin and parallelism 6T-2MTJ SOT-MRAM based TCAM for energy-Efficient Similarity Priority calculation in MANNs. ISCAS 2025: 1-5 - 2024
- [j8]Yifan Wang, Jianrong Xu, Fei Xu, Long Deng, Chensheng Jin, Wenzhong Bao, Yufeng Xie:
Contactless Diagnosis Method and Unsupervised Learning for Panel-Level Photovoltaic Plant Operation and Maintenance. IEEE Access 12: 174808-174817 (2024) - 2023
- [j7]Xianwu Hu, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4216-4220 (2023) - [c8]Zizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. A-SSCC 2023: 1-3 - [c7]Zizhao Ma, Xianwu Hu, Yihao Wang, Gan Wen, Xiaoyang Zeng, Yufeng Xie:
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. ISCAS 2023: 1-5 - 2022
- [c6]Xianwu Hu, Yu Wang, Jiayun Feng, Zizhao Ma, Xiaoyang Zeng, Yufeng Xie:
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. ISCAS 2022: 2438-2442 - 2021
- [c5]Xianwu Hu, Dongyang Li, Yu Wang, Jiayun Feng, Zizhao Ma, Shaohao Wang, Tai Min, Xiaoyang Zeng, Yufeng Xie:
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. ASICON 2021: 1-4 - [c4]Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie:
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight. ASICON 2021: 1-4
2010 – 2019
- 2019
- [c3]Danqing Wu, Shilin Yan, Haodi Tang, Yu Wang, Jiayun Feng, Xianwu Hu, Jiaxin Cao, Yufeng Xie:
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme. ASICON 2019: 1-4 - 2017
- [j6]Xiaoyong Xue, Yarong Fu, Yanqing Zhao, Juan Xu, Jianguo Yang, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 186-190 (2017) - 2016
- [j5]Yufeng Xie, Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Qingtian Zou, Ryan Huang, Jingang Wu:
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 336-340 (2016) - 2013
- [j4]Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, Fanjie Xiao, Gang Chen, Shuliu Xu, Yufeng Xie, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. IEEE J. Solid State Circuits 48(5): 1315-1322 (2013) - 2012
- [j3]Yufeng Xie, Wenxiang Jian, Xiaoyong Xue, Gang Jin, Yinyin Lin:
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. IEICE Electron. Express 9(12): 1051-1056 (2012) - 2011
- [j2]Xiaoyong Xue, Yufeng Xie, Yinyin Lin:
Novel 2T programmable element to improve density and performance of FPGA. IEICE Electron. Express 8(7): 454-459 (2011) - [c2]Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin:
A BIST scheme for high-speed Gain Cell eDRAM. ASICON 2011: 244-247 - [c1]Xiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin:
Novel RRAM programming technology for instant-on and high-security FPGAs. ASICON 2011: 291-294 - 2010
- [j1]Ji Zhang, Yiqing Ding, Xiaoyong Xue, Gang Jin, Yuxin Wu, Yufeng Xie, Yinyin Lin:
A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. IEICE Trans. Electron. 93-C(12): 1692-1699 (2010)
Coauthor Index
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