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ORCIDChenyang Zhao 0008
Person information
- affiliation: Fudan University, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
Other persons with the same name
- Chenyang Zhao — disambiguation page
- Chenyang Zhao 0001
![[0000-0002-9096-4094]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9096-4094")
— Harbin Institute of Technology at Shenzhen, School of Robotics and Advanced Manufacture, China (and 1 more) - Chenyang Zhao 0002 — Taiyuan Institute of Technology, Department of Electronic Engineering, China (and 1 more)
- Chenyang Zhao 0003 — Ruhr University Bochum, Department of Civil and Environmental Engineering, Germany
- Chenyang Zhao 0004 — Wuhan University of Technology, Intelligent Transportation Systems Research Center, China
- Chenyang Zhao 0005 — Beijing University of Posts and Telecommunications, State Key Laboratory of Networking and Switching Technology, China
- Chenyang Zhao 0006 — Xi'an Jiaotong University, School of Cyber Science and Engineering, China
- Chenyang Zhao 0007 — Research Center for Applied Mathematics and Machine Intelligence, Zhejiang Lab, Hangzhou, China
- Chenyang Zhao 0009 — Nankai University, College of Artificial Intelligence, Tianjin, China
- Chenyang Zhao 0010 — University of Southern California, School of Medicine, Department of Biomedical Engineering, Los Angeles, CA, USA
- Chenyang Zhao 0011 — Hong Kong University of Science and Technology, Department of Computer Science, Hong Kong (and 1 more)
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2020 – today
- 2025
[j8]Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng:
Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(2): 602-612 (2025)- 2024
- [j7]Chenyang Zhao, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang, Jiawei Wang, Jianguo Yang, Jun Han, Peng Zhou, Xiaoyong Xue, Xiaoyang Zeng:
A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications. IEEE J. Solid State Circuits 59(10): 3277-3289 (2024) - [c2]Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng:
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC 2024: 551-556 - 2023
- [j6]Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng:
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 986-999 (2023) - [j5]Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng:
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 364-377 (2023) - [j4]Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng:
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 276-280 (2023) - [j3]Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng:
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2645-2649 (2023) - 2022
- [j2]Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu:
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 846-857 (2022) - 2021
- [j1]Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng:
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2932-2936 (2021) - [c1]Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Zhiwang Guo, Xiaoyong Xue, Xiaoyang Zeng:
Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications. ASICON 2021: 1-4
Coauthor Index
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