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ORCIDXin Lou 0002
Person information
- affiliation: ShanghaiTech University, Shanghai, China
Other persons with the same name
- Xin Lou — disambiguation page
- Xin Lou 0001
![[0000-0001-7196-9861]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-7196-9861")
— ShanghaiTech University, Shanghai, China - Xin Lou 0003 — Virginia Tech, Blacksburg, VA, USA
- Xin Lou 0004 — PLA General Hospital, Beijing, China
- Xin Lou 0005 — Singapore Institute of Technology, Singapore
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2020 – today
- 2024
[j28]Shengyu Gao, Jianru Zhang, Yexing Hu, Yanan Wu, Linlin Li, Qian Hu, Xin Lou, Xingjun Zhu, Jiahua Jiang, Wuwei Ren:
Multifunctional Optical Tomography System With High-Fidelity Surface Extraction Based on a Single Programmable Scanner and Unified Pinhole Modeling. IEEE Trans. Biomed. Eng. 71(4): 1391-1403 (2024)- [j27]Ling Zhang, Haoyan Li, Xiangyu Zhang, Xin Lou:
RAW Images-Based Motion-Assisted Object Detection Accelerator Using Deformable Parts Models Features on 1080p Videos. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5054-5066 (2024) - [j26]Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wenbin Ye, Xin Lou:
FPGA Accelerator for Human Activity Recognition Based on Radar. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1441-1445 (2024) - [j25]Junran Ding, Yunxiang He, Binzhe Yuan, Zhechen Yuan, Pingqiang Zhou, Jingyi Yu, Xin Lou:
Ray Reordering for Hardware-Accelerated Neural Volume Rendering. IEEE Trans. Circuits Syst. Video Technol. 34(11): 11413-11422 (2024) - [c21]Yuhan Gu, Qing Wu, Zhechen Yuan, Xiangyu Zhang, Wenyan Su, Yuyao Zhang, Xin Lou:
An FPGA Accelerator for 3D Cone-beam Sparse-view Computed Tomography Reconstruction. AICAS 2024: 577-581 - [c20]Hongyu Wang, Xiangyu Zhang, Xin Lou:
A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing. ISCAS 2024: 1-5 - 2023
- [j24]Chaolin Rao, Qing Wu, Pingqiang Zhou, Jingyi Yu, Yuyao Zhang, Xin Lou:
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1625-1638 (2023) - [j23]Kangjie Long, Chaolin Rao, Yunxiang He, Zhechen Yuan, Pingqiang Zhou, Jingyi Yu, Xin Lou:
Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4260-4270 (2023) - [j22]Ling Zhang, Chaolin Rao, Xin Lou:
Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 3169-3173 (2023) - [c19]Mengchuan Dong, Wei Zhou, Cong Pang, Xiangyu Zhang, Xin Lou:
Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping. AICAS 2023: 1-5 - [c18]Haoyan Li, Wei Zhou, Xiangyu Zhang, Xin Lou:
An Efficient Frequency Domain Vision Pipeline From RAW Images to Backend Tasks. ISCAS 2023: 1-5 - 2022
- [j21]Guoji Lai, Xin Lou, Wenbin Ye:
Radar-Based Human Activity Recognition With 1-D Dense Attention Network. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j20]Deyang Jiang, Xiaochun Liu, Jianwen Luo, Zhengpeng Liao, Andreas Velten, Xin Lou:
Ring and Radius Sampling Based Phasor Field Diffraction Algorithm for Non-Line-of-Sight Reconstruction. IEEE Trans. Pattern Anal. Mach. Intell. 44(11): 7841-7853 (2022) - [j19]Tong Ma, Ying Wei, Xin Lou:
Reconfigurable Nonuniform Filter Bank for Hearing Aid Systems. IEEE ACM Trans. Audio Speech Lang. Process. 30: 758-771 (2022) - [j18]Jianhua Geng, Sifan Wang, Qinglai Liu, Xin Lou:
Multi-Level Time-Frequency Bins Selection for Direction of Arrival Estimation Using a Single Acoustic Vector Sensor. IEEE ACM Trans. Audio Speech Lang. Process. 30: 1048-1060 (2022) - [j17]Xue Xian Zheng, Zhengpeng Liao, Ying Wei, Xiu Yin Zhang, Xin Lou:
Design of FRM-Based Nonuniform Filter Bank With Reduced Effective Wordlength for Hearing Aids. IEEE Trans. Biomed. Circuits Syst. 16(6): 1216-1227 (2022) - [j16]Xiangyu Zhang, Ling Zhang, Xin Lou:
A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 322-333 (2022) - [j15]Zhengpeng Liao, Deyang Jiang, Xiaochun Liu, Andreas Velten, Yajun Ha, Xin Lou:
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 721-734 (2022) - [j14]Hongyu Wang, Wei Zhou, Xiangyu Zhang, Xin Lou:
A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2893-2905 (2022) - [c17]Kangjie Long, Chaolin Rao, Xiangyu Zhang, Wen Bin Ye, Xin Lou:
FPGA Accelerator for Radar-Based Human Activity Recognition. AICAS 2022: 391-394 - [c16]Hongyu Wang, Wei Zhou, Xiangyu Zhang, Xin Lou:
A 39pJ/label 1920x1080 165.7 FPS Block PatchMatch Based Stereo Matching Processor on FPGA. CICC 2022: 1-2 - [c15]Andrey Ignatov, Radu Timofte, Shuai Liu, Chaoyu Feng, Furui Bai, Xiaotao Wang, Lei Lei, Ziyao Yi, Yan Xiang, Zibin Liu, Shaoqing Li, Keming Shi, Dehui Kong, Ke Xu, Minsu Kwon, Yaqi Wu, Jiesi Zheng, Zhihao Fan, Xun Wu, Feng Zhang, Albert No, Minhyeok Cho, Zewen Chen, Xiaze Zhang, Ran Li, Juan Wang, Zhiming Wang, Marcos V. Conde, Ui-Jin Choi, Georgy Perevozchikov, Egor I. Ershov, Zheng Hui, Mengchuan Dong, Xin Lou, Wei Zhou, Cong Pang, Haina Qin, Mingxuan Cai:
Learned Smartphone ISP on Mobile GPUs with Deep Learning, Mobile AI & AIM 2022 Challenge: Report. ECCV Workshops (3) 2022: 44-70 - [c14]Ling Zhang, Wei Zhou, Xiangyu Zhang, Xin Lou:
An End-to-end Computer Vision System Architecture. ISCAS 2022: 2338-2342 - [i1]Andrey Ignatov, Radu Timofte, Shuai Liu, Chaoyu Feng, Furui Bai, Xiaotao Wang, Lei Lei, Ziyao Yi, Yan Xiang, Zibin Liu, Shaoqing Li, Keming Shi, Dehui Kong, Ke Xu, Minsu Kwon, Yaqi Wu, Jiesi Zheng, Zhihao Fan, Xun Wu, Feng Zhang, Albert No, Minhyeok Cho, Zewen Chen, Xiaze Zhang, Ran Li, Juan Wang, Zhiming Wang, Marcos V. Conde, Ui-Jin Choi, Georgy Perevozchikov, Egor I. Ershov, Zheng Hui, Mengchuan Dong, Xin Lou, Wei Zhou, Cong Pang, Haina Qin, Mingxuan Cai:
Learned Smartphone ISP on Mobile GPUs with Deep Learning, Mobile AI & AIM 2022 Challenge: Report. CoRR abs/2211.03885 (2022) - 2021
- [j13]Shengyu Gao, Hongyu Wang, Xin Lou:
A Low-Complexity End-to-End Stereo Matching Pipeline From Raw Bayer Pattern Images to Disparity Maps. IEEE Access 9: 47786-47794 (2021) - [j12]Jianping Zhu, Xin Lou, Wenbin Ye:
Lightweight Deep Learning Model in Mobile-Edge Computing for Radar-Based Human Activity Recognition. IEEE Internet Things J. 8(15): 12350-12359 (2021) - [j11]Wei Zhou, Ling Zhang, Shengyu Gao, Xin Lou:
Gradient-Based Feature Extraction From Raw Bayer Pattern Images. IEEE Trans. Image Process. 30: 5122-5137 (2021) - [c13]Shengyu Gao, Hongyu Wang, Teng Wang, Yang Wang, Xiangyu Zhang, Xin Lou:
Motion Assisted Video-based Stereo Matching. APCCAS 2021: 57-60 - [c12]Wangchao Liu, Teng Wang, Yang Wang, Xiangyu Zhang, Xin Lou:
Stereo Point Cloud Refinement for 3D Object Detection. APCCAS 2021: 61-64 - [c11]Jianhua Geng, Sifan Wang, Juan Li, Jingwei Li, Xiangyu Zhang, Xin Lou:
Robust Multi-Source Direction of Arrival Estimation Using a Single Acoustic Vector Sensor. APCCAS 2021: 161-164 - [c10]Hongyu Wang, Shengyu Gao, Teng Wang, Yang Wang, Xin Lou:
Multi-Scale Slanted O(1) Stereo Matching Algorithm. ISCAS 2021: 1-5 - [c9]Xiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou:
Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds. ISOCC 2021: 264-265 - 2020
- [j10]Wei Zhou, Shengyu Gao, Ling Zhang, Xin Lou:
Histogram of Oriented Gradients Feature Extraction From Raw Bayer Pattern Images. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 946-950 (2020) - [j9]Wangqian Chen, Mo Huang, Wen Bin Ye, Xin Lou:
Cascaded Form Sparse FIR Filter Design. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1692-1703 (2020) - [c8]Ling Zhang, Wei Zhou, Jingwei Li, Juan Li, Xin Lou:
Histogram of Oriented Gradients Feature Extraction Without Normalization. APCCAS 2020: 252-255
2010 – 2019
- 2019
- [j8]Wangqian Chen, Mo Huang, Xin Lou:
Design of Sparse FIR Filters With Reduced Effective Length. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1496-1506 (2019) - 2018
- [c7]Shiting Li, Wenbin Ye, Huawei Liang, Xiaofang Pan, Xin Lou, Xiaojin Zhao:
K-SVD Based Denoising Algorithm for DoFP Polarization Image Sensors. ISCAS 2018: 1-5 - 2017
- [j7]Wen Bin Ye, Xin Lou, Ya Jun Yu:
Design of Low-Power Multiplierless Linear-Phase FIR Filters. IEEE Access 5: 23466-23472 (2017) - [j6]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 313-324 (2017) - [j5]Pramod Kumar Meher, Xin Lou:
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 399-408 (2017) - [j4]Xin Lou, Pramod Kumar Meher, Yajun Yu, Wenbin Ye:
Novel Structure for Area-Efficient Implementation of FIR Filters. IEEE Trans. Circuits Syst. II Express Briefs 64-II(10): 1212-1216 (2017) - [c6]Xin Lou, Wenbin Ye:
Low complexity and low power multiplierless FIR filter implementation. ASICON 2017: 596-599 - [c5]Xin Lou, Wenbin Ye, Ya Jun Yu:
Investigation on power consumption of product accumulation block for multiplierless FIR filters. DSP 2017: 1-5 - [c4]Yong Wang, Yan Hong, Wang Ling Goh, Kevin T. C. Chai, Xin Lou, Wen Bin Ye:
A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization. ISCAS 2017: 1-4 - 2016
- [j3]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1701-1713 (2016) - 2015
- [j2]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 863-872 (2015) - [j1]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2695-2705 (2015) - [c3]Xin Lou, Pramod Kumar Meher, Ya Jun Yu:
Fine-grained pipelining for multiple constant multiplications. ISCAS 2015: 966-969 - [c2]Wen Bin Ye, Xin Lou, Ya Jun Yu:
Design of high-speed multiplierless linear-phase FIR filters. ISCAS 2015: 2964-2967 - 2014
- [c1]Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
High-speed multiplier block design based on bit-level critical path optimization. ISCAS 2014: 1308-1311
Coauthor Index
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