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ORCIDACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13
Volume 13, Number 1, January 2008
- Nikil D. Dutt
:
Editorial. 1:1 - Michael S. Hsiao, Robert B. Jones:
Introduction to special section on high-level design, validation, and test. 2:1 - Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer:
Boosting interpolation with dynamic localized abstraction and redundancy removal. 3:1-3:20 - Marc Boule, Zeljko Zilic:
Automata-based assertion-checker synthesis of PSL properties. 4:1-4:21 - Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m). 5:1-5:18 - Sami Taktak, Jean Lou Desbarbieux, Emmanuelle Encrenaz:
A tool for automatic detection of deadlock in wormhole networks on chip. 6:1-6:22 - Hai Zhou:
A new efficient retiming algorithm derived by formal manipulation. 7:1-7:19 - Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. 8:1-8:35 - Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang:
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. 9:1-9:27 - F. Ryan Johnson, JoAnn M. Paul:
Interrupt modeling for efficient high-level scheduler design space exploration. 10:1-10:22 - Ümit Y. Ogras, Radu Marculescu:
Analysis and optimization of prediction-based flow control in networks-on-chip. 11:1-11:28 - Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen:
Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes. 12:1-12:31 - Ali Abbasian, Safar Hatami, Ali Afzali-Kusha, Massoud Pedram:
Wavelet-based dynamic power management for nonstationary service requests. 13:1-13:41 - Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang:
Synthesis of a novel timing-error detection architecture. 14:1-14:14 - Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf:
ReChannel: Describing and simulating reconfigurable hardware in systemC. 15:1-15:18 - Xiangrong Zhou, Chenjie Yu, Alokika Dash, Peter Petrov:
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors. 16:1-16:25 - Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Jun-hee Yoo, Kiyoung Choi, Xingguang Feng:
SoCDAL: System-on-chip design AcceLerator. 17:1-17:38 - Nicholas H. Zamora, Xiaoping Hu, Ümit Y. Ogras, Radu Marculescu:
Enabling multimedia using resource-constrained video processing techniques: A node-centric perspective. 18:1-18:27 - Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula:
A fuel-cell-battery hybrid for portable embedded systems. 19:1-19:34 - Wei-Chung Chao, Wai-Kei Mak:
Low-power gated and buffered clock network construction. 20:1-20:20 - Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou:
Optimizing wirelength and routability by searching alternative packings in floorplanning. 21:1-21:13 - Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai:
Chip placement in a reticle for multiple-project wafer fabrication. 22:1-22:21
Volume 13, Number 2, April 2008
- Nikil D. Dutt:
Editorial. 23:1 - Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri:
SAT-based ATPG using multilevel compatible don't-cares. 24:1-24:18 - Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang:
A noniterative equivalent waveform model for timing analysis in presence of crosstalk. 25:1-25:21 - Jin-Tai Yan:
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction. 26:1-26:18 - Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado:
An open-source binary utility generator. 27:1-27:17 - James Moscola, John W. Lockwood, Young H. Cho:
Reconfigurable content-based router using hardware-accelerated language parser. 28:1-28:25 - Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle:
Radio frequency identification prototyping. 29:1-29:22 - Yu Hu, Yan Lin, Lei He, Tim Tuan:
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. 30:1-30:29 - Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev:
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration. 31:1-31:21 - Xiangrong Zhou, Peter Petrov:
Heterogeneously tagged caches for low-power embedded systems with virtual memory support. 32:1-32:24 - Fang Liu, Sule Ozev, Plamen K. Nikolov:
Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling. 33:1-33:28 - Lei Cheng, Deming Chen, Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. 34:1-34:15 - Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
The optimization of kEP-SOPs: Computational complexity, approximability and experiments. 35:1-35:31 - R. Iris Bahar, Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. 36:1-36:2
Volume 13, Number 3, July 2008
- Nikil D. Dutt:
Editorial. 37:1-37:2 - Alex K. Jones, Robert Walker:
Introduction to the special section on demonstrable software systems and hardware platforms II. 38:1-38:3 - Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek:
A retargetable parallel-programming framework for MPSoC. 39:1-39:18 - Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal:
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. 40:1-40:27 - Ronny Krashinsky, Christopher Batten, Krste Asanovic:
Implementing the scale vector-thread processor. 41:1-41:24 - Prabhat Mishra, Nikil D. Dutt:
Specification-driven directed test generation for validation of pipelined processors. 42:1-42:36 - Yongsoo Joo, Youngjin Cho, Donghwa Shin, Jaehyun Park, Naehyuck Chang:
An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory. 43:1-43:29 - Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood:
Designing secure systems on reconfigurable hardware. 44:1-44:24 - Panagiotis Manolios, Sudarshan K. Srinivasan:
Automatic verification of safety and liveness for pipelined machines using WEB refinement. 45:1-45:19 - Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti:
Postplacement voltage assignment under performance constraints. 46:1-46:20 - Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow. 47:1-47:22 - Hiroaki Inoue, Junji Sakai, Masato Edahiro:
Processor virtualization for secure mobile terminals. 48:1-48:23 - Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor:
Combining system scenarios and configurable memories to tolerate unpredictability. 49:1-49:7 - Ozcan Ozturk, Mahmut T. Kandemir:
ILP-Based energy minimization techniques for banked memories. 50:1-50:40 - Sabyasachi Das, Sunil P. Khatri:
Resource sharing among mutually exclusive sum-of-product blocks for area reduction. 51:1-51:7 - I-Lun Tseng, Adam Postula:
Partitioning parameterized 45-degree polygons with constraint programming. 52:1-52:29 - Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Power-aware SoC test planning for effective utilization of port-scalable testers. 53:1-53:19 - Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek:
Evolution of synthetic RTL benchmark circuits with predefined testability. 54:1-54:21
Volume 13, Number 4, September 2008
- Massoud Pedram:
Editorial. 55:1-55:3 - Nan Guan, Qingxu Deng, Zonghua Gu, Wenyao Xu, Ge Yu:
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs. 56:1-56:43 - Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal:
A high-level clustering algorithm targeting dual Vdd FPGAs. 57:1-57:20 - Javier Resano, Juan Antonio Clemente, Carlos González, Daniel Mozos, Francky Catthoor:
Efficiently scheduling runtime reconfigurations. 58:1-58:12 - Siddharth Garg, Diana Marculescu:
System-level throughput analysis for process variation aware multiple voltage-frequency island designs. 59:1-59:25 - Ozcan Ozturk, Mahmut T. Kandemir, Guangyu Chen:
Access pattern-based code compression for memory-constrained systems. 60:1-60:30 - Nastaran Baradaran, Pedro C. Diniz:
A compiler approach to managing storage and memory bandwidth in configurable architectures. 61:1-61:26 - Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti:
Auxiliary state machines + context-triggered properties in verification. 62:1-62:31 - Subrat Kumar Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar:
Simulation-based verification using Temporally Attributed Boolean Logic. 63:1-63:52 - Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li:
Layout-aware scan chain reorder for launch-off-shift transition test coverage. 64:1-64:16 - Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Timing-aware power-optimal ordering of signals. 65:1-65:17 - Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
Effective decap insertion in area-array SoC floorplan design. 66:1-66:20 - Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack:
Constraint-driven floorplan repair. 67:1-67:13 - Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules. 68:1-68:20
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