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ORCIDACM Transactions on Embedded Computing Systems, Volume 24
Volume 24, Number 1, January 2025
- Junqiang Jiang
, Shengjie Jin, Zhifang Sun, Jinxue Duan, Lizhi Liu, Li Pan, Zebo Peng:
An Efficient Approach for Improving Message Acceptance Rate and Link Utilization in Time-Sensitive Networking. 1:1-1:25 - Sofiya Semenova, Steven Y. Ko, Yu David Liu, Lukasz Ziarek, Karthik Dantu:
A Comprehensive Study of Systems Challenges in Visual Simultaneous Localization and Mapping Systems. 2:1-2:31 - Zhuoqun Xia, Ziyu Wang, Xiao Liu:
Trust Based Active Game Data Collection Scheme in Smart Cities. 3:1-3:23 - Gao-Yu Lin, Po-Yuan Wang, Shin-Ming Cheng, Hahn-Ming Lee:
Improving Robustness in IoT Malware Detection through Execution Order Analysis. 4:1-4:17 - Thomas Garbay, Khalil Hachicha, Petr Dobiás, Andréa Pinna, Karim Hocine, Wilfried Dron, Pedro Lusich, Imane Khalis, Bertrand Granado:
ZIP-CNN: Design Space Exploration for CNN Implementation within a MCU. 5:1-5:26 - Mohammad Rafiuzzaman, Sathish Gopalakrishnan, Karthik Pattabiraman:
Co-Approximator: Enabling Performance Prediction in Colocated Applications. 6:1-6:28 - Kam-Yiu Lam, Xiaofei Zhao, Chunjiang Zhu, Tei-Wei Kuo:
MVLevelDB+: Meeting Relative Consistency Requirements of Temporal Queries in Sensor Stream Databases. 7:1-7:26 - Thilo Leon Fischer, Heiko Falk:
Towards Analysing Cache-Related Preemption Delay in Non-Inclusive Cache Hierarchies. 8:1-8:37 - Yann Argotti, Yasmine Kenfaoui, Claude Baron, Alain Abran, Philippe Esteban:
An Operational Quality Model of Embedded Software Aligned with ISO 25000. 9:1-9:41 - Suparna Kundu, Quinten Norga, Angshuman Karmakar, Shreya Gangopadhyay, Jose Maria Bermudo Mera, Ingrid Verbauwhede:
Scabbard: An Exploratory Study on Hardware Aware Design Choices of Learning with Rounding-based Key Encapsulation Mechanisms. 10:1-10:40 - Shikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan:
EXPRESS: A Framework for Execution Time Prediction of Concurrent CNNs on Xilinx DPU Accelerator. 11:1-11:31 - Mahendra Rathor:
ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer. 12:1-12:26 - Héctor Pérez Tijero, José Javier Gutiérrez García, Diego García-Prieto:
Application-Level Evaluation of IEEE 802.1AS Synchronized Time and Linux for Distributed Real-Time Systems. 13:1-13:16 - Abdullah M. Zyarah, Dhireesha Kudithipudi:
Time-Series Forecasting and Sequence Learning Using Memristor-based Reservoir System. 14:1-14:17 - Suhap Sahin, Oguz Narli, Bahadir Turkoglu, Hikmetcan Ozcan:
Hardware Area Efficient and Real-Time FPGA Implementation of PHMMRGB. 15:1-15:20 - Pengzhou He, Yazheng Tu, Tianyou Bao, Çetin Çetin Koç, Jiafeng Xie:
HSPA: High-Throughput Sparse Polynomial Multiplication for Code-based Post-Quantum Cryptography. 16:1-16:24 - Sezana Fahmida, Aakriti Jain, Venkata Prashant Modekurthy, Dali Ismail, Abusayeed Saifullah:
RTPL: A Real-Time Communication Protocol for LoRa Network. 17:1-17:31 - Liangliang Chang, Serhan Gener, Joshua Mack, Hasan Umut Suluhan, Ali Akoglu, Chaitali Chakrabarti:
Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded System. 18:1-18:32 - Soonhoi Ha, Eunjin Jeong:
Software Optimization and Design Methodology for Low Power Computer Vision Systems. 19:1-19:31 - Joshua Mack, Anish Krishnakumar, Ümit Y. Ogras, Ali Akoglu:
Tutorial: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures. 20:1-20:24 - Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Guochu Xiong, Weichen Liu:
Efficient Deep Learning Infrastructures for Embedded Computing Systems: A Comprehensive Survey and Future Envision. 21:1-21:100 - Mario Günzel, Harun Teper, Georg von der Brüggen, Jian-Jia Chen:
End-To-End Latency of Cause-Effect Chains: A Tutorial. 22:1-22:18
Volume 24, Number 2, March 2025
- Chen-Fong Hsu, Hong-Sheng Zheng, Yu-Yuan Liu, Tsung Tai Yeh:
StreamNet++: Memory-Efficient Streaming TinyML Model Compilation on Microcontrollers. 23:1-23:26 - Shihang Zhou, Alejandra C. Hernández, Clara Gómez, Wenjie Yin, Mårten Björkman:
SmartTBD: Smart Tracking for Resource-constrained Object Detection. 24:1-24:19 - Ziying Ni, Ayesha Khalid, Weiqiang Liu, Máire O'Neill:
A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers. 25:1-25:24 - Zhengyuan Shi, Cheng Chen, Gangqiang Yang, Hongchao Zhou, Hailiang Xiong, Zhiguo Wan:
Customized FPGA Implementation of Authenticated Lightweight Cipher Fountain for IoT Systems. 26:1-26:26 - Kevin Hutto, Vincent J. Mooney:
Implementing Privacy Homomorphism with Random Encoding and Computation Controlled by a Remote Secure Server. 27:1-27:27 - Sagar Dev Achar, Thejaswini P, Sukumar Nandi, Sunit Nandi:
LiteHash: Hash Functions for Resource-Constrained Hardware. 28:1-28:17 - Shih-Wen Hsu, Yen-Ting Chen, Kam-Yiu Lam, Yuan-Hao Chang, Wei-Kuan Shih, Han-Chieh Chao:
APB-tree: An Adaptive Pre-built Tree Indexing Scheme for NVM-based IoT Systems. 29:1-29:31 - Jungyoon Kwon, Hyemi Min, Bernhard Egger:
SENNA: Unified Hardware/Software Space Exploration for Parametrizable Neural Network Accelerators. 30:1-30:26 - Francesco Ratti, Johannes Knödtel, Marc Reichenbach:
HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing Cost. 31:1-31:50 - Saeed Aghapour, Kasra Ahmadi, Mila Anastasova, Reza Azarderakhsh, Mehran Mozaffari Kermani:
PUF-Dilithium: Design of a PUF-Based Dilithium Architecture Benchmarked on ARM Processors. 32:1-32:20 - Daniel Dobkin, Nimrod Cever, Itamar Levi:
RAD-FS: Remote Timing and Power SCA Security in DVFS-augmented Ultra-Low-Power Embedded Systems. 33:1-33:27 - Jong-Yeon Park, Seonggyeom Kim, Wonil Lee, Bo Gyeong Kang, Il-Jong Song, Jaekeun Oh, Kouichi Sakurai:
A Compact and Parallel Swap-Based Shuffler Based on Butterfly Network and Its Complexity Against Side Channel Analysis. 34:1-34:40 - Yang Liu, Zihan Wang, Mengchi Cai, Qing Xu, Keqiang Li:
A Hybrid Target Selection Model of Functional Safety Compliance for Autonomous Driving System. 35:1-35:27 - Konstantin Lübeck, Alexander Louis-Ferdinand Jung, Felix Wedlich, Mika Markus Müller, Federico Nicolás Peccia, Felix Thömmes, Jannik Steinmetz, Valentin Biermaier, Adrian Frischknecht, Paul Palomero Bernardo, Oliver Bringmann:
Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators. 36:1-36:32
Volume 24, Number 3, May 2025
- Wangyang Yu, Qi Guo, Yumeng Cheng, Lu Liu, Fei Hao, Xiaojun Zhai, Minsi Chen:
Formal Modeling of Hybrid System Based on Semi-continuous Colored Petri Net: A Case Study of Adaptive Cruise Control System. 37:1-37:21 - Jingjing Chang, Peining Zhen, Xiaotao Yan, Yixin Yang, Ziyang Gao, Haibao Chen:
MemATr: An Efficient and Lightweight Memory-augmented Transformer for Video Anomaly Detection. 38:1-38:26 - Zain Taufique, Anil Kanduri, Antonio Miele, Amir M. Rahmani, Cristiana Bolchini, Nikil D. Dutt, Pasi Liljeberg:
Exploiting Approximation for Run-time Resource Management of Embedded HMPs. 39:1-39:30 - Qiong Chang, Xinyuan Chen, Xiang Li, Weimin Wang, Jun Miyazaki:
Faster than Fast: Accelerating Oriented FAST Feature Detection on Low-end Embedded GPUs. 40:1-40:22 - Zahra Ramezani, Kenan Sehic, Luigi Nardi, Knut Åkesson:
Falsification of Cyber-physical Systems Using Bayesian Optimization. 41:1-41:23 - Zhiyong Tao, Zhelun Wang, Ying Liu, Yuqing He, Yikai Wang:
Wireless Perceptual Space Modeling Method for Cross-Domain Human Activity Recognition. 42:1-42:20 - Bokyung Kim, Shiyu Li, Brady Taylor, Yiran Chen:
Efficient and Robust Edge AI: Software, Hardware, and the Co-design. 43:1-43:34
- Jens Brandt, Indranil Saha, Lijun Zhang:
Introduction to the Special Issue on Formal Methods and Models for System Design. 44:1-44:3 - Alexandre Honorat, Hai Nam Tran, Thierry Gautier, Loïc Besnard, Shuvra S. Bhattacharyya, Jean-Pierre Talpin:
Real-time Fixed Priority Scheduling Synthesis Using Affine DataFlow Graphs: from Theory to Practice. 45:1-45:31 - Bastien Sultan, Léon Frénot, Ludovic Apvrille, Philippe Jaillon, Sophie Coudert:
AMULET: A Mutation Language Enabling Automatic Enrichment of SysML Models. 46:1-46:28 - Sung Woo Choi, Mykhailo Ivashchenko, Luan Viet Nguyen, Hoang-Dung Tran:
Reachability Analysis of Sigmoidal Neural Networks. 47:1-47:25 - Anup Das:
Design Flow for Scheduling Spiking Deep Convolutional Neural Networks on Heterogeneous Neuromorphic System-on-chip. 48:1-48:30 - Navin Kumar, Sandeep K. Sood, Munish Saini:
IoV-Fog-Assisted Framework for Accident Detection and Classification. 49:1-49:19 - Abhinandan Panda, Srinivas Pinisetty, Partha S. Roop:
Securing Pacemakers Using Runtime Monitors over Physiological Signals. 50:1-50:41 - Hugo Valente, Miguel A. de Miguel, Ángel-Grover Pérez-Muñoz, Alejandro Alonso, Juan Zamorano, Juan Antonio de la Puente:
Model-based Toolchain for Core Flight System (cFS) Embedded Systems. 51:1-51:28 - Ruiqi Hu, Kairong Liu, Zhikun She:
Evolution Function Based Reach-Avoid Verification for Time-varying Systems with Disturbances. 52:1-52:30
Volume 24, Number 4, July 2025
- Yiwen Zhang, Rong-Kun Chen:
Energy-Efficient Partitioned-RM Scheduling for Shared Resources Imprecise Mixed-Criticality Tasks. 53:1-53:30 - Chunlin Li, Sen Liu, Kun Jiang, Mengjie Yang, Zihao Zhang, Bingxin Wang, Liang Zhao, Chen Chen, Shaohua Wan:
DNN Inference Acceleration Based on Adaptive Task Partitioning and Offloading in Embedded VEC. 54:1-54:35 - Zihao Zhao, Yanhong Wang, Xu Jin, Haotian Zheng, Maohua Nie, Longfei Gou, Junmin He, Yongchuan Dong, Qiaosha Zou, Yiyun Zhang, C.-J. Richard Shi:
A Workload-Balance-Aware Accelerator Enabling Dense-to-Arbitrary-Sparse Neural Networks. 55:1-55:25 - Renshuang Jiang, Pan Dong, Yan Ding, Ran Wei, Zhe Jiang:
Thetis-lathe: Guidance on Reducing Residual Safety Obstacle in System Software from Rust Source Codes. 56:1-56:25 - Karan Pathak, Joshua Alexander Harrison Klein, Giovanni Ansaloni, Said Hamdioui, Georgi Gaydadjiev, Marina Zapater, David Atienza:
Towards Accurate RISC-V Full System Simulation via Component-Level Calibration. 57:1-57:19 - Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Efficient Implementation of LinearUCB through Algorithmic Improvements and Vector Computing Acceleration for Embedded Learning Systems. 58:1-58:23 - Cuiping Shao, Wenzhe Li, Huiyun Li, Zhimin Tang, Jianing Liang:
A Novel Lattice-Based Fault Injection Attack Targeting the Nonce in the SM2 Digital Signature Algorithm. 59:1-59:21 - Joan Miquel Solé, Roger Pueyo Centelles, Felix Freitag, Roc Meseguer, Roger Baig:
Middleware for Distributed Applications in a LoRa Mesh Network. 60:1-60:26 - Ying Liu, Zhiyang Cao, Jiaqi Cai, Yuqing He, Mingzhe Hu:
Wi-GPD Identification System Based on Gait Point Density. 61:1-61:24 - Qingbin Wang, Yuchen Pei, Wai Chon Wong, Xuefeng Mu, Yan Zhang, Yutao Ma:
Activation Map-based Knowledge Distillation for Real-time Cervical OCT Image Classification. 62:1-62:27 - Owen Le Gonidec, Guillaume Bouffard, Jean-Christophe Prévotet, Maria Méndez Real:
Do Not Trust Power Management: A Survey on Internal Energy-based Attacks Circumventing Trusted Execution Environments Security Properties. 63:1-63:35
Volume 24, Number 5, September 2025
- Michael Tempelmeier, Fabrizio De Santis, Shivam Bhasin, Stefan Mangard:
Special Issue on Open Hardware for Embedded System Security and Cryptography. 64:1-64:3 - Kamyar Mohajerani, Luke Beckwith, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process. 65:1-65:25 - Patrick Karl, Jonas Schupp, Georg Sigl:
Performance and Communication Cost of Hardware Accelerators for Hashing in Post-Quantum Cryptography. 66:1-66:31 - Maicol Ciani, Emanuele Parisi, Alberto Musa, Francesco Barchi, Andrea Bartolini, Ari Kulmala, Rafail Psiakis, Angelo Garofalo, Andrea Acquaviva, Davide Rossi:
Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading. 67:1-67:29 - Vatistas Kostalabros, Jordi Ribes-González, Xavier Carril, Oriol Farràs, Carles Hernández, Miquel Moretó:
Leveraging HLS to Design a Versatile & High-Performance Classic McEliece Accelerator. 68:1-68:27 - Sanjay Deshpande, Yongseok Lee, Cansu Karakuzu, Jakub Szefer, Yunheung Paek:
SPHINCSLET: An Area-Efficient Accelerator for the Full SPHINCS+ Digital Signature Algorithm. 69:1-69:19 - Tommaso Sacchetti, Marton Bognar, Jesse De Meulemeester, Benedikt Gierlichs, Frank Piessens, Volodymyr Bezsmertnyi, Maria Chiara Molteni, Stefano Cristalli, Arianna Gringiani, Olivier Thomas, Daniele Antonioli:
AttackDefense Framework (ADF): Enhancing IoT Devices and Lifecycles Threat Modeling. 70:1-70:34 - Mohamed El Bouazzati, Philippe A. Tanguy, Guy Gogniat, Russell Tessier:
Diwall: A Lightweight Host Intrusion Detection System Against Jamming and Packet Injection Attacks. 71:1-71:30 - Ashish Mahanta, Haibo Wang:
Abnormality Detection Using Power Rising and Descending Signature (PRIDES). 72:1-72:18 - Zheng Wu, Lin Ding, Zhengting Li, Xinhai Wang, Ziyu Guan:
Side Channel Attacks on GPRS Standard Encryption Algorithms. 73:1-73:16 - Yongliang Chen, Xiaole Cui, Sunrui Zhang, Xiaoxin Cui:
A VC Dimension-Oriented Improvement Method of PUFs for the Anti-Modeling-Attack Capability. 74:1-74:30 - Naina Gupta, Arpan Jati, Anupam Chattopadhyay:
AI Attacks AI: Recovering Neural Network Architecture from NVDLA Using AI-Assisted Side Channel Attack. 75:1-75:29 - Xinpeng Hao, Xiangxue Li:
FirmCAN: Sensitive CAN Knowledge Leakage from Automotive ECUs. 76:1-76:24
- Maria Doglioni, Eren Yildiz, Matteo Nardello, Khakim Akhunov, Kasim Sinan Yildirim, Davide Brunelli:
CapDYN: Adaptive Self-Scaling Energy Storage for Powering Batteryless IoT. 77:1-77:32 - Liang Xu, Hongrui Song, Lan Tian, Zhongfeng Wang, Meiqi Wang:
TAFP-ViT: A Transformer Accelerator via QKV Computational Fusion and Adaptive Pruning for Vision Transformer. 78:1-78:21 - Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Algorithm-Level Error Detection for Number-Theoretic Transform Used for Kyber Assessed on FPGAs and ARM. 79:1-79:23 - Theologos Anthimopoulos, Georgios Keramidas, Vasilios I. Kelefouras, Iakovos Stamoulis:
Register Blocking: A Source-to-Source Analytical Modelling Approach for Affine Loop Kernels. 80:1-80:24 - Aranya Gupta, Amit Surpur, Bishnu Prasad Das, Sanjeev Kumar Manhas:
A Unified Approach to a Secure and Lightweight Mutual Authentication Protocol Using Pre-Characterized COTS SRAM ICs for IoT Applications. 81:1-81:27 - Jon Gutiérrez-Zaballa, Koldo Basterretxea, Javier Echanobe:
Optimization of DNN-based HSI Segmentation FPGA-based SoC for ADS: A Practical Approach. 82:1-82:27 - Debarpita Banerjee, Sumana Ghosh:
P2SDS: A Polynomial-Time Pattern-Guided Stable Dynamic Scheduling for Weakly Hard Control Task Systems. 83:1-83:33
Volume 24, Number 5s, September 2025
CASES 2025
- Mohamed Fathy, Hassan Nassar, Mohamed A. Abd El Ghany, Jörg Henkel:
Timekeepers: ML-Driven SDF Analysis for Power-Wasters Detection in FPGAs. 84:1-84:26 - Gabriele Tombesi, Je Yang, Joseph Zuckerman, Davide Giri, William Baisi, Luca P. Carloni:
FLIP2M: Flexible Intra-layer Parallelism and Inter-layer Pipelining for Multi-model AR/VR Workloads. 85:1-85:27 - Zewei Lai, Jinhui Ye, Xiaohang Wang, Zheang Fu, Amit Kumar Singh, Yingtao Jiang, Kui Ren, Mei Yang, Sihai Qiu, Xiaodong Li, Xin Tang, Jie Song, Mingzhe Zhang:
On Improving the Performance of Intra- and Inter-chiplet Interconnection Networks in Multi-chiplet Systems for Accelerating FHE Encrypted Neural Network Applications. 86:1-86:25 - Dinesh Joshi, Aritra Bagchi, Preeti Ranjan Panda:
SHARP: SHARing-Aware Cache Writeback byPass. 87:1-87:25 - Priyanjana Pal, Tara Gheshlaghi, Haibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
PRINT-SAFE: Printed Ultra-Low-Cost Electronic X-Design with Scalable Adaptive Fault Endurance. 88:1-88:22 - Danish Gufran, Sudeep Pasricha:
GATE: Graph Attention Neural Networks with Real-Time Edge Construction for Robust Indoor Localization using Mobile Embedded Devices. 89:1-89:24 - Yashika Verma, Debadatta Mishra, Mainak Chaudhuri:
LeakyRand: An Efficient High-fidelity Covert Channel in Fully Associative Last-level Caches with Random Eviction. 90:1-90:29 - Serhan Gener, Aditya Ukarande, Shilpa Mysore Srinivasa Murthy, Md Sahil Hassan, Joshua Mack, Chaitali Chakrabarti, Ümit Y. Ogras, Ali Akoglu:
RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing. 91:1-91:24 - Yongin Kwon, JooHyoung Cha, Sehyeon Oh, Misun Yu, Jeman Park, Jemin Lee:
Luthier: Bridging Auto-Tuning and Vendor Libraries for Efficient Deep Learning Inference. 92:1-92:23 - Aruna Jayasena, Sai Suprabhanu Nallapaneni, Prabhat Mishra:
FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution. 93:1-93:24 - Szu-Wei Chen, Shuo-Han Chen:
Exploiting LDPC Syndrome for Multidimensional Hard-Decoding Read Retry on NAND Flash. 94:1-94:20 - Pratyush Dhingra, Chibuike E. Ugwu, Jana Doppa, Partha Pande:
ERGo: Energy-Efficient Hybrid Graph Neural Network Training on Processing-in-Memory Architectures. 95:1-95:25 - Harsh Sharma, Jana Doppa, Ümit Y. Ogras, Partha Pande:
Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures Enabled by Non-Bendable Glass Interposer. 96:1-96:28 - Chi-Chieh Hung, Yao-Yu Liao, Yi-Chao Shih, Tseng-Yi Chen:
ReLoaDing Performance: A Locality-Based Strategy for Rapid Reads in Encrypted Key-Value Systems. 97:1-97:25 - Guangliang Yao, Tsun-Yu Yang, Yingjia Wang, Tseng-Yi Chen, Ming-Chang Yang:
Large or Small: Harnessing the Erase Duality of Emerging Bit-Alterable NAND Flash to Suppress Tail Latency. 98:1-98:21 - Matchima Buddhanoy, Aleksandar Milenkovic, Sudeep Pasricha, Biswajit Ray:
Page-Overwrite Data Sanitization in 3D NAND Flash: Challenges, Feasibility, and the PULSE Solution. 99:1-99:26 - Logan Kenwright, Partha S. Roop, Nathan Allen, Calin Cascaval, Avinash Malik:
Timetide: A Programming Model for Logically Synchronous Distributed Systems. 100:1-100:25 - Zhijie Huang, Yulong Shi, Chengjia Zhao, Haoran Li, Nannan Zhao, Shujie Han, Xiao Zhang:
A Load-Balanced Collaborative Repair Algorithm for Single-Disk Failures in Erasure Coded Storage Systems. 101:1-101:18 - Gaurav Kumar, Kushal Pravin Nanote, Sohan Lal, Yamuna Prasad, Satyadev Ahlawat:
Robust LFSR-based Scrambling to Mitigate Stencil Attack on Main Memory. 102:1-102:22 - José Cubero-Cascante, Lucas Tonini Rosenberg Schneider, Rebecca Pelke, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph:
CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators. 103:1-103:22
CODES+ISSS 2025
- Chih-Hsuan Yen, Hashan Roshantha Mendis, Tei-Wei Kuo, Pi-Cheng Hsiu:
Catch Non-determinism If You Can: Intermittent Inference of Dynamic Neural Networks. 104:1-104:24 - Xiangfeng Liu, Zhe Jiang, Anzhen Zhu, Xiaomeng Han, Mingsong Lyu, Qingxu Deng, Nan Guan:
Re-thinking Memory-Bound Limitations in CGRAs. 105:1-105:26 - Zeming Ma, Jian Zhou, Yu Fu, Xiaochang Ma, Shuhan Bai, Fei Wu:
Lemonade: Learning-based Heterogeneous Metadata Offloading for Disaggregated Memory. 106:1-106:25 - Yongxiang Cao, Hongxu Jiang, Huiyong Li, Yu Tang, Dongcheng Shi, Guocheng Zhao:
HMSA: High-Performance Heterogeneous Mixed-Precision CNN Systolic Array Accelerator on FPGA. 107:1-107:27 - Yinjie Fang, Liping Yang, Weichen Liu, Guoquan Zhang, Yaoyao Gu, Xiang Xiao, Wei Qin, Xiangzhen Ouyang, Wanli Chang:
FT-DAG: An Efficient Full-Topology DAG Generator with Controllable Parameters. 108:1-108:25 - Zimeng Fan, Min Peng:
GNNmap: A Scalable Framework for GNN Deployment through Co-Optimized Graph Partitioning and Mapping. 109:1-109:25 - Jiyong Kim, Jaeho Lee, Jiahao Lin, Alish Kanani, Miao Sun, Ümit Y. Ogras, Jaehyun Park:
eMamba: Efficient Acceleration Framework for Mamba Models in Edge Computing. 110:1-110:22 - Rafael Medina Morillas, Pengbo Yu, Alexandre Levisse, Dwaipayan Biswas, Marina Zapater, Giovanni Ansaloni, Francky Catthoor, David Atienza:
SideDRAM: Integrating SoftSIMD Datapaths near DRAM Banks for Energy-Efficient Variable Precision Computation. 111:1-111:24 - Mohamed Alsharkawy, Hassan Nassar, Jeferson González-Gómez, Xun Xiao, Osama Abboud, Jörg Henkel:
DPReF: Decentralized Key Generation Using Physical-Related Functions. 112:1-112:24 - Surajit Das, Abhijit Das, Chandan Karfa:
Developing Deadlock-Free Routing Algorithms in Torus NoC: A Formal Approach. 113:1-113:26 - Yatharth Agarwal, Vijay Raghunathan:
SecuPilot: A Security Coprocessor-Integrated Platform for Autonomous UAV Security. 114:1-114:25 - Dean You, Jieyu Jiang, Xiaoxuan Wang, Yushu Du, Zhihang Tan, Wenbo Xu, Hui Wang, Jiapeng Guan, Ran Wei, Shuai Zhao, Zhe Jiang:
MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors. 115:1-115:26 - Gaurav Narang, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Krishnendu Chakrabarty, Partha Pratim Pande:
GINA: Exploiting Graph Neural Network Layer Features for Energy Efficient Inferencing in NVM-based PIM Accelerators. 116:1-116:26 - Mahta Mayahinia, Tommaso Marinelli, Zhenlin Pei, Hsiao-Hsuan Liu, Chenyun Pan, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori:
System Scenario-Based Design of the Last-Level Cache in Advanced Interconnect-Dominant Technology Nodes. 117:1-117:26 - Sumedh Shridhar Joshi, Hwisoo So, Soyeong Park, Woobin Ko, Jinhyo Jung, Yohan Ko, Uiwon Hwang, Kyoungwoo Lee, Aviral Shrivastava:
ProGIP: Protecting Gradient-based Input Perturbation Approaches for OOD Detection From Soft Errors. 118:1-118:25 - Lok Yin Chow, Yingjia Wang, Yuhong Liang, Ming-Chang Yang:
Unlocking the Full Potential of Dual-Interface SSDs: A Comprehensive Hardware and Software Perspective. 119:1-119:25 - Haotian Qiao, Vidya Srinivas, Peter A. Dinda, Robert P. Dick:
Efficient Video Redaction at the Edge: Human Motion Tracking for Privacy Protection. 120:1-120:22 - Garima Modi, Priyanka Singla, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda:
FARRE: Fairness Aware Request Response Arbitration in Shared Caches. 121:1-121:26 - Ke Wang, Yingnan Zhao, Ahmed Louri:
FORT-GCN: A Fault-Tolerant and Adaptive Accelerator Design for Efficient Graph Convolutional Network Inference. 122:1-122:26 - Alles Rebel, Nikil D. Dutt, Bryan Donyanavard:
OASIS: Optimized Adaptive System for Intelligent SLAM. 123:1-123:22 - Juliette Pottier, Maria Méndez Real, Bertrand Le Gal, Sébastien Pillement:
DynHaMo: Dynamic Hardware-Based Monitoring Dedicated to Attacks Detection. 124:1-124:25 - Alish Kanani, Lukas Pfromm, Harsh Sharma, Jana Doppa, Partha Pande, Ümit Y. Ogras:
THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures. 125:1-125:26 - Mehrshad Zandigohar, Mallesham Dasari, Gunar Schirner:
Grasp-HGN: Grasping the Unexpected. 126:1-126:21 - Praseetha M, Madhu Mutyam, Venkata Kalyan Tavva:
Selective Subarray Isolation for Mitigating RowHammer Attack. 127:1-127:22 - Smita Das, Amit Jana, Debdeep Mukhopadhyay:
A Severe Vulnerability and an Effective Defense Against DFA on Ascon. 128:1-128:25
EMSOFT 2025
- Suraj Meshram, Arnab Sarkar, Arijit Mondal:
A Tunable Generic Meta-Heuristic Framework for Balancing Assembly Line Systems in Manufacturing. 129:1-129:23 - Yi-Cheng Wei, Yi-Chieh Tsou, Yong-Cheng Chen, Li-Pin Chang:
App-aware Swap Resource Allocation for Enhancing User-perceived Latency on Mobile Devices. 130:1-130:24 - Philip Tasche, Paula Herber, Marieke Huisman:
Deductive Verification of Cooperative RTOS Applications. 131:1-131:25 - Lars Willemsen, Mario Günzel, Björn B. Brandenburg, Georg von der Brüggen, Ching-Chi Lin, Jian-Jia Chen:
Transfer Schedulability in Periodic Real-Time Systems. 132:1-132:25 - Jiwon Kim, Geon Kim, Jeho Lee, Thiemo Voigt, Hojung Cha:
SecureRide: Detecting Safety-Threatening Behavior of E-Scooters Using Battery Information. 133:1-133:24 - Yiqi Zhao, Xinyi Yu, Bardh Hoxha, Georgios Fainekos, Jyotirmoy Deshmukh, Lars Lindemann:
STL-GO: Spatio-Temporal Logic with Graph Operators for Distributed Systems with Multiple Network Topologies. 134:1-134:23 - Ruiqi Wang, Zichen Wang, Peiqi Gao, Mingzhen Li, Jaehwan Jeong, Yihang Xu, Yejin Lee, Carolyn M. Baum, Lisa Tabor Connor, Chenyang Lu:
Real-Time Video-Based Human Action Recognition on Embedded Platforms. 135:1-135:24 - Yuhui Shi, Yuming Wu, Lei Bu, Xuandong Li:
Checking Bounded Reachability of Compositional Linear Hybrid Automata Using Interaction Relations. 136:1-136:26 - Tsubasa Matsumoto, Kazuki Watanabe, Kohei Suenaga, Masaki Waga:
Efficient Black-Box Checking with Specification-Guided Abstraction. 137:1-137:26 - Nikhil Vijay Naik, Alessandro Pinto, Pierluigi Nuzzo:
Contract Embeddings for Layered Control Architectures. 138:1-138:24 - Binqi Sun, Bohua Zou, Yigong Hu, Tomasz Kloda, Ling Wang, Tarek F. Abdelzaher, Marco Caccamo:
SAPar: A Surrogate-Assisted DNN Partitioner for Efficient Inferences on Edge TPU Pipelines. 139:1-139:26 - Jiale Chen, Duc Van Le, Yuanchun Li, Yunxin Liu, Rui Tan:
TimelyNet: Adaptive Neural Architecture for Autonomous Driving with Dynamic Deadline. 140:1-140:23 - Jonas Peeck, Rolf Ernst, Selma Saidi:
Towards Efficient Multi-Frame Clustering in Response Time Analysis for Large Object Communication. 141:1-141:26 - Kay Heider, Christian Hakert, Kuan-Hsun Chen, Jian-Jia Chen:
LazyTick: Lazy and Efficient Management of Job Release in Real-Time Operating Systems. 142:1-142:25 - Joep van Wanrooij, Twan Basten, Marc Geilen:
Schedule Synthesis for Synchronous Dataflow Models with Lower and Upper Timing Bounds. 143:1-143:28 - Zimo Ma, Xiangzhong Luo, Qun Song, Rui Tan:
Dynamic Layer Routing Defense for Real-Time Embedded Vision. 144:1-144:26 - Seonghoon Park, Jiwon Kim, Jeho Lee, Hojung Cha:
Ember: Task Wakeup Sequence-Based Energy Optimization for Mobile Web Browsing. 145:1-145:24 - Maximilian Seidler, Alexander Krause, Peter Ulbrich:
Wasm-IO: Enabling Low-Level Device Interaction in WebAssembly for Industry Automation. 146:1-146:26 - Beatrice Melani, Ezio Bartocci, Michele Chiari:
A Tree-Shaped Tableau for Checking the Satisfiability of Signal Temporal Logic with Bounded Temporal Operators. 147:1-147:26 - Debarpita Banerjee, Parasara Sridhar Duggirala, Bineet Ghosh, Sumana Ghosh:
A Formal Approach towards Safe and Stable Schedule Synthesis in Weakly Hard Control Systems. 148:1-148:26 - Hongkai Chen, Zeyu Zhang, Shouvik Roy, Ezio Bartocci, Scott A. Smolka, Scott D. Stoller, Shan Lin:
Cumulative-Time Signal Temporal Logic. 149:1-149:23 - Shaokai Lin, Erling Jellum, Mirco Theile, Tassilo Tanneberger, Binqi Sun, Chadlia Jerad, Yimo Xu, Guangyu Feng, Magnus Mæhlum, Jian-Jia Chen, Martin Schoeberl, Linh Thi Xuan Phan, Jerónimo Castrillón, Sanjit A. Seshia, Edward A. Lee:
Quasi-Static Scheduling for Deterministic Timed Concurrent Models on Multi-Core Hardware. 150:1-150:25 - Abdelrhman Mohamed Abotaleb, Mohamed Hassan:
The Case for HW/SW Harmony in Real-Time Systems: Tightening Memory Latency of Streaming Applications. 151:1-151:27 - Lipsy Gupta, Pavithra Prabhakar:
Star-Set Based Efficient Reachable Set Computation of Anytime Sensing-Based Neural Network-Controlled Dynamical Systems. 152:1-152:20 - Abigail Eisenklam, Robert Gifford, Georgiy A. Bondar, Yifan Cai, Tushar Sial, Linh Thi Xuan Phan, Abhishek Halder:
Rasco: Resource Allocation and Scheduling Co-design for DAG Applications on Multicore. 153:1-153:27 - Dipankar Mandal, Arnab Sarkar, Arijit Mondal:
A Discrete Partial Charging Enabled Dynamic Programming Strategy for Optimal Fixed-Route Electric Vehicle Charging. 154:1-154:25 - Srinivasan Subramaniyan, Xiaorui Wang:
FC-GPU: Feedback Control GPU Scheduling for Real-time Embedded Systems. 155:1-155:25
Volume 24, Number 6, November 2025
- Yashashwee Chakrabarty, Akanksha Dixit, Smruti R. Sarangi:
VoxDepth: Rectification of Depth Images on Edge Devices. 156:1-156:27 - Qizhi Zhang, Ya Gao, Haocheng Ma, Jiaji He, Yiqiang Zhao, Xiaolong Guo:
Boosting Cryptographic ICs' Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths. 157:1-157:25 - Mainak Mondal, Fei Dou, Jinbo Bi, Song Han:
Deep Q-Learning-Based Mobile Charger Path Planning in Wireless Powered Communication Networks. 158:1-158:32 - Khakim Akhunov, Kasim Sinan Yildirim, Jongouk Choi, Changhee Jung:
Adaptive Computing in Memory Meets Conventional Batteryless Platforms. 159:1-159:26 - Xianghong Hu, Chaoming Yang, Xueming Li, Rongfeng Li, Yuanmiao Lin, Shansen Fu, Hongmin Huang, Shuting Cai, Xiaoming Xiong:
A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees. 160:1-160:26 - Woosuk Kang, Eunjin Jeong, Kyonghwan Yoon, Soonhoi Ha:
A Framework for Multi-Robot Programming: From High-Level Specification to Retargetable Deployment. 161:1-161:45 - Danny Abraham, Biswadip Maity, Bryan Donyanavard, Nikil D. Dutt:
Runtime Adaptivity for Efficient Neural Network Inference on Autonomous Systems. 162:1-162:25 - Mir Md Sajid Sarwar, Rajarshi Ray:
Exploring Inevitable Waypoints for Unsolvability Explanation in Hybrid Planning Problems. 163:1-163:20 - Vishesh Mishra, Dipesh, Sparsh Mittal, Urbi Chatterjee:
SATGuard: SAT-driven Countermeasures for Protecting Approximate Circuits from Hardware Trojan. 164:1-164:29 - Ayushi Agarwal, Pulkit Goel, P. J. Joseph, Prokash Ghosh, Sourav Roy, Preeti Ranjan Panda:
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators. 165:1-165:34 - Alan Burns, Cliff B. Jones:
A Specification Framework for Mixed-Criticality Scheduling Protocols. 166:1-166:24 - Huachen Zhang, Jianyang Ding, Bowen Jiang, Tianshuo Lu, Wei Xu, Zhilei Chai:
Optimizing Sparse Matrix Convolution on RISC-V Core: Custom Instructions for Embedded System. 167:1-167:23 - Hyunjun Kim, Hwajeong Seo:
Optimizing AES-GCM on 32-Bit ARM Cortex-M4 Microcontrollers: Fixslicing and FACE-Based Approach. 168:1-168:24 - Seonghoon Park, Junick Ahn, Daeyong Kim, Hojung Cha:
Duration-Aware Sound Event Detection on Ultra-Low-Power Sensor Devices. 169:1-169:26 - Nikhil Shukla, Kai Ni, Sam Stevenson, Vijaykrishnan Narayanan:
Ferroelectric Memory Technology for Big Data Applications. 170:1-170:20 - Theologos Anthimopoulos, Milad Kokhazadeh, Vasilios I. Kelefouras, Benjamin Himpel, Georgios Keramidas:
Optimizing Tensor Train Decomposition in DNNs for RISC-V Architectures Using Design Space Exploration and Compiler Optimizations. 171:1-171:34 - Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Daniele Frigioni, Tania Di Mascio:
A New HW/SW Co-Design Approach for Monitored Systems-on-Chip Development. 172:1-172:37 - Artem Klashtorny, Mahesh Tripunitara, Hiren D. Patel:
Optimal Split Point Placement for Predictable GPU Wavefront Splitting. 173:1-173:25
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