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ORCIDIEEE Solid-State Circuits Letters, Volume 8
Volume 8, 2025
- Christoph Gasser
, Christoph Ribisch, Simon Michael Laube, Kerstin Schneider-Hornstein, Horst Zimmermann:
Ultrasensitive Reset-Less Integrator-Based PIN-Diode Receiver With Input Current Control. 17-20 - Songtao Wei, Peng Yao, Xinying Guo, Dong Wu, Lu Jie, Qi Qin, Bin Gao, Jianshi Tang, He Qian, Sining Pan, Huaqiang Wu:
A 28-nm Static-Power-Free Fully Parallel RRAM-Based TD CIM Macro With 1982 TOPS/W/Bit for Edge Applications. 21-24 - Hing Tai Chen, Xun Liu, Ka Nang Leung:
A 1.48-fs FoM Analog Capacitorless-LDO With Cascade-Inverter-Based Pseudo-Power Transistor. 25-28 - Dengquan Li, Maowen Qian, Depan Li, Hongzhi Liang, Zhangming Zhu:
A 2.6-GS/s 8-bit Time-Interleaved ADC With Fully Dynamic Current Integrating Sampler. 29-32 - Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla:
A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS. 33-36 - Ali Ameri, Ali M. Niknejad:
A Sub-THz Harmonic Recycling Single-Stage Frequency Quadrupler in CMOS 28-nm Technology. 37-40 - Yahia Ibrahim, Ali Niknejad:
A 23-28-GHz Doherty Power Amplifier With a PVT Insensitive Power Detection for Adaptive Biasing. 41-44 - Gaofeng Jin, Fei Feng, Yan Chen, Hanli Liu, Xiang Gao:
A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique. 45-48 - Liheng Liu, Tianxiang Qu, Hao Li, Dan Li, Gan Guo, Zhiliang Hong, Jiawei Xu:
A 0.86 mW 17 fA/√Hz, 129-dB DR Current-Sensing Front-End for Under-Display Ambient Light Sensor With Zero-Compensated Logarithmic TIA. 49-52 - Jin-Fa Chang:
20-26-GHz CMOS PA With High Pout and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner. 53-56 - Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury:
A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor. 57-60 - Hesham Beshary, Yikuan Chen, Ethan Chou, Ali M. Niknejad:
A 1.54 pJ/b 80 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas in 28-nm Bulk CMOS. 61-64 - Kai-Cheng Cheng, Soon-Jyh Chang, Chung-Chieh Chen, Shuo-Hong Hung:
A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator. 65-68 - Yuxuan Chen, Xianzhi Yang, Jiayi Lin, Zilong Liu, Min Zeng, Qi Wu, Mingyi Chen:
A 115.2-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Mismatch Error Shaping for Noninvasive Biomedical Devices. 69-72 - Young-Ju Oh, Hyun-Woo Jeong, Hyeonho Park, Jeeyoung Shin, Junwon Jeong, Woong Choi, Sung-Wan Hong:
Compact Single-Stage Input and Output Rail-to-Rail Class AB Buffer Amplifier With an Asymmetric Output Structure. 73-76 - Yun Hao, Bo Zhou, Xukun Wang, Chunli Huang, Zhihua Wang:
A Bi-Directional Near-Ground Current Sensor With Reconfigurable Unidirectional Gains. 77-80 - Zehang Wu, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins, Minglei Zhang:
An Inverter-Based Sampling Front-End Achieving >46-dB SFDR at 50-GHz Input. 81-84 - Ragh Kuttappa, Vinayak Honkote, Amreesh Rao, Gaurav Kamalkar, Kailash Chandrashekar, Eric Finley, Chaitanya Sankuratri, Faran Rafiq, Robert Orton, Nils Hernandez, Anuradha Srinivasan, Tanay Karnik:
A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology. 85-88 - Yu-Tse Shih, Li-Jen Huang, Xiao-Quan Wu, Wei-Chieh Hung, Tz-Han Hsu, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A 24 V-to-1 V Low Input Current Ripple SC Hybrid Converter With Conducted EMI Noise Precompensation Filter and Current-Modulated Gate-Driver for Automobile Application. 89-92 - Marziyeh Rezaei, Liban Hussein, Alana Dee, Shucheng Fang, Qixuan Lin, Mo Li, Sajjad Moazeni:
Secure FMCW LiDAR Ranging With an Electro-Optical Synthesizer at 5000 Measurements/s. 93-96 - Michihiro Ide, Keito Yuasa, Sena Kato, Shu Date, Takashi Tomura, Kenichi Okada, Atsushi Shirane:
A 122 GHz Wirelessly Powered Active Reflector for D-Band Communications. 97-100 - Vaishali Choudhary, Pydi Ganga Bahubalindruni:
A Low-Power Fully Dynamic Latched Comparator Using Flexible Oxide TFT Technology. 101-104 - Guangxu Shen, Haitao Ma, Chenyang Zhang, Dingyuan Zeng, Haoshen Zhu, Wenquan Che:
GaN HEMT-Based Resonators Using Parasitic Effects and Its Application to A Ka-band Coupled-Resonator SPDT Switch. 105-108 - Jooeun Kim, Jeongmyeong Kim, Minkyu Yang, Kyounghun Kang, Wanyeong Jung:
A MOS-Based Temperature Sensor With Energy-Efficient Techniques. 109-112 - Mehdi Saberi, Alexandre Schmid:
Analysis of Power Consumption and Propagation Delay in Voltage Level Shifters. 113-116 - Chang Xue, Youming Yang, Siyuan He, Gang Du, Yuan Wang, Yandong He:
A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure. 117-120 - Yong-Jun Jo, Chufeng Yang, Yuanjin Zheng, Tony Tae-Hyoung Kim:
Convolutional Window-Inspired Similarity-Aware Computation-in-Memory for Energy Saving. 121-124 - Srujan Kumar Kaile, Julian Camilo Gomez Diaz, Yuanming Zhu, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo:
A 56-Gb/s DAC/ADC-Based Multicarrier Transceiver With TX Polar DSP and RX MIMO-DSP for >40-dB Loss Channel. 125-128 - Jaeho Kim, Jooeun Bang, Seohee Jung, Myeongho Han, Jaehyouk Choi:
A Low-Reference-Spur and Low-Jitter D-Band PLL With Complementary Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector. 129-132 - Satoshi Tanaka, Shinsuke Hara, Kyoya Takano, Akifumi Kasamatsu, Yoshiki Sugimoto, Kunio Sakakibara, Shunichi Kubo, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima:
A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver. 133-136 - Yu-Teng Chang, Shau-Chi Ho, Wen-Jie Lin:
A Wideband VCO Using a Switchable Inductance Technique and Negative Gₘ Enhancement With Positive Feedback. 137-140 - Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Junlong Gong, Qiuyu Peng, Baoyong Chi:
A Series-Parallel-Resonance Oscillator With a 191.5 dBc/Hz FoM. 141-144 - Changyoung Lee, Youngseok Park, Hyunchul Yoon, Seryeong Yoon, Donggeon Kim, Bokyeon Won, Junhwa Song, Injae Bae, Jae-Joon Song, Kyuchang Kang, Jaehyuk Kim, Kyungrak Cho, Incheol Nam, Jungdon Ihm, Younghun Seo, Changsik Yoo, Sangjun Hwang:
A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier With Ground Precharge and Charge Transfer Pre Sensing for Sub-1V DRAM. 145-148 - Shaokang Zhao, Li Wang, C. Patrick Yue:
A 5-10-GHz Quadrature Clock Generator With Open-Loop Quadrature Error Correction in 28-nm CMOS. 149-152 - Hao Guo, Jiawei Chen, Hailong Jiao:
A 15T SRAM Cell-Based Fully-Digital Computing-in-Memory Macro Supporting High Parallelism and Fine-Grained Simultaneous Read + Write + MAC Operations. 153-156 - Kedar Bhatt, Stafford Hutchins, Atresh Sanne, Mohammad M. Hasan, Zhanping Chen, Jaydeep P. Kulkarni:
A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 Logic Technology. 157-160 - Nengxu Zhu, Yiting Zhang, Genyin Ma, Fanyi Meng:
Two 7-13-GHz GaAs-SiGe Four-Channel Beamforming Chiplets With/Without Metallic Interlayer Shields. 161-164 - Yu-Kai Chen, Yi-Fan Tseng, Wei-Zhe Su, Chun-Hsing Li:
A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS. 165-168 - Cody J. Ellington, Sandeep Hari, Brian A. Floyd:
A 10 to 40 GHz Reflection-Mode N-Path Filter. 169-172 - Jiahao Wang, Shen Ye, Shiqi Zhang, Zhiliang Hong, Jiawei Xu:
A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range. 173-176 - Sungjin Kim, Jeonghyun Lee, Yoonseo Cho, Jintae Kim, Jaehyouk Choi, Heein Yoon:
A 6.2b-ENOB 2.5 GS/s Flash-and-VCO-Based Subranging ADC Using a Residue Shifting Technique. 177-180 - Wei-Yu Lin, Jun-Chau Chien:
A Millimeter-Wave Standing-Wave Oscillator With Frequency-Specific Wave-Velocity Control Demonstrating Class-F Effects. 181-184 - Changde Ding, Yan Zhu, Pengjie Wang, Zhiliang Hong, Jiawei Xu:
A 10.9-nV/√Hz, 74.9-dB DR, 20-MS/s Ultrasound Analog Front End for Fully Digital Beamforming. 185-188 - Yihao Yang, Dan Li, Nan Qi, Binhao Wang:
A 2 pA/√Hz Input-Referred Noise TIA in 180-nm CMOS With 2.5 GHz Bandwidth for Optical Receiver. 189-192 - Yichen Xu, Zhaoqing Wang, Rentao Wan, Suhwan Kim, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok:
Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency. 193-196 - Wei Chen, Minhao Li, Ming Zhong, Yuan Li, Ying Wu, Pisen Zhou, Patrick Yin Chiang:
A 4×56 -Gbaud PAM-4 Linear and Low-Noise TIA for Linear-Drive Pluggable Optics. 197-200 - Zhaowu Wang, Dexin Shi, Xinyan Li, Shu Ma, Ronglin Chen, Ze Yu, Ziao Wang, Shijie Chen, Xiaochen Tang, Yong Wang:
A Compact 8-to-16 GHz GaN Nonuniform Distributed PA With Double Feeding Line Matching Structure Presenting 43.2% Average PAE. 201-204 - Qiumeng Wei, Peng Yao, Dong Wu, Qi Qin, Bin Gao, Qingtian Zhang, Sining Pan, Jianshi Tang, He Qian, Lu Jie, Huaqiang Wu:
A RRAM-Based CIM Design With in-Situ Transposable Computing and Hybrid-Precision Scheme for Edge Learning. 205-208 - Suyash Shrivastava, Vaishali Choudhary, Pydi Ganga Bahubalindruni:
A Compact Low Power Active Oscillator Using Oxide TFTs on a Flexible Foil. 209-212 - Wei-Chun Wang, Shida Zhang, Laith A. Shamieh, Narasimha Vasishta Kidambi, Isha Chakraborty, Saibal Mukhopadhyay:
MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication. 213-216 - Edoardo Baiesi Fietta, David Seebacher, Davide Ponton, Andrea Bevilacqua:
A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS. 217-220 - Alican Çaglar, Imri Fattal, Clement Godfrin, Roy Li, Steven Van Winckel, Kristiaan De Greve, Piet Wambacq, Jan Craninckx:
A Scalable mK DC Demultiplexer With Extremely Low OFF-Leakage CMOS Switches for Biasing of Spin Qubits. 221-224 - Chun-Sheng Lin, Chih-Hsueh Lin, Chun-Hsing Li:
A 240-GHz Sub-THz Direct-Conversion Transmitter With I/Q Phase Calibration in 40-nm CMOS. 225-228 - Cai Li, Kaize Zhou, Junyi Qian, Haochang Zhi, Weiwei Shan:
A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization. 229-232 - Hyeon-Ji Choi, Joo-Mi Cho, Hyo-Jin Park, Seok-Jun Lee, Sung-Wan Hong:
A 0-to- 10μF Off-Chip Output Capacitor-Scalable Boost Converter Achieving 96.68% Peak Efficiency. 233-236 - Yan Chen, Gaofeng Jin, Haojie Xu, Yu Cui, Lei Zeng, Xiang Gao:
A Dual-Path SPD/PFD PLL With PVT-Insensitive Loop Bandwidth. 237-240 - Chenxin Liu, Yudai Yamazaki, Anyi Tian, Chun Wang, Hans Herdian, Abanob Shehata, Han Nie, Minzhe Tang, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 160-Gb/s D-Band Bi-Directional CMOS Mixer Covering 112-170 GHz for 6G Transceivers. 241-244 - Yuibi Gomi, Akira Sato, Waleed Madany, Kenichi Okada, Satoshi Adachi, Masatoshi Itoh, Masanori Hashimoto:
A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement. 245-248 - Javier Granizo, Rubén Garvi, Ricardo Carrero, Luis Hernández:
LIF Neuron Based on a Charge-Powered Ring Oscillator in Weak Inversion Achieving 201 fJ/SOP. 249-252 - Cheng-Bin Chen, Tsung Chen, Yuan-Hao Huang:
24.86 Gb/s Full-Digital Chaos Random Number 1.53 GSamples/s Noise Generator in 40nm CMOS. 253-256 - Bu-Il Nam, Jayang Yoon, Kyunghea Lee, Sol Kim, Junhong Park, Chi-Weon Yoon, Eunkyoung Kim:
Integrated Circuit to Compensate Parasitic Leakage Component for WL Leakage Current in nand Flash Memory. 257-260 - Kai Cui, Honglei Xu, Yingduo Duan, Yan Lu, Xiaoya Fan, Yanzhao Ma:
A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation. 261-264 - Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim:
A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation. 265-268 - Seok-Ju Yun, Jaehyuk Lee, Sungmeen Myung, Jangho An, Daekun Yoon, Seungchul Jung, Soonwan Kwon, Sangjoon Kim:
5-nm High-Efficiency and High-Density Digital SRAM In-Memory-Computing Macros for AI Accelerators. 269-272 - Chongyun Zhang, Li Wang, Fuzhan Chen, C. Patrick Yue:
A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS. 273-276 - Zhendong Li, Yongjuan Shi, Yifan Jiang, Chen Hu, Junting Chen, Mengyuan Hua, Xun Liu, Junmin Jiang:
Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions. 277-280 - Chang Liu, Burak Catli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Xiaochen Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao:
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm. 281-284 - David Dolt, Samuel Palermo:
A 19.5-GHz Radiation-Hardened Sub-Sampled PLL With Quad-Core VCO in 16-nm FinFET Achieving Sub-50 fs Jitter. 285-288 - Lucrezia Navarin, Karl Norling, Marco Parenzan, Stefano Ruzzu, Andrea Neviani, Andrea Bevilacqua:
A Fully Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication. 289-292 - Po-Han Chen, Bo-Wun Cheng, Michael Oduoza, Zhouhua Xie, Rupert Lu, Sai Gautham Ravipati, Kalhan Koul, Alex Carsello, Yuchen Mei, Mark Horowitz, Priyanka Raina:
Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications. 293-296 - Yongling Zhang, Ji Xiong, Junzai Chen, Xiaoyu Li, Jinrui Zuo, Yan Wang, Xiaoyi Wang, Miao Meng:
A Battery-Free BLE Backscatter Communication Chip for Wearable Systems. 297-300 - Shankkar Balasubramanian, Kristof Vaesen, Piet Wambacq, Carsten Wulff:
A Compact Current-Reusing 6-mW 66-92 GHz Frequency Quadrupler With 5% Peak Power Added Efficiency and >36 dBc Harmonic Rejection in 22-nm FDSOI CMOS. 301-304 - Ronald Wijermars, Yi-Han Ou-Yang, Sijun Du, Dante G. Muratore:
A 40.68-MHz, 200-ns-Settling Active Rectifier for mm-Sized Implants. 305-308 - Alessandro Catania, Sebastiano Strangio, Maksym Paliy, Christian Sbrana, Michele Bertozzi, Giuseppe Iannaccone:
High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit. 309-312 - Jelle H. T. Bakker, Nimit Jain, Paul Klatser, Mark S. Oude Alink, Bram Nauta:
Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI. 313-316 - Bram Veraverbeke, Filip Tavernier:
A Benchmark of Cryo-CMOS Dynamic Comparators in a 40 nm Bulk CMOS Technology. 317-320 - Prashanth Mohan, Siddharth Das, Ken Mai:
A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET. 321-324 - Berkay Özbek, Timothy G. Constandinou:
A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core. 325-328 - Basem Abdelaziz Abdelmagid, Yuqi Liu, Hua Wang:
A Wideband Calibration-Free D-Band Passive Phase Shifter With Frequency-Invariant Codes Over 24% Fractional Bandwidth. 329-332 - Yongjia Li, Jianlin Xia, Feng Cheng, Yifan Cao, Jin Wu, Encheng Zhu, Xiaofeng Sun, Dejin Wang, Long Zhang, Zhongyuan Fang, Weifeng Sun:
An 8.5 MHz 42 ppm/°C Relaxation Oscillator With Charge-Pump Delay Cancellation and Digital Chopping Demodulation. 333-336 - Changjoo Kim, Sooho Park, Yohan Choi, Minkyun Shim, Woojin Lee, Donghwi Seo, Chulwoo Kim:
An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration. 345-348 - Ethan Chou, Hesham Beshary, Nima Baniasadi, Ali M. Niknejad:
A 200 GHz Wideband and Low-Power Direct-Downconversion Receiver Element in 16 nm FinFET Technology. 349-352 - Mamoru Sato, Sachio Akebono, Kazuyoshi Yasuoka, Eriko Kato, Masahiro Tsuruta, Chiaki Takano, Kensuke Ota, Kazuki Haraguchi, Masahiro Watanabe, Genki Fujii, Koichiro Yamanaka, Kazunori Yasuda, Satoshi Minami, Katsuhiko Hanzawa, Kohei Matsuda, Akihiko Kato, Yosuke Ueno:
A 0.8-μm 32-Mpixel Always-On CMOS Image Sensor With Windmill-Pattern Edge Extraction and On-Chip DNN. 353-356 - Harold Pilo, Manish Arora, Chien-An Lai, Mike Lee, Zack Lo, Mayur Randeria:
A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection. 357-360 - Xiuzhi Zhao, Liheng Liu, Shi Chen, Tianxiang Qu, Qinjing Pan, Dan Li, Gan Guo, Zhiliang Hong, Jiawei Xu:
A 560 μ W, 6 fA/√Hz, 146 dB-DR Ultrasensitive Current Readout Circuit for PWM-Dimming-Tolerant Under-Display Ambient Light Sensors. 361-364 - Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher:
PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI. 365-368
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