default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID6th IOLTW 2000: Palma de Mallorca, Spain
- 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain. IEEE Computer Society 2000, ISBN 0-7695-0646-1
Fault Tolerance
- Keith Whisnant, Zbigniew Kalbarczyk, Ravishankar K. Iyer:
Micro-Checkpointing: Checkpointing for Multithreaded Applications. 3-8 - Alfredo Benso, Silvia Chiusano, Paolo Prinetto:
A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT. 9-16 - Maurizio Rebaudengo, Matteo Sonza Reorda
, Massimo Violante, Ph. Cheynet, Bogdan Nicolescu, Raoul Velazco:
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. 17-
Fault Tolerance and On-Line Testing for Reconfigurable Systems
- Lukás Sekanina, Vladimír Drábek:
Relation between Fault Tolerance and Reconfiguration in Cellular Systems. 25-30 - Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John Marty Emmert:
Improving On-Line BIST-Based Diagnosis for Roving STARs. 31-39 - Andrzej Krasniewski:
Self-Testing of FPGA Delay Faults in the System Environment. 40-
Reliability Issues in Nanometer Technologies and Radiation Effects
- José Antonio Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca:
A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits. 45-51 - Vincent Pouget, Pascal Fouillat, Dean Lewis, Hervé Lapuyade, L. Sarger, F. M. Roche, S. Duzellier, R. Ecoffet:
An Overview of the Applications of a Pulsed Laser System for SEU Testing. 52-
Fault Injection: Regis Leveugle, TIMA Laboratory
- B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
New Techniques for Accelerating Fault Injection in VHDL Descriptions. 61-66 - Fabian Vargas, Alexandre M. Amory, Raoul Velazco:
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL. 67-72 - Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System. 73-79 - Raoul Velazco, Sana Rezgui:
Transient Bitflip Injection in Microprocessor Embedded Applications. 80-
On-Line Current Monitoring
- Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller:
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. 87-91 - Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková:
I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. 92-93 - Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos:
A Compact Built-In Current Sensor for IDDQ Testing. 95-99 - Yvan Maidon, Yann Deval, Jean-Baptiste Bégueret:
An Improved CMOS BICS for On-Line Testing. 100-
Concurrent Checking
- Jose Miguel Vieira dos Santos:
Concurrent Scan Monitoring and Multi-Pattern Search. 107-111 - Ahmad Abdelhay, Emmanuel Simeu:
Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems. 112-
Built-In Self Testing
- Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. 121-126 - Ondrej Novák, Jiri Nosek:
On Using Deterministic Test Sets in BIST. 127-132 - Xiaodong Zhang, Kaushik Roy:
Power Reduction in Test-Per-Scan BIST. 133-
Self Checking Circuits and Analog Approaches
- Andrej A. Morosov, Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Michael Gössel:
New Self-Checking Circuits by Use of Berger-Codes. 141-146 - Michael Gössel, Alexej Dmitriev, Vladimir V. Saposhnikov, Valerij V. Saposhnikov:
A New Method for Concurrent Checking by Use of a 1-out-of-4 Code. 147-152 - Anzhela Yu. Matrosova, Sergey Ostanin:
Self-Checking FSM Design with Observing only FSM Outputs. 153-154 - Paolo Migliavacca:
Faster Time-to-Market, Lower Cost of Development and Test for Standard Analog IC. 155-
Coding Theory and Applications
- K. D. R. Jagath-Kumara:
Theoretical Performance Bounds of a Probability of Bit Error Estimator Used in Digital Links Employing Binary Block Codes. 165-168 - T. Vallino, Abbas Dandache, Jean-Paul Delahaye, Fabrice Monteiro, Bernard Lepley:
A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code. 169-170 - Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel:
Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. 171-
Fault Tolerance and On-Line Testing in Railway and Industrial Control
- M. E. Nillesen, A. Del Pizzo, M. Pasquariello, R. Rizzo:
A Very Flexible DSP-Based Controller for On-Line Test and Control of Industrial Processes. 179-184 - Naotake Kamiura, Masashi Tomita, Teijiro Isokawa, Nobuyuki Matsui:
On Realization of Fault-Tolerant Fuzzy Controllers. 185-190 - Michael Nicolaidis, N. Zaidan, Th. Calin, D. Bied-Charreton:
ISIS: A Fail-Safe Interface Realized in Smart Power Technology. 191-
On-Line Testing and Self Repair
- Mohammad A. Naal, Emmanuel Simeu:
High-Level Synthesis Methodology for On-Line Testability Optimization. 201-206 - Janusz Sosnowski:
Improving Fault Coverage in System Tests. 207-213 - Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni:
A Family of Self-Repair SRAM Cores. 214-218
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-01-29 02:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
