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ORCID33rd ICCD 2015: New York City, NY, USA
- 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, USA, October 18-21, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-7166-7
- Todd M. Austin:
Keynote talk I: Ending the Tyranny of Amdahl's Law. vii-ix - Elena Kakoulli
, Vassos Soteriou, Charalambos Koutsides, Kyriacos Kalli:
Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonics. 1-8 - Jiashen Li, Yun Pan:
A fast and energy efficient branch and bound algorithm for NoC task mapping. 9-16 - Dharanidhar Dang, Rabi N. Mahapatra, Eun Jung Kim:
PID controlled thermal management in photonic network-on-chip. 17-23 - Vijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham:
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification. 24-31 - Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos:
Clustering-based revision debug in regression verification. 32-37 - Prateek Puri, Michael S. Hsiao:
SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships. 38-45 - Pouya Taatizadeh, Nicola Nicolici:
Emulation-based selection and assessment of assertion checkers for post-silicon validation. 46-53 - Karthikeyan P. Saravanan, Paul M. Carpenter, Alex Ramírez:
Exploring multiple sleep modes in on/off based energy efficient HPC networks. 54-61 - Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Houman Homayoun:
Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs. 62-69 - David A. Penry:
Improving the interface performance of synthesized structural FAME simulators through scheduling. 70-77 - Michael J. Hall, Roger D. Chamberlain:
Using M/G/l queueing models with vacations to analyze virtualized logic computations. 78-85 - Daniele Jahier Pagliari, Andrea Calimera, Enrico Macii, Massimo Poncino:
An automated design flow for approximate circuits based on reduced precision redundancy. 86-93 - Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue:
Logic simplification by minterm complement for error tolerant application. 94-100 - Alvaro Velasquez, Sumit Kumar Jha:
Fault-tolerant in-memory crossbar computing using quantified constraint solving. 101-108 - Ali Ahari, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori:
Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency. 109-116 - Arseniy Vitkovskiy, Vassos Soteriou, Paul V. Gratz:
Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects. 117-124 - XianWei Zhang, Youtao Zhang, Jun Yang:
DLB: Dynamic lane borrowing for improving bandwidth and performance in Hybrid Memory Cube. 125-132 - Yanan Cao, Long Chen, Zhao Zhang:
Memory design for selective error protection. 133-140 - Si Wu, Yinlong Xu, Yongkun Li, Yunfeng Zhu:
POS: A Popularity-based Online Scaling scheme for RAID-structured storage systems. 141-148 - Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura:
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. 149-156 - XianWei Zhang, Lei Zhao, Youtao Zhang, Jun Yang:
Exploit common source-line to construct energy efficient domain wall memory based caches. 157-163 - Bhargavraj Patel, Nikos Hardavellas, Gokhan Memik:
SCP: Synergistic cache compression and prefetching. 164-171 - Parth Lathigara, Shankar Balachandran, Virendra Singh:
Application behavior aware re-reference interval prediction for shared LLC. 172-179 - Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar:
InvArch: A hardware eficient architecture for Matrix Inversion. 180-187 - Benjamin C. Lee:
Applied statistical inference for system design and management. 188-191 - Nicola Bombieri, Federico Busato, Alessandro Danese, Luca Piccolboni, Graziano Pravadelli:
Exploiting GPU architectures for dynamic invariant mining. 192-195 - Valeria Bertacco, Wade Bonkowski:
ItHELPS: Iterative high-accuracy error localization in post-silicon. 196-199 - Cristiana Bolchini, Gianluca C. Durelli, Antonio Miele, Gabriele Pallotta, Marco D. Santambrogio:
An orchestrated approach to efficiently manage resources in heterogeneous system architectures. 200-207 - Alok Prakash, Siqi Wang, Alexandru Eugen Irimiea, Tulika Mitra:
Energy-efficient execution of data-parallel applications on heterogeneous mobile platforms. 208-215 - Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran:
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. 216-223 - Tsung-Yi Ho, William H. Grover, Shiyan Hu, Krishnendu Chakrabarty:
Cyber-physical integration in programmable microfluidic biochips. 224-227 - Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
SOP based logic synthesis for memristive IMPLY stateful logic. 228-235 - Chen-Hsuan Lin, Subhendu Roy, Chun-Yao Wang, David Z. Pan, Deming Chen:
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction. 236-243 - Chia-Yu Wu, Helmut Graeb, Jiang Hu:
A pre-search assisted ILP approach to analog integrated circuit routing. 244-250 - Pietro Fezzardi, Michele Castellana, Fabrizio Ferrandi:
Trace-based automated logical debugging for high-level synthesis generated circuits. 251-258 - Jinwook Jung, Daijoon Hyun, Youngsoo Shin:
Physical synthesis of DNA circuits with spatially localized gates. 259-265 - Vinayaka Jyothi, Sateesh Addepalli, Ramesh Karri:
Deep Packet Field Extraction Engine (DPFEE): A pre-processor for network intrusion detection and denial-of-service detection systems. 266-272 - Chongxi Bao, Ankur Srivastava:
3D Integration: New opportunities in defense against cache-timing side-channel attacks. 273-280 - Chao Luo, Yunsi Fei, Pei Luo, Saoni Mukherjee, David R. Kaeli:
Side-channel power analysis of a GPU AES implementation. 281-288 - Bicky Shakya, Ujjwal Guin, Mark Tehranipoor, Domenic Forte:
Performance optimization for on-chip sensors to detect recycled ICs. 289-295 - Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay:
From theory to practice of private circuit: A cautionary note. 296-303 - Hamid Reza Ghasemi, Ulya R. Karpuzcu, Nam Sung Kim:
Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications. 304-310 - Mahanama Wickramasinghe, Hui Guo:
Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors. 311-318 - Wei Zhang, Hang Zhang, John C. Lach:
Dynamic core scaling: Trading off performance and energy beyond DVFS. 319-326 - Sudarshan Srinivasan, Israel Koren, Sandip Kundu:
Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core. 327-334 - Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Koen Bertels, Said Hamdioui:
Fast boolean logic mapped on memristor crossbar. 335-342 - Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael T. Niemier, Xiaobo Sharon Hu:
Reliable and high performance STT-MRAM architectures based on controllable-polarity devices. 343-350 - John Demme, Bipin Rajendran, Steven M. Nowick, Simha Sethumadhavan:
Increasing reconfigurability with memristive interconnects. 351-358 - Manqing Mao, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. 359-366 - Fernando García-Redondo, Marisa López-Vallejo, Pablo Ituero:
A thermal adaptive scheme for reliable write operation on RRAM based architectures. 367-374 - Shahzad Muzaffar, Ibrahim Abe M. Elfadel:
Power management of pulsed-index communication protocols. 375-378 - Maria Malik, Houman Homayoun:
Big data on low power cores: Are low power embedded processors a good fit for the big data workloads? 379-382 - Doyun Kim, Jiangyi Li, Mingoo Seok:
Energy-optimal voltage model supporting a wide range of nodal switching rates for early design-space exploration. 383-386 - Soumya Banerjee, Wenjing Rao:
On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairs. 387-390 - Joao Marcos de Aguiar, Sunil P. Khatri:
Exploring the viability of stochastic computing. 391-394 - Tomohiro Yoneda, Masashi Imai:
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. 395-398 - Yanwei Song, Mahdi Nazm Bojnordi, Engin Ipek:
Energy-efficient data movement with sparse transition encoding. 399-402 - Zhiguo Liu, Ziyuan Zhu, Jinglin Shi, Jinbao Liu, Shiqiang Li:
A low power buffer-aided vector register file for LTE baseband signal processing. 403-406 - Alberto Bocca, Alessandro Sassone, Alberto Macii, Enrico Macii, Massimo Poncino:
An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns. 407-410 - Rik Jongerius, Giovanni Mariani, Andreea Anghel, Gero Dittmann, Erik Vermij, Henk Corporaal:
Analytic processor model for fast design-space exploration. 411-414 - Md. Tauhidur Rahman, Domenic Forte, Fahim Rahman, Mark Tehranipoor:
A pair selection algorithm for robust RO-PUF against environmental variations and aging. 415-418 - Ji Wu, Dezun Dong, Xiangke Liao, Wang Li:
Chameleon: Adaptive energy-efficient heterogeneous network-on-chip. 419-422 - Cesar Gomes, Mark Hempstead:
Combative cache efficacy techniques: Cache replacement in the context of independent prefetching in last level cache. 423-426 - Ehsan Atoofian, Ahsan Saghir:
Shift-aware racetrack memory. 427-430 - Satish Grandhi, David McCarthy, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana:
ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits. 431-434 - Khaled Z. Mahmoud, William E. Smith, Mark Fishkin, Timothy N. Miller:
Data-driven logic synthesizer for acceleration of Forward propagation in artificial neural networks. 435-438 - Seth H. Pugsley, Arjun Deb, Rajeev Balasubramonian, Feifei Li:
Fixed-function hardware sorting accelerators for near data MapReduce execution. 439-442 - Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. 443-446 - Bo Mao, Suzhen Wu:
Exploiting request characteristics and internal parallelism to improve SSD performance. 447-450 - Jeongjae Yu, Wooyoung Jang:
FDRAM: DRAM architecture flexible in successive row and column accesses. 451-454 - Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Runtime multi-optimizations for energy efficient on-chip interconnections1. 455-458 - Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf:
A hardware-based multi-objective thread mapper for tiled manycore architectures. 459-462 - Masahiro Fujita:
Automatic identification of assertions and invariants with small numbers of test vectors. 463-466 - Ishan G. Thakkar, Sudeep Pasricha:
A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses. 467-470 - Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk:
M-MAP: Multi-factor memory authentication for secure embedded processors. 471-474 - Daniele Jahier Pagliari, Mario R. Casu, Luca P. Carloni:
Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis. 475-478 - Paul Otto, Maria Malik, Nima Akhlaghi, Rebel Sequeira, Houman Homayoun, Siddhartha Sikdar:
Power and performance characterization, analysis and tuning for energy-efficient edge detection on atom and ARM based platforms. 479-482 - Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri:
Security implications of cyberphysical digital microfluidic biochips. 483-486 - Abdullah Muzahid:
Hardware support for production run diagnosis of performance bugs. 487-490 - Dawei Li, Siddhartha Joshi, Seda Ogrenci Memik, James Hoff, Sergo Jindariani, Tiehui Liu, Jamieson Olsen, Nhan Tran:
A methodology for power characterization of associative memories. 491-498 - Pasquale Corsonello, Stefania Perri, Fabio Frustaci:
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. 499-504 - Leo Filippini, Emre Salman, Baris Taskin:
A wirelessly powered system with charge recovery logic. 505-510 - Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar:
Reactive clocks with variability-tracking jitter. 511-518 - Jakob Lechner, Andreas Steininger, Florian Huemer:
Methods for analysing and improving the fault resilience of delay-insensitive codes. 519-526 - Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Engin Ipek, Eby G. Friedman:
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime. 527-534 - Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet:
VLSI implementation of high-throughput, low-energy, configurable MIMO detector. 535-542 - Alen Bardizbanyan, Per Larsson-Edefors:
Exploring early and late ALUs for single-issue in-order pipelines. 543-548 - Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon:
Improving memristor memory with sneak current sharing. 549-556 - Sudhanshu Shukla, Mainak Chaudhuri:
Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems. 557-564 - Chih-Hsun Chou, Laxmi N. Bhuyan:
A multicore vacation scheme for thermal-aware packet processing. 565-572 - Anil Kanduri, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen:
Dark silicon aware runtime mapping for many-core systems: A patterning approach. 573-580 - Mohammad Khavari Tavana, Divya Pathak, Mohammad Hossein Hajkazemi, Maria Malik, Ioannis Savidis, Houman Homayoun:
Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping. 581-588 - Gustavo A. Chaparro-Baquero, Soamar Homsi, Omara Vichot, Shaolei Ren, Gang Quan, Shangping Ren:
Cache allocation for fixed-priority real-time scheduling on multi-core platforms. 589-596 - Li Jiang, Xiangwei Huang, Hongfeng Xie, Qiang Xu, Chao Li, Xiaoyao Liang, Huiyun Li:
A novel TSV probing technique with adhesive test interposer. 597-604 - M. P. Jomu George, Otmane Aït Mohamed:
A methodology to generate evenly distributed input stimuli by clustering of variable domain. 605-612 - Huajun Chen, Zichu Qi, Lin Wang, Chao Xu:
A scan chain optimization method for diagnosis. 613-620 - Cheng Xue, R. D. (Shawn) Blanton:
A one-pass test-selection method for maximizing test coverage. 621-628 - Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi:
Non-enumerative correlation-aware path selection. 629-634 - Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran:
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. 635-642 - Rizwana Begum, Mark Hempstead:
Power-agility metrics: Measuring dynamic characteristics of energy proportionality. 643-650 - Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal:
VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes. 651-658 - XianWei Zhang, Youtao Zhang, Jun Yang:
TriState-SET: Proactive SET for improved performance of MLC phase change memories. 659-665 - Jie Zhang, Gieseo Park, Mustafa M. Shihab, David Donofrio, John Shalf, Myoungsoo Jung:
OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization. 666-673 - Yiren Shen, Jiang Hu:
GPU acceleration for PCA-based statistical static timing analysis. 674-679 - Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. 680-687 - Xiaowei Liu, Alex Doboli, Fan Ye:
Optimized local control strategy for voice-based interaction-tracking badges for social applications. 688-695 - Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
FPGA-SPICE: A simulation-based power estimation framework for FPGAs. 696-703 - Andrew D. Targhetta, Donald E. Owen, Francis L. Israel, Paul V. Gratz:
Energy-efficient implementations of GF (p) and GF(2m) elliptic curve cryptography. 704-711 - Chang Song, Lei Ju, Zhiping Jia:
Hybrid scratchpad and cache memory management for energy-efficient parallel HEVC encoding. 712-719 - Garo Bournoutian, Alex Orailoglu:
Mobile ecosystem driven application-specific low-power control microarchitecture. 720-727 - Raphael Viguier, Chung-Ching Lin, Karthik Swaminathan, Augusto Vega, Alper Buyuktosunoglu, Sharathchandra Pankanti, Pradip Bose, H. Akbarpour, Filiz Bunyak, Kannappan Palaniappan, Guna Seetharaman:
Resilient mobile cognition: Algorithms, innovations, and architectures. 728-731 - Wang Zhou, Dhruv Nair, Oki Gunawan, Theodore G. van Kessel, Hendrik F. Hamann:
A testing platform for on-drone computation. 732-735 - Augusto Vega, Chung-Ching Lin, Karthik Swaminathan, Alper Buyuktosunoglu, Sharathchandra Pankanti, Pradip Bose:
Resilient, UAV-embedded real-time computing. 736-739
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