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ORCIDICCD 2001: Austin, Texas, USA
- 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings. IEEE Computer Society 2001, ISBN 0-7695-1200-3
Keynote Addresses
- Karl-Thomas Neumann:
The In-Car Computing Network: An Embedded Systems Challenge. 3 - John Paul Shen:
Clear and Present Tensions in Microprocessor Design. 4 - Lee M. Harrison:
Moore's Law Meets Shannon's Law: The Evolution of the Communication's Industry. 5-8
Asynchronous Techniques
- Montek Singh, Steven M. Nowick:
MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. 9-17 - Robert B. Reese, Mitchell A. Thornton
, Cherrice Traver:
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. 18-23 - Fu-Chiung Cheng, Shuen-Long Ho:
Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission. 24-31
Architectural Modeling: Performance and Power Analysis
- John W. Haskins Jr., Kevin Skadron:
Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State. 32-39 - Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
A Framework for Energy Estimation of VLIW Architecture. 40-45 - Li Shang, Niraj K. Jha:
High-Level Power Modeling of CPLDs and FPGAs. 46-53
Caching
- Qianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai:
Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores. 54-61 - Aamer Jaleel, Bruce L. Jacob:
In-Line Interrupt Handling for Software-Managed TLBs. 62-67 - Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau:
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures. 68-75
Simulation Based Verification
- Farzan Fallah, Koichiro Takayama:
A New Functional Test Program Generation Methodology. 76-81 - Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer:
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. 82-88 - Lee D. McFearin, David W. Matula:
Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division. 89-97
Modeling of Capacitance and Crosstalk Noise
- Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen:
Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. 98-103 - Payam Heydari, Massoud Pedram:
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits. 104-109 - Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera:
Crosstalk Noise Estimation for Generic RC Trees. 110-117
Improving the Performance of Caching Structures
- Jung-Hoon Lee, Jang-Soo Lee, Seh-Woong Jeong, Shin-Dug Kim:
A Banked-Promotion TLB for High Performance and Low Power. 118-123 - Wei-Fen Lin, Steven K. Reinhardt, Doug Burger, Thomas R. Puzak:
Filtering Superfluous Prefetches Using Density Vectors. 124-132 - Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson:
Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. 133-141
Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
- Irith Pomeranz, Sudhakar M. Reddy:
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. 142-147 - Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. 148-153 - Dong Xiang, Yi Xu:
Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. 154-160
Computer Arithmetic
- Hagen Ploog, Sebastian Flügel, Dirk Timmermann:
Improved ZDN-arithmetic for Fast Modulo Multiplication. 166-171 - Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek:
Design Alternatives for Parallel Saturating Multioperand Adders. 172-177 - Mark G. Arnold, Mark D. Winkel:
A Single-Multiplier Quadratic Interpolator for LNS Arithmetic. 178-185
Circuit Sizing and Optimization
- Tong Xiao, Malgorzata Marek-Sadowska:
Gate Sizing to Eliminate Crosstalk Induced Timing Violation. 186-191 - Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang:
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. 192-198 - Shih-Yih Lai, Ross Baldick:
Buffered Interconnect Tree Optimization Using Lagrangian Relaxation and Dynamic Programming. 199-207
Clocking and Time-Domain Measurements
- Payam Heydari, Massoud Pedram:
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective. 209-213 - Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl:
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. 214-220 - Kenneth L. Shepard, Yu Zheng:
On-Chip Oscilloscopes for Noninvasive Time-domain Measurement of Waveforms. 221-227
Processor Microarchitecture
- Juan L. Aragón, José González, José M. García, Antonio González:
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. 228-233 - Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya B. Gokhale:
Mutable Functional Units and Their Applications on Microprocessors. 234-239 - Qing Zhao, David J. Lilja:
Compiler-Directed Classification of Value Locality Behavior. 240-248 - Vadhiraj Sankaranarayanan, Akhilesh Tyagi:
A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage. 249-255
Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics
- Georg Pelz:
Designing Circuits for Disk Drives. 256-261 - James Jeppensen, Walt Allen, Steve Anderson, Michael Pilsl:
Hard Disk Controller: The Disk Drive's Brain and Body. 262-267 - Wolfgang Sereinig:
Motion-Control: The Power Side of Disk Drives. 268-275
Energy Efficiency Caches and Multiport Cache Structures
- Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger:
Static Energy Reduction Techniques for Microprocessor Caches. 276-283 - Deepak Limaye, Ryan N. Rakvic, John Paul Shen:
Parallel Cachelets. 284-292 - Bhooshan S. Thakar, Gyungho Lee:
Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors. 293-301
Control by Simulation and On-line Checking
- Dragos Lungeanu, Chuanjin Richard Shi:
Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits. 302-307 - Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller:
High Performance Parallel Fault Simulation. 308-313 - Seongwoo Kim, Arun K. Somani:
On-Line Integrity Monitoring of Microprocessor Control Logic. 314-321
CAD Algorithms for Physical Design
- Fan Mo, Abdallah Tabbara, Robert K. Brayton:
A Timing-Driven Macro-Cell Placement Algorithm. 322-327 - Saurabh N. Adya, Igor L. Markov:
Fixed-outline Floorplanning through Better Local Search. 328-334 - Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang:
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. 335-347
Formal Methods for Property Verification and Equivalence Verification
- Katarzyna Radecka, Zeljko Zilic:
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. 348-353 - Christoph Meinel, Christian Stangier:
Hierarchical Image Computation with Dynamic Conjunction Scheduling. 354-359 - Jin Yang, Carl-Johan H. Seger:
Introduction to Generalized Symbolic Trajectory Evaluation. 360-367
Hardware Representation
- William N. N. Hung, Xiaoyu Song:
BDD Variable Ordering by Scatter Search. 368-373 - Alicia Manthe, Chuanjin Richard Shi:
Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis. 374-379 - Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos:
Run-Time Execution of Reconfigurable Hardware in a Java Environment. 380-387
Circuit Techniques
- Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Realization of Multiple-Output Functions by Reconfigurable Cascades. 388-393 - Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong:
A Low-Power Cache Design for CalmRISCTM-Based Systems. 394-399 - Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time. 400-405 - Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. 406-414
DSP/Multimedia
- Deependra Talla, Lizy Kurian John:
Cost-effective Hardware Acceleration of Multimedia Applications. 415-424 - Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers:
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. 425-430 - Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis:
Low-Energy DSP Code Generation Using a Genetic Algorithm. 431-437 - Ali Manzak, Chaitali Chakrabarti:
Voltage Scaling for Energy Minimization with QoS Constraints. 438-446
Novel Architectures and ISA Extensions
- Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan:
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. 447-452 - John Patrick McGregor, Ruby B. Lee:
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications. 453-461 - Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura:
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. 462-467 - Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Use of Local Memory for Efficient Java Execution. 468-476
Poster Papers
- Afzal Hossain, Daniel J. Pease:
An Analytical Model for Trace Cache Instruction Fetch Performance. 477-480 - Jiang Hu, Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement. 481-483 - Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh:
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. 484-487 - Felix Sheng-Ho Chang, Alan J. Hu:
Fast Specification of Cycle-accurate Processor Models. 488-492 - Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang:
A Performance Analysis of the Active Memory System. 493-496 - Kent E. Wires, Michael J. Schulte, James E. Stine:
Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. 497-500 - Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
An Algorithm for Dynamically Reconfigurable FPGA Placement. 501-504 - Pradeepsunder Ganesh, Charlie Chung-Ping Chen:
RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. 505-506 - James W. Hauser, Carla Neaderhouser Purdy:
Efficient Function Approximation for Embedded and ASIC Applications. 507-510 - Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park:
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. 511-512 - Hong-Sik Kim, Jin-kyue Lee, Sungho Kang:
A Heuristic for Multiple Weight Set Generation. 513-514 - Prosenjit Chatterjee, Ganesh Gopalakrishnan:
towards A formal Model of Shared Memory Consistency for Intel ItaniumTM. 515-518 - Jennifer L. White, Moon-Jung Chung, Anthony S. Wojcik, Travis E. Doom:
Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem. 519-522 - Halima El Naga, Jean-Luc Gaudiot:
MCOMA: A Multithreaded COMA Architecture. 523-525 - Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar:
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. 526-529 - Pipat Reungsang, Sun Kyu Park, Seh-Woong Jeong, Hyung-Lae Roh, Gyungho Lee:
Reducing Cache Pollution of Prefetching in a Small Data Cache. 530-533 - Rajesh Ramanujam, Murali Ravirala, Gyungho Lee:
Alloyed Path-pattern Scheme for Branch Prediction. 534-537 - Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Timing Characterization of Dual-edge Triggered Flip-flops. 538-541 - A. Murat Fiskiran, Ruby B. Lee:
Performance Impact of Addressing Modes on Encryption Algorithms. 542-545 - Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. 546-552 - James D. Z. Ma, Arvind Parihar, Lei He:
Pre-routing Estimation of Shielding for RLC Signal Integrity. 553-556
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