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ORCIDICCD 1999: Austin, Texas, USA
- Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999. IEEE Computer Society 1999, ISBN 0-7695-0406-X
Session 1.1.1: Keynote Address
- Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli:
System Design: Traditional Concepts and New Paradigms. 2-13 - Kurt Keutzer, A. Richard Newton:
The MARCO/DARPA Gigascale Silicon Research Center. 14-
Session 1.3.1: Embedded Tutorial
- Wayne H. Wolf:
CAD Techniques for Embedded Systems-on-Silicon. 24-
Session 1.3.2: Applied Verification Techniques
- Eduard Cerny, Fen Jin:
Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. 32-39 - Abhijit Ghosh, Ranga Vemuri:
Formal Verification of Synthesized Analog Designs. 40-45 - Ted Stanion:
Implicit Verification of Structurally Dissimilar Arithmetic Circuits. 46-50 - Dirk W. Hoffmann, Thomas Kropf:
Automatic Error Correction of Tri-State Circuits. 51-
Session 1.3.3: Computer Arithmetic
- Sumio Morioka
, Yasunao Katayama:
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. 60-67 - Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.:
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. 68-72 - Tomás Lang, Javier D. Bruguera:
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. 73-79 - William L. Freking, Keshab K. Parhi:
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations. 80-
Session 1.4.1: Machines and Characterization
- Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer:
Designing the M·CORETM M3 CPU Architecture. 94-101 - Mike Clark, Lizy Kurian John:
Performance Evaluation of Configurable Hardware Features on the AMD-K5. 102-107 - Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep Lluís Larriba-Pey, Bob Knighten, Youjip Won:
Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. 108-
Session 1.4.2: Power and Noise Considerations in Microprocessor Design
- Nathan Kalyanasundharam, Nital Patwa:
Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. 118-123 - Srivatsan Srinivasan, Lizy Kurian John:
On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors. 124-130 - William Fornaciari, Donatella Sciuto, Cristina Silvano:
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. 131-
Session 1.4.3: Architectures for Embedded Systems
- Tor E. Jeremiassen:
A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. 138-145 - David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor:
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. 146-151 - You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
Customization of a CISC Processor Core for Low-Power Applications. 152-
Session 1.4.4: Built-In Self Test
- Hangkyu Lee, Sungho Kang:
A New Weight Set Generation Algorithm for Weighted Random Pattern Generation. 160-165 - Christian Dufaza:
Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. 166-174 - Paul Chang, Brion L. Keller, Sarala Paliwal:
Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. 175-
Session 1.5.1: Intelligent Memory
- Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim:
Design and Evaluation of a Selective Compressed Memory System. 184-191 - Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik:
FlexRAM: Toward an Advanced Intelligent Memory System. 192-201 - Mark Oskin, Frederic T. Chong, Timothy Sherwood:
ActiveOS: Virtualizing Intelligent Memory. 202-
Session 1.5.2: Performance and Area Optimization
- I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou:
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. 210-215 - K. K. Lee, D. F. Wong:
An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. 216-221 - Chunhong Chen, Majid Sarrafzadeh:
An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. 222-
Session 1.5.3: VLSI Implementation of Arithmetic Circuits
- Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy:
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. 230-235 - Alberto Nannarelli, Tomás Lang:
Low-Power Radix-4 Combined Division and Square Root. 236-242 - Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. 243-
Session 1.5.4: Design Convergence
- Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking:
A Robust Solution to the Timing Convergence Problem in High-Performance Design. 250-257 - Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy:
Performance Driven Optimization of Network Length in Physical Placement. 258-265 - Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi:
Efficient Crosstalk Estimation. 266-
Session 1.6: Poster Presentations
- Hasan Cam, Mostafa I. H. Abd-El-Barr, Sadiq M. Sait:
A High-Performance Hardware-Efficient Memory Allocation Technique and Design. 274-276 - Rolf Hakenes, Yiannos Manoli:
Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter. 277-278 - Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada:
A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. 279-280 - Ramesh Radhakrishnan, Juan Rubio, Lizy Kurian John:
Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels. 281-284 - Avinash K. Gautam, V. Visvanathan, S. K. Nandy:
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. 285-288 - G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim:
Yield Optimization by Design Centering and Worst-Case Distance Analysis. 289-290 - Tom Thomas, Brian W. Anthony:
Area, Performance, and Yield Implications of Redundancy in On-Chip Caches. 291-292 - Walling R. Cyre:
Conceptual Modeling and Simulation. 293-296 - Peter James Aldworth:
System-on-a-Chip Bus Architecture for Embedded Applications. 297-298 - Kyoung-Mook Lim, Seh-Woong Jeong, Yong-Chun Kim, Seung-Jae Jeong, Hong-Kyu Kim, Yang-Ho Kim, Bong-Young Chung, Hyung-Lae Roh, H. S. Yang:
CalmRISCTM: A Low Power Microcontroller with Efficient Coprocessor Interface. 299-302 - Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
An Even Wiring Approach to the Ball Grid Array Package Routing. 303-306 - Per Lindgren, Rolf Drechsler, Bernd Becker:
Synthesis of Pseudo Kronecker Lattice Diagrams. 307-310 - Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang:
Generic Universal Switch Blocks. 311-314 - Ronald W. Mehler, M. Ray Mercer:
Multi-Level Logic Minimization through Fault Dictionary Analysis. 315-318 - Kang Yi, Seong Yong Ohm:
A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping. 319-320 - Ashok Kumar, Magdy A. Bayoumi:
Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis. 321-324 - Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Efficient Functional Coverage Test for HDL Descriptions at RTL. 325-327 - Hyunjin Kim, Jongchul Shin, Sungho Kang:
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. 328-329 - Jaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis:
On-Line BIST for Testing Analog Circuits. 330-
Session 2.2.1: System Level Issues
- Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.:
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. 340-347 - Sari L. Coumeri, Donald E. Thomas:
An Environment for Exploring Low Power Memory Configurations in System Level Design. 348-353 - Brandon M. Bachman, Hao Zheng, Chris J. Myers:
Architectural Synthesis of Timed Asynchronous Systems. 354-363 - Hen-Ming Lin, Jing-Yang Jou:
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. 364-
Session 2.2.2: Compilers and Algorithms
- Steven P. Vanderwiel, David J. Lilja:
A Compiler-Assisted Data Prefetch Controller. 372-377 - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis:
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. 378-383 - Priyadarshan Kolte, Roger Smith, Su Wen:
A Fast Median Filter Using AltiVec. 384-391 - Guo-Hui Lin, Guoliang Xue, Defang Zhou:
Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees. 392-
Session 2.2.3: Test Generation and Delay Testing
- Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu:
On Detecting Bridges Causing Timing Failures. 400-406 - Jacob Savir:
Design for Testability to Combat Delay Faults. 407-411 - Irith Pomeranz, Sudhakar M. Reddy:
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. 412-417 - Abhijit Jas, Nur A. Touba:
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. 418-
Session 2.3.1: Microarchitecture
- Lucian Codrescu, D. Scott Wills:
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. 428-435 - Chi-Hung Chi, Jun-Li Yuan:
Load-Balancing Branch Target Cache and Prefetch Buffer. 436-441 - Akhilesh Tyagi, Hon-Chi Ng, Prasant Mohapatra:
Dynamic Branch Decoupled Architecture. 442-
Session 2.3.2: Efficient State-Space Exploration
- Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham:
Improving Witness Search Using Orders on States. 452-457 - Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya:
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. 458-466 - Kavita Ravi, Fabio Somenzi:
Efficient Fixpoint Computation for Invariant Checking. 467-
Session 2.3.3: Clocking and Analog Circuit Prototyping
- Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria:
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. 476-481 - Sree Ganesan, Ranga Vemuri:
A Methodology for Rapid Prototyping of Analog Systems. 482-488 - Matthew E. Becker, Thomas F. Knight Jr.:
Transmission Line Clock Driver. 489-
Session 2.3.4: Embedded Tutorial
- Alan Weiss:
Benchmarking, Selection and Debugging of Microcontrollers. 492-498 - Ronald Stence:
A New Development Tool with the IEEE-ISTO. 499-502 - Ronald Stence:
32-Bit Architectures for Embedded Systems. 503-
Invited Session 2.4.1: Digital Signal Processors
- Donald Steiss:
The Specialization of General Purpose Processor Architecture Elements for Programmable Digital Signal Processors. 512-515 - Uming Ko, Mike McMahan, Edgar Auslander:
DSP for the Third Generation Wireless Communications. 516-520 - Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor:
Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. 521-
Session 2.4.2: Caching Approaches
- Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin:
Pursuing the Performance Potential of Dynamic Cache Line Sizes. 528-537 - Brian R. Fisk, R. Iris Bahar:
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. 538-545 - Pedro Trancoso, Josep Torrellas:
Cache Optimization for Memory-Resident Decision Support Commercial Workloads. 546-
Session 2.4.3: CMOS Circuit Design Techniques
- Qi Wang, Sarma B. K. Vrudhula:
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. 556-562 - Maitham Shams, Mohamed I. Elmasry:
Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. 563-568 - Tyler Thorp, Gin Yee, Carl Sechen:
Design and Synthesis of Monotonic Circuits. 569-572 - J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak:
SOI Implementation of a 64-Bit Adder. 573-
Session 3.1: Plenary
- Harvey G. Cragon:
Forty Five Years of Computer Architecture-All That's Old is New Again. 576-
Invited Session 3.2.1
- A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans:
TriMedia CPU64 Application Domain and Benchmark Suite. 580-585 - Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel:
TriMedia CPU64 Architecture. 586-592 - Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt:
TriMedia CPU64 Application Development Environment. 593-598 - Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans:
TriMedia CPU64 Design Space Exploration. 599-
Session 3.2.2: Logic Synthesis
- Imtiaz Ahmad, Raza Ul-Mustafa:
On State Assignment of Finite State Machines Using Hypercube Embedding Approach. 608-613 - Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi:
Synthesis of Arrays and Records. 614-619 - Rupesh S. Shelar, Madhav P. Desai, H. Narayanan:
Decomposition of Finite State Machines for Area, Delay Minimization. 620-625 - Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal:
BDD Decomposition for Efficient Logic Synthesis. 626-
Session 3.2.3: Hardware Software Partitioning and Synthesis
- Felice Balarin, Massimiliano Chiodo:
Software Synthesis for Complex Reactive Embedded Systems. 634-639 - Romain Kamdem, Alain Fonkoua, Andre Zenatti:
Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory. 640-645 - Xiaohan Zhu, Bill Lin:
Compositional Software Synthesis of Communicating Processes. 646-651 - Gang Quan, Xiaobo Hu, Garrison W. Greenwood:
Preference-Driven Hierarchical Hardware/Software Partitioning. 652-
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