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ORCID27th Asian Test Symposium 2018: Hefei, China
- 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018. IEEE 2018, ISBN 978-1-5386-9466-4
Session 1A: 3D/NOC Testing
- Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri
, Hafizur Rahaman:
Identification of Faulty TSV with a Built-In Self-Test Mechanism. 1-6 - Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design. 7-12 - Aijun Zhu, Duanyong Chen, Chuan-pei Xu, Cong Hu, Aiguo Song:
A Fault Check Graph Approach for Photonic Router in Network on Chip. 13-18
Session 1B: Memory BIST and Logic BIST
- Meng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu:
A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit. 19-24 - Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai:
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. 25-29 - Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara:
On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST. 30-35
Session 2A: DFT and Secure DFT
- Amitava Majumdar, Balakrishna Jayadev:
Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. 36-41 - Tian Chen, Chenxin Lin, Huaguo Liang, Fuji Ren:
A Dictionary-Based Test Data Compression Method Using Tri-State Coding. 42-47 - Chia-Chi Wu, Man-Hsuan Kuo, Kuen-Jong Lee:
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks. 48-53
Session 2B: Design on FPGAs
- Gaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou:
A Low-Cost High-Efficiency True Random Number Generator on FPGAs. 54-58 - Xiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu:
An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs. 59-62 - Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao:
A High Reliability FPGA Chip Identification Generator Based on PDLs. 63-67
Session 3A: Hardware Trojan Design and Detection
- Jing Ye, Yu Hu, Xiaowei Li:
Hardware Trojan in FPGA CNN Accelerator. 68-73 - Tien-Hung Tseng, Shou-Chun Li, Kai-Chiang Wu:
Lifetime Reliability Trojan Based on Exploring Malicious Aging. 74-79 - Wei Zhao, Haihua Shen, Huawei Li, Xiaowei Li:
Hardware Trojan Detection Based on Signal Correlation. 80-85
Session 3B: Aging Analysis and Minimization
- Aibin Yan, Yafei Ling, Kang Yang, Zhili Chen, Maoxiang Yi:
Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS. 86-91 - Chang Liu, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, Hans-Joachim Wunderlich:
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 92-97 - Shengyu Duan, Basel Halak, Mark Zwolinski:
Cell Flipping with Distributed Refresh for Cache Ageing Minimization. 98-103
Session 4A: Design for Hardware Security
- Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li:
A New Scheme to Extract PUF Information by Scan Chain. 104-108 - Yueying Han, Xiaoxiao Wang, Mark Tehranipoor:
CIPA: Concurrent IC and PCB Authentication Using On-chip Ring Oscillator Array. 109-114 - Qingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li:
PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model. 115-120
Session 4B: Fault Tolerance and Error Tolerance
- Zhengfeng Huang, Yangyang Zhang, Zian Su, Huaguo Liang, Huijie Yao, Tianming Ni:
A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE. 121-126 - Christian M. Fuchs, Nadia M. Murillo, Aske Plaat, Erik van der Kouwe, Peng Wang:
Towards Affordable Fault-Tolerant Nanosatellite Computing with Commodity Hardware. 127-132 - Shuhao Jiang, Jiajun Li, Xin He, Guihai Yan, Xuan Zhang, Xiaowei Li:
RiskCap: Minimizing Effort of Error Regulation for Approximate Computing. 133-138
Session 5A: Low Power Design and Testing
- Yiming Ouyang, Lizhu Hu, Yifeng Wu, Jianfeng Yang, Kun Xing:
Dynamic Fine-Grain Power Gating Design in WiNoC. 139-148 - Yucong Zhang, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara, Hans-Joachim Wunderlich, Jun Qian:
Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. 149-154 - Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima:
Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST. 155-160
Session 5B: Reliable Memory
- Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase:
Progressive ECC Techniques for Phase Change Memory. 161-166 - Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue:
Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage. 167-172 - Tsung-Chu Huang, Jeffae Schroff:
Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. 173-178
Session 6A: Design and Test for Emerging Technologies
- Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Digital Rights Management for Paper-Based Microfluidic Biochips. 179-184 - Sourav Ghosh, Hafizur Rahaman, Chandan Giri:
Test Diagnosis of Digital Microfluidic Biochips Using Image Segmentation. 185-190 - Jun-Yang Lei, Thomas Moon, Justin Chow, Suresh K. Sitaraman, Abhijit Chatterjee:
A Monobit Built-In Test and Diagnostic System for Flexible Electronic Interconnect. 191-196
Session 6B: Mixed Signal Designs and ATE
- Yuto Sasaki, Yujie Zhao, Anna Kuwana, Haruo Kobayashi:
Highly Efficient Waveform Acquisition Condition in Equivalent-Time Sampling System. 197-202 - Kosuke Machida, Uni Ozawa, Yudai Abe, Haruo Kobayashi:
Time-to-Digital Converter Architectures Using Two Oscillators with Different Frequencies. 203-208 - Guan-Hao Hou, Wei-Chen Huang, Jiun-Lang Huang, Terry Kuo:
Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter. 209-214
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