"Generation of Synthesizable Verilog Code From Natural Language Specifications."

Daniil S. Yashchenko et al. (2026)

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DOI: 10.1109/ACCESS.2026.3651684

access: open

type: Journal Article

metadata version: 2026-01-20

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Daniil S. Yashchenko, Aleksandr Yu. Romanov, Artur A. Ziazetdinov, Dmitry V. Telpukhov, Roman A. Solovyev:
Generation of Synthesizable Verilog Code From Natural Language Specifications. IEEE Access 14: 4990-5001 (2026)

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