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ORCIDJürgen Teich
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- affiliation: University of Erlangen-Nuremberg, Germany
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2020 – today
- 2025
[j129]Muhammad Sabih
, Mohamed Abdo, Frank Hannig, Jürgen Teich:
Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks Using RISC-V Custom Functional Units. IEEE Embed. Syst. Lett. 17(5): 329-332 (2025)- [j128]Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich:
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(4): 1250-1261 (2025) - [j127]Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich:
Combining Multi-Objective Bayesian Optimization with Reinforcement Learning for TinyML. ACM Trans. Evol. Learn. Optim. 5(3): 17:1-17:21 (2025) - [c517]Tobias Hahn, Jan Hofmann, Stefan Wildermann, Jürgen Teich:
FSST Compression of JSON Data on FPGAs. ARCS 2025: 48-62 - [c516]Nils Wilbert, Matthias Szymanski, Stefan Wildermann, Henriette Herzog, Timo Hönig, Jürgen Teich:
CHaOS: A Persistent Lightweight Cache Hybridization-Aware OS. ARCS 2025: 63-78 - [c515]José Juan Hernández Morales, Frank Hannig, Jürgen Teich:
A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices. ARCS 2025: 172-188 - [c514]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. ASP-DAC 2025: 1160-1166 - [c513]Stefan Wildermann, Nils Wilbert, Tobias Häberlein, Jürgen Teich:
Self-powered Embedded Systems: The Role of Non-volatile Memory Technology in IoT Devices. Go Where the Bugs Are 2025: 155-177 - [c512]Tobias Hahn, Maximilian S. Langohr, Stefan Meißner, Benedikt Döring, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich:
ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. BTW 2025: 899-906 - [c511]Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali:
Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. CODES+ISSS 2025: 23-32 - [c510]Jan Spieck, Dominik Walter, Jan Waschkeit, Jürgen Teich:
Co-Design of Sustainable Embedded Systems-on-Chip. DATE 2025: 1-2 - [c509]Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn:
Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). DATE 2025: 1-6 - [c508]Basile Darne, Abrarul Karim, Paul-Antoine Matrangolo, Joachim Falk, Ian O'Connor, Cédric Marchand, Alberto Bosio, Jürgen Teich:
Special Session Paper: FeMFET-Based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. DFT 2025: 1-8 - [c507]Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich:
Multi-Objective Bayesian Optimization with Reinforcement Learning for Edge Deployment of DNNs on Microcontrollers. GECCO Companion 2025: 19-20 - [c506]Jan Spieck, Dominik Walter, Jan Waschkeit, Jürgen Teich:
Co-Design of Systems-On-Chip for Sustainability. NG-RES@HiPEAC 2025: 3:1-3:12 - [c505]Paul Krüger, Stefan Wildermann, Jürgen Teich:
Breaking Confidentiality of XTS-AES Encrypted Data at Rest on Microprocessors Using Electromagnetic Side-Channel Attacks. HOST 2025: 450-461 - [c504]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Run-Time Requirement Enforcement of Safety Requirements of Human-Robot Interactions. ICARA 2025: 111-115 - [c503]Batuhan Sesli, Muhammad Sabih, Frank Hannig, Jürgen Teich:
Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. ICCAD 2025: 1-9 - [c502]Pierre-Louis Sixdenier, Mark Deutel, Jürgen Teich:
Early-Exit Neural Architecture Search for Energy-Harvesting Edge Computing. MCSoC 2025: 372-379 - [c501]Mark Deutel, Axel Plinge, Dominik Seuß, Christopher Mutschler, Frank Hannig, Jürgen Teich:
Unsupervised Learning of Variational Autoencoders on Cortex-M Microcontrollers. MCSoC 2025: 469-476 - [i49]Yun-Chih Chen, Tristan Taylan Seidl, Nils Hölscher, Christian Hakert, Minh Duy Truong, Jian-Jia Chen, João Paulo C. de Lima, Asif Ali Khan, Jerónimo Castrillón, Ali Nezhadi, Lokesh Siddhu, Hassan Nassar, Mahta Mayahinia, Mehdi Baradaran Tahoori, Jörg Henkel, Nils Wilbert, Stefan Wildermann, Jürgen Teich:
Modeling and Simulating Emerging Memory Technologies: A Tutorial. CoRR abs/2502.10167 (2025) - [i48]Dominik Walter, Marita Halm, Daniel Seidel, Indrayudh Ghosh, Christian Heidorn, Frank Hannig, Jürgen Teich:
Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs. CoRR abs/2502.12062 (2025) - [i47]Dominik Walter, Marita Halm, Daniel Seidel, Indrayudh Ghosh, Christian Heidorn, Frank Hannig, Jürgen Teich:
Evaluation of CGRA Toolchains. CoRR abs/2502.19114 (2025) - [i46]Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich:
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. CoRR abs/2504.19659 (2025) - 2024
- [j126]Martín Letras, Joachim Falk, Jürgen Teich:
Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems. IEEE Access 12: 39748-39769 (2024) - [j125]Christian Heidorn, Muhammad Sabih, Nicolai Meyerhöfer, Christian Schinabeck, Jürgen Teich, Frank Hannig:
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. 52(1-2): 40-58 (2024) - [j124]Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-43 (2024) - [j123]Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. 17(2): 24:1-24:28 (2024) - [c500]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC 2024: 3-18 - [c499]Dominik Walter, Thomas Adamtschuk, Frank Hannig, Jürgen Teich:
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. ASAP 2024: 97-106 - [c498]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. DATE 2024: 1-2 - [c497]Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich:
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE 2024: 1-2 - [c496]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. DDECS 2024: 79-85 - [c495]Nils Wilbert, Stefan Wildermann, Jürgen Teich:
To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches. DIMES@SOSP 2024: 17-24 - [c494]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
DSL-Based SNN Accelerator Design Using Chisel. DSD 2024: 176-184 - [c493]Paul Krüger, Stefan Wildermann, Jürgen Teich:
CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. EuroSec@EUROSYS 2024: 37-43 - [c492]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. FPL 2024: 11-18 - [c491]Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich:
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. ICFPT 2024: 1-9 - [c490]Khalil Esper, Jürgen Teich:
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. NG-RES@HiPEAC 2024: 4:1-4:11 - [c489]Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich:
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS 2024: 1-5 - [c488]Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. MECO 2024: 1-5 - [c487]Abrarul Karim, Joachim Falk, Dennis Schmidt, Jürgen Teich:
Self-Powering Dataflow Networks - Concepts and Implementation. MEMOCODE 2024: 69-74 - [c486]Nils Wilbert, Stefan Wildermann, Jürgen Teich:
Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. MEMSYS 2024: 257-269 - [c485]Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich:
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS 2024: 64-75 - [d3]Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich:
Combining Multi-Objective Bayesian Optimization with Reinforcement Learning for TinyML (Code). Zenodo, 2024
- [i45]Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich:
OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR abs/2404.15833 (2024) - [i44]Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich:
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR abs/2407.10734 (2024) - [i43]Mark Deutel, Christopher Mutschler, Jürgen Teich:
microYOLO: Towards Single-Shot Object Detection on Microcontrollers. CoRR abs/2408.15865 (2024) - 2023
- [j122]Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich:
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test 40(3): 5-7 (2023) - [j121]Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation. ACM Trans. Embed. Comput. Syst. 22(4): 73:1-73:24 (2023) - [j120]Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. 28(1): 4:1-4:40 (2023) - [j119]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. 28(6): 98:1-98:20 (2023) - [c484]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW 2023: 729-749 - [c483]Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES 2023: 11-20 - [c482]Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich:
Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE 2023: 133-139 - [c481]Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen:
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys 2023: 87-93 - [c480]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL 2023: 189-196 - [c479]Martín Letras, Joachim Falk, Jürgen Teich:
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. NG-RES@HiPEAC 2023: 6:1-6:13 - [c478]Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC 2023: 7:1-7:16 - [c477]Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich:
Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression. MBMV 2023: 1-12 - [c476]Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jürgen Teich:
Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. MEMOCODE 2023: 23-35 - [c475]Mark Deutel, Christopher Mutschler, Jürgen Teich:
μYOLO: Towards Single-Shot Object Detection on Microcontrollers. PKDD/ECML Workshops (5) 2023: 163-169 - [i42]Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich:
Augmented Random Search for Multi-Objective Bayesian Optimization of Neural Networks. CoRR abs/2305.14109 (2023) - [i41]Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze:
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR abs/2306.12742 (2023) - [i40]Martín Letras, Joachim Falk, Jürgen Teich:
Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems. CoRR abs/2311.17473 (2023) - 2022
- [j118]Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich:
Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access 10: 33787-33802 (2022) - [j117]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34(14) (2022) - [j116]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64(3): 89-98 (2022) - [j115]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 3767-3778 (2022) - [j114]Jan Spieck, Stefan Wildermann, Jürgen Teich:
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4289-4300 (2022) - [j113]Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich:
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2661-2666 (2022) - [j112]Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich:
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 345-366 (2022) - [j111]Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 7:1-7:27 (2022) - [c474]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS 2022: 65-74 - [c473]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. DATE 2022: 250-255 - [c472]Muhammad Sabih, Frank Hannig, Jürgen Teich:
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys 2022: 109-115 - [c471]Jens Trautmann, Jürgen Teich, Stefan Wildermann:
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM 2022: 1-9 - [c470]Patrick Plagwitz, Frank Hannig, Jürgen Teich:
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL 2022: 17-23 - [c469]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL 2022: 94-100 - [c468]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL 2022: 160-166 - [c467]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
Auto-Tuning of Raw Filters for FPGAs. FPL 2022: 167-175 - [c466]Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich:
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC 2022: 1-8 - [c465]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC 2022: 2:1-2:13 - [c464]Peter Brand, Benjamin Hackenberg, Joachim Falk, Jürgen Teich:
Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. IWCMC 2022: 647-652 - [c463]Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich:
Hardware-Aware Evolutionary Filter Pruning. SAMOS 2022: 283-299 - [c462]Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich:
SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS 2022: 329-345 - [i39]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR abs/2203.11028 (2022) - [i38]Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich:
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR abs/2203.12437 (2022) - [i37]Chetana Pradhan, Martín Letras, Jürgen Teich:
Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. CoRR abs/2204.02443 (2022) - [i36]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. CoRR abs/2205.05464 (2022) - [i35]Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich:
Deployment of Energy-Efficient Deep Learning Models on Cortex-M based Microcontrollers using Deep Compression. CoRR abs/2205.10369 (2022) - [i34]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR abs/2206.10368 (2022) - 2021
- [j110]Frank Hannig, Jürgen Teich:
Open Source Hardware. Computer 54(10): 111-115 (2021) - [j109]Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - [j108]Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich:
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21(1): 55-64 (2021) - [j107]M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig:
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18(3): 765-777 (2021) - [j106]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20(5): 49:1-49:31 (2021) - [j105]Faramarz Khosravi, Alexander Raß, Jürgen Teich:
Efficient Computation of Probabilistic Dominance in Multi-objective Optimization. ACM Trans. Evol. Learn. Optim. 1(4): 15:1-15:26 (2021) - [j104]Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich:
Adaptive Predictive Power Management for Mobile LTE Devices. IEEE Trans. Mob. Comput. 20(8): 2518-2535 (2021) - [j103]Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich:
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Trans. Design Autom. Electr. Syst. 26(3): 18:1-18:33 (2021) - [c461]Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich:
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC 2021: 242-253 - [c460]Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann:
Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems 2021: 125-149 - [c459]Peter Brand, Joachim Falk, Tanja Maier, Jürgen Teich:
Simulating Realistic IoT Network Traffic Using Similarity-based DSE. CSCI 2021: 1377-1380 - [c458]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Approximate Logic Synthesis of Very Large Boolean Networks. DATE 2021: 1552-1557 - [c457]Muhammad Sabih, Frank Hannig, Jürgen Teich:
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops 2021: 166-174 - [c456]Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c455]Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich:
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM 2021: 10-19 - [c454]Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
Choice - A Tunable PUF-Design for FPGAs. FPL 2021: 38-44 - [c453]Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL 2021: 388 - [c452]Khalil Esper, Stefan Wildermann, Jürgen Teich:
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC 2021: 1:1-1:12 - [c451]Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor:
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD 2021: 1-9 - [c450]Bo Qiao, Jürgen Teich, Frank Hannig:
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops 2021: 387-396 - [c449]Peter Brand, Joachim Falk, Eduard Potwigin, Jürgen Teich:
Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. ISNCC 2021: 1-6 - [c448]Martín Letras, Joachim Falk, Jürgen Teich:
Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. MBMV 2021: 1-11 - [c447]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE 2021: 21-31 - [c446]Dominik Walter, Jürgen Teich:
LION: real-time I/O transfer control for massively parallel processor arrays. MEMOCODE 2021: 32-43 - [c445]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD 2021: 1-6 - [c444]Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS 2021: 1-5 - [c443]Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich:
Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. PKDD/ECML Workshops (1) 2021: 375-389 - [c442]Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich:
Aarith: an arbitrary precision number library. SAC 2021: 529-534 - [c441]Stefan Groth, Jürgen Teich, Frank Hannig:
Efficient Application of Tensor Core Units for Convolving Images. SCOPES 2021: 1-6 - [i33]Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich:
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR abs/2101.04395 (2021) - [i32]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR abs/2105.05588 (2021) - 2020
- [j102]Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich:
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63(5): 74-80 (2020) - [j101]M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig:
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3202-3214 (2020) - [c440]Bo Wang, Aneek Imtiaz, Joachim Falk, Michael Glaß, Jürgen Teich:
Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-Specific Multi-core SoCs. ARCS 2020: 153-167 - [c439]Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP 2020: 157-164 - [c438]Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann:
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC 2020: 629-636 - [c437]Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig:
A runtime system for finite element methods in a partitioned global address space. CF 2020: 39-48 - [c436]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. DAC 2020: 1-6 - [c435]Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC 2020: 1-6 - [c434]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. DAC 2020: 1-6 - [c433]Fedor Smirnov, Behnaz Pourmohseni, Jürgen Teich:
Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems. DATE 2020: 957-962 - [c432]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich:
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT 2020: 639-642 - [c431]Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende:
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops 2020: 185-196 - [c430]Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich:
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. NG-RES@HiPEAC 2020: 2:1-2:13 - [c429]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems.