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ORCIDXiangyu Dong 0001
Person information
- affiliation: Qualcomm Technology, Inc., San Diego, CA, USA
Other persons with the same name
- Xiangyu Dong — disambiguation page
- Xiangyu Dong 0002
![[0009-0009-6312-8160]](https://dblp.org/img/orcid-mark.12x12.png "0009-0009-6312-8160")
— Chinese University of Hong Kong, Hong Kong - Xiangyu Dong 0003 — Beijing Institute of Technology Beijing, China
- Xiangyu Dong 0004 — University of Notre Dame, Notre Dame, IN, USA
- Xiangyu Dong 0005 — School of Remote Sensing and Information Engineering, Wuhan University, Wuhan, China
- Xiangyu Dong 0006 — henyang Normal University, Shenyang, Liaoning, China
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2010 – 2019
- 2014
[j9]Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
Endurance-aware cache line management for non-volatile caches. ACM Trans. Archit. Code Optim. 11(1): 4:1-4:25 (2014)- [j8]Jue Wang, Xiangyu Dong, Yuan Xie:
Preventing STT-RAM Last-Level Caches from Port Obstruction. ACM Trans. Archit. Code Optim. 11(3): 23:1-23:19 (2014) - [j7]Jue Wang, Xiangyu Dong, Yuan Xie:
Building and Optimizing MRAM-Based Commodity Memories. ACM Trans. Archit. Code Optim. 11(4): 36:1-36:22 (2014) - [c26]Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie:
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. ICCAD 2014: 301-308 - [c25]Jue Wang, Xiangyu Dong, Yuan Xie:
ProactiveDRAM: A DRAM-initiated retention management scheme. ICCD 2014: 22-27 - [c24]Jue Wang, Xiangyu Dong, Yuan Xie:
Enabling high-performance LPDDRx-compatible MRAM. ISLPED 2014: 339-344 - 2013
- [j6]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. ACM Trans. Archit. Code Optim. 10(4): 23:1-23:22 (2013) - [c23]Jue Wang, Xiangyu Dong, Yuan Xie:
OAP: an obstruction-aware cache management policy for STT-RAM last-level caches. DATE 2013: 847-852 - [c22]Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi:
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. HPCA 2013: 234-245 - [c21]Nikolaos Strikos, Vasileios Kontorinis, Xiangyu Dong, Houman Homayoun, Dean M. Tullsen:
Low-current probabilistic writes for power-efficient STT-RAM caches. ICCD 2013: 511-514 - [c20]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. ISPASS 2013: 140-141 - 2012
- [j5]Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi:
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 994-1007 (2012) - [c19]Jue Wang, Xiangyu Dong, Yuan Xie:
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches. DAC 2012: 253-258 - 2011
- [j4]Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie:
Three-dimensional Integrated Circuits: Design, EDA, and Architecture. Found. Trends Electron. Des. Autom. 5(1-2): 1-151 (2011) - [j3]Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai (Helen) Li:
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET Comput. Digit. Tech. 5(3): 213-220 (2011) - [j2]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. 8(2): 6:1-6:29 (2011) - [c18]Xiangyu Dong, Yuan Xie:
AdaMS: Adaptive MLC/SLC phase-change memory design for file storage. ASP-DAC 2011: 31-36 - [c17]Jishen Zhao, Xiangyu Dong, Yuan Xie:
An energy-efficient 3D CMP design with fine-grained voltage scaling. DATE 2011: 539-542 - [c16]Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
Design implications of memristor-based RRAM cross-point structures. DATE 2011: 734-739 - [c15]Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie:
Energy-efficient multi-level cell phase-change memory system with data encoding. ICCD 2011: 175-182 - [c14]Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80 - [p1]Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Yuan Xie, Narayanan Vijaykrishnan:
Influence of Stacked 3D Memory/Cache Architectures on GPUs. 3D Integration for NoC-based SoC Architectures 2011: 249-271 - 2010
- [j1]Xiangyu Dong, Jishen Zhao, Yuan Xie:
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1959-1972 (2010) - [c13]Jing Xie, Xiangyu Dong, Yuan Xie:
3D memory stacking for fast checkpointing/restore applications. 3DIC 2010: 1-6 - [c12]Jing Xie, Jishen Zhao, Xiangyu Dong, Yuan Xie:
Architectural benefits and design challenges for three-dimensional integrated circuits. APCCAS 2010: 540-543 - [c11]Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie:
Energy and performance driven circuit design for emerging phase-change memory. ASP-DAC 2010: 193-198 - [c10]Jishen Zhao, Xiangyu Dong, Yuan Xie:
Cost-aware three-dimensional (3D) many-core multiprocessor design. DAC 2010: 126-131 - [c9]Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li:
Cost-driven 3D integration with interconnect layers. DAC 2010: 150-155 - [c8]Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie:
Energy- and endurance-aware design of phase change memory caches. DATE 2010: 136-141 - [c7]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC 2010: 1-11
2000 – 2009
- 2009
- [c6]Xiangyu Dong, Yuan Xie:
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). ASP-DAC 2009: 234-241 - [c5]Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen:
A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249 - [c4]Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. ICCAD 2009: 269-275 - [c3]Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie:
3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis. ICCD 2009: 254-259 - [c2]Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie:
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC 2009 - 2008
- [c1]Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Li, Yiran Chen:
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559
Coauthor Index
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