{"@attributes":{"name":"Toru Miyabo","pid":"396\/5259","n":"1"},"person":{"@attributes":{"key":"homepages\/396\/5259","mdate":"2025-02-04"},"author":"Toru Miyabo"},"r":{"article":{"@attributes":{"key":"journals\/jssc\/MatsumiyaKSOMKIMSS92","mdate":"2025-02-03"},"author":["Masato Matsumiya","Shoichiro Kawashima","Makoto Sakata","Masahiko Ookura","Toru Miyabo","Tom Koga","Kazuo Itabashi","Kazuhiro Mizutani","Hiroshi Shimada","Noriyuki Suzuki"],"title":"A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture.","pages":"1497-1503","year":"1992","month":"November","volume":"27","journal":"IEEE J. Solid State Circuits","number":"11","ee":"https:\/\/doi.org\/10.1109\/4.165328","url":"db\/journals\/jssc\/jssc27.html#MatsumiyaKSOMKIMSS92","stream":"streams\/journals\/jssc"}},"coauthors":{"@attributes":{"n":"9","nc":"1"},"co":[{"@attributes":{"c":"0"},"na":"Kazuo Itabashi"},{"@attributes":{"c":"0"},"na":"Shoichiro Kawashima"},{"@attributes":{"c":"0"},"na":"Tom Koga"},{"@attributes":{"c":"0"},"na":"Masato Matsumiya"},{"@attributes":{"c":"0"},"na":"Kazuhiro Mizutani"},{"@attributes":{"c":"0"},"na":"Masahiko Ookura"},{"@attributes":{"c":"0"},"na":"Makoto Sakata"},{"@attributes":{"c":"0"},"na":"Hiroshi Shimada"},{"@attributes":{"c":"0"},"na":"Noriyuki Suzuki"}]}}