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ORCIDInternational Journal of Reconfigurable Computing, Volume 2010
Volume 2010, 2010
- Yuet Ming Lam
, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk:
Multiloop Parallelisation Using Unrolling and Fission. 475620:1-475620:10 - Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Power Characterisation for Fine-Grain Reconfigurable Fabrics. 787405:1-787405:9 - Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps, Gustavo Sutter:
High-Speed FPGA 10's Complement Adders-Subtractors. Int. J. Reconfigurable Comput. 2010: 219764:1-219764:14 (2010) - Hanyu Liu, Ali Akoglu:
Timing-Driven Nonuniform Depopulation-Based Clustering. 158602:1-158602:11 - Sergio Ruben Geninatti, José Ignacio Benavides Benítez, Manuel Hernandez Calviño, Nicolás Guil Mata:
Concurrent Calculations on Reconfigurable Logic Devices Applied to the Analysis of Video Images. 962057:1-962057:8 - Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. 390545:1-390545:15 - Shahnam Mirzaei, Ryan Kastner, Anup Hosangadi:
Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs. 697625:1-697625:17 - Miaoqing Huang, Olivier Serres, Tarek A. El-Ghazawi, Gregory B. Newby:
Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study. 454506:1-454506:11 - Elias Todorovich, Valentin Obac Roda:
Selected Papers from SPL 2009: Programmable Logic and Applications. 714270:1-714270:2 - Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA. 980762:1-980762:20 - Mariam Hoseini, Tan Zhou, Chao You, Mark Pavicic:
Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing. 352428:1-352428:11 - Shoaib Akram, Alexandros Papakonstantinou, Rakesh Kumar, Deming Chen:
A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. 205852:1-205852:22 - Vitor de Paulo, Cristinel Ababei:
3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans. 603059:1-603059:12 - Zachary K. Baker, Mark E. Dunham, Keith Morgan, Michael Pigue, Matthew Stettler, Paul S. Graham, Eric N. Schmierer, John Power:
Space-Based FPGA Radio Receiver Design, Debug, and Development of a Radiation-Tolerant Computing System. 546217:1-546217:12 - Lev Kirischian, Victor Dumitriu, Pil Woo Chun, Galina Okouneva:
Mechanism of Resource Virtualization in RCS for Multitask Stream Applications. 159367:1-159367:13 - Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. 375245:1-375245:12 - Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA. 357839:1-357839:13 - Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera:
Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic. 357978:1-357978:14 - Taho Dorta, Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa:
Reconfigurable Multiprocessor Systems: A Review. 570279:1-570279:10 - Rafael A. Arce-Nazario, Edusmildo Orozco, Dorothy Bollman:
Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm. 313479:1-313479:14 - Jorge Alberto Surís, Adolfo Recio, Peter M. Athanas:
RapidRadio: A Domain-Specific Productivity Enhancing Framework. 492560:1-492560:15 - John A. Kalomiros, John N. Lygouras:
Robotic Mapping and Localization with Real-Time Dense Stereo on Reconfigurable Hardware. 480208:1-480208:17 - Stephanie Drzevitzky, Uwe Kastens, Marco Platzner:
Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. 180242:1-180242:11 - Nathalie Bochard, Florent Bernard, Viktor Fischer, Boyan Valtchanov:
True-Randomness and Pseudo-Randomness in Ring Oscillator-Based True Random Number Generators. 879281:1-879281:13 - James Coole, Greg Stitt:
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. 652620:1-652620:16 - Stefan Döbrich, Christian Hochberger:
Low-Complexity Online Synthesis for AMIDAR Processors. Int. J. Reconfigurable Comput. 2010: 953693:1-953693:15 (2010) - Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Jose M. Motta:
A Reconfigurable System Approach to the Direct Kinematics of a 5 D.o.f Robotic Manipulator. 727909:1-727909:10 - Lionel Torres, Viktor K. Prasanna:
Selected Papers from ReconFig 2009 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2009). 679484:1-679484:2
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