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ORCIDJournal of Electronic Testing, Volume 10
Volume 10, Numbers 1-2, February 1997
- Vishwani D. Agrawal:
Editorial. 5 - Yervant Zorian:
Guest Editorial. 6 - Yervant Zorian:
Fundamentals of MCM Testing and Design-for-Testability. 7-14 - Larry Gilg:
Known Good Die. 15-25 - Madhavan Swaminathan, Bruce C. Kim, Abhijit Chatterjee:
A Survey of Test Techniques for MCM Substrates. 27-38 - Anne E. Gattiker, Wojciech Maly:
Smart Substrate MCMs. 39-53 - Ralf Schmid, Reinhold Schmitt, Matthias Brunner, Oliver Gessner, Matthias Sturm:
Electron Beam Probing - A Solution for MCM Test and Failure Analysis. 55-63 - Andrew Flint:
MCM Test Strategy Synthesis from Chip Test and Board Test Approaches. 65-76 - Najmi T. Jarwala:
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules. 77-86 - Yervant Zorian, Hakim Bederr:
An Effective Multi-Chip BIST Scheme. 87-95 - Joel A. Jorgenson, Russell J. Wagner:
Design-For-Test in a Multiple Substrate Multichip Module. 97-107 - Thomas M. Storey, Bruce McWilliam:
A Test Methodology for High Performance MCMs. 109-118 - Ken Posse:
A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules. 119-125 - Prawat Nagvajara, J. Lin, P. Nilagupta, C. Wang:
Multichip Module Diagnosis by Product-Code Signatures. 127-136 - Mick Tegethoff, Tom Chen:
Simulation Techniques for the Manufacturing Test of MCMs. 137-149 - Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn:
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die. 151-166
Volume 10, Number 3, June 1997
- Vishwani D. Agrawal:
Editorial. 171 - Michael L. Bushnell, John Giraldi:
A Functional Decomposition Method for Redundancy Identification and Test Generation. 175-195 - René David, Janusz A. Brzozowski, Helmut Jürgensen:
Testing for Bounded Faults in RAMs. 197-214 - Debaleena Das, Mark G. Karpovsky:
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations. 215-229 - C. P. Ravikumar, Nitin Agrawal, Parul Agarwal:
Hierarchical Delay Test Generation. 231-244 - Jacob Savir:
Delay Test Generation: A Hardware Perspective. 245-254 - Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. 255-269 - Michele Favalli, Marcello Dalpasso
:
Symbolic Handling of Bridging Fault Effects. 271-276 - Minesh B. Amin, Bapiraju Vinnakota:
Workload Distribution in Fault Simulation. 277-282 - Jacob Savir:
Module Level Weighted Random Patterns. 283-287
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