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ORCID37th SoCC 2024: Dresden, Germany
- Diana Göhringer, Uwe Gäbler, Tanja Harbaum, Klaus Hofmann:
37th IEEE International System-on-Chip Conference, SOCC 2024, Dresden, Germany, September 16-19, 2024. IEEE 2024, ISBN 979-8-3503-7756-9 - Kun-Chih Jimmy Chen, Hao-Hsiang Peng, Pin-Ching Shen:
Ultra-NoC: Unified Low-Transmission Routing Assisted NoC for High-flexible DNN Accelerator. 1-5 - Goeun Kim, Younghwan Chang, Yong-Un Jeong, Suhwan Kim:
A 8Gb/s PAM-4/NRZ Dual-Mode Transmitter for Panel Interfaces with Run-length Limited Maximum Transition. 1-5 - Shubham Rai, Cecilia De la Parra, Martin Rapp, Jan Micha Borrmann, Nina Bretz, Stefan Metzlaff, Taha Soliman, Christoph Schorn
:
Accelerating Automated Driving and ADAS Using HW/SW Codesign. 1-6 - Nayana Das, Saikat Basu, Goutam Paul, Vijay S. Rao:
User-Authenticated Device-Independent Quantum Secure Direct Communication Protocol. 1-6 - Dipal Halder, Yuntao Liu, Kostas Amberiadis, Ankur Srivastava, Sandip Ray:
PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures. 1-6 - Vishal Chourasia, Anirban Sengupta, Rahul Chaurasia:
HLS based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature. 143-148 - Alireza Taghavizade, Dara Rahmati, Saeid Gorgin, Jeong-A Lee:
GELU-MSDF: A Hardware Accelerator for Transformer's GELU Activation Function Using Most Significant Digit First Computation. 1-6 - Liu He, Yujin Wang, Zongle Huang, Shupei Fan, Chen Tang, Shuyuan Zhang, Luchang Lei, Huazhong Yang, Yongpan Liu, Hongyang Jia:
Exploring Approximation and Dataflow Co-Optimization for Scalable Transformer Inference Architecture on the Edge. 1-6 - Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Jiayi Chen, Lukas Witte, Andre Scheder, Tanja Harbaum, Jürgen Becker:
Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development. 1-6 - Eloïse Delolme, Viktor Fischer, Florent Bernard, Nathalie Bochard, Maxime Pelcat:
Beyond Total Locking: Demonstrating and Measuring Mutual Influence on a RO-Based True Random Number Generator on an FPGA. 1-6 - Sabbir Ahmed Khan, Zhuoran Li, Woosub Jung, Yizhou Feng, Dan Zhao, Chunsheng Xin, Gang Zhou:
DeepShield: Lightweight Privacy-Preserving Inference for Real-Time IoT Botnet Detection. 1-6 - Wuqian Tang, Chuan-Shun Huang, Yung-Chih Chen, Yi-Ting Li, Shih-Chieh Chang, Chun-Yao Wang:
Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. 1-6 - Qiuhao Zeng, Yuefei Wang, Zhongfeng Wang, Wendong Mao:
An Automated Hardware Design Framework for Various DNNs Based on ChatGPT. 1-6 - Jayoung Yang, Taewhan Kim:
Improving Timing Quality Through Net Topology Optimization in Global Routing. 1-6 - Saeid Gorgin, Mohammad K. Fallah, Mohammad Sina Karvandi, Jeong-A Lee:
Hardware Design Space Exploration in High-Level Synthesis Backend Featuring Online Arithmetic. 1-6 - Carsten Heinz, Andreas Koch:
COSSEA: Context-based SoC Security Enforcement Architecture. 1-6 - Fuyi Li, Yu Xia, Shuai Xiao, Pengcheng Yang, Xingyu Zhu, Bo Li, Jiuren Zhou, Genquan Han, Wei Mao:
Accurate Charge-Domain Bootstrapped Computing-in-Memory SRAM Design with Wide Programmable Output Voltage Range. 1-6 - Ján Mach, Lukás Kohútka, Pavel Cicák:
Lockstep Vs Microarchitecture: A Comparison. 1-6 - Lutz Schammer, Gianluca Martino, Görschwin Fey:
Usage Driven Relevance Analysis for IP Cores. 1-6 - Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe:
Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI. 1-6 - Agshare Dheeraj, Pabitra Das, Y. V. Sai Dinesh, Anagha Nimbekar, Amit Acharyya:
Multiple PUF-CPRNG based Authentication Methodology for Protecting the IP Cores. 1-6 - Mojgan Mirzaei Hotkani, Jean-François Bousquet, Bruce Martin, Ehsan Malekshahi:
Assessing the Circuit Requirements for a Real-Time Spectrum Analyzer on 65-nm CMOS Technology. 132-137 - Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura:
A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. 1-6 - Hamza Amara, Cédric Killian, Daniel Chillet, Emmanuel Casseau:
Mitigation of Hardware Trojan in NoC using Delta-Based Compression. 1-6 - Fabian Kreß, Alexey Serdyuk, Denis Kobsar, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator. 126-131 - Lizhong Wang, Haoyu Wang:
Heloc-NoC: High-Efficiency and Low-Hop On-Chip Communication in 3D Network-on-Chips. 1-6 - Yue Zhang, Basel Halak, Haoyu Wang:
ZeKi: A Zero-Knowledge Dynamic Logic Locking Implementation with Resilience to Multiple Attacks. 1-6 - Hongsup Shin:
Robust Learning-to-Rank Algorithm for Bug Discovery in Hardware Verification. 1-2 - Marwan A. Abdelfattah, Hossam O. Ahmed, Mohamed A. Abdelghany:
16-Bit SABP: Quasi-Stochastic Data Representation Unit for AI Hardware Using FPGA. 1-6 - Janik Kaden, Erik Markert, Ulrich Heinkel:
Performance Investigation for IEEE 802.15.4z-compliant SiP-assisted Ranging. 1-6 - Imran M. Saied, Anil Kumar Appukuttan Nair Syamala Amma, Srinjoy Mitra, Tughrul Arslan:
Pressure-Activated RF Sensing: A Smart Cushion Approach for Energy-Efficient IoT Health Monitoring. 1-6 - Koji Kikuta, Takashi Hisakado, Mahfuzul Islam:
Fully Integrated Switched-Capacitor DC-DC Converter With Self-Recovery Hysteresis Control. 1-6 - Robin Geens, Man Shi, Arne Symons, Chao Fang, Marian Verhelst:
Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators. 1-6 - Pratibha Verma, Tarun Gupta, Pabitra Das, Appa Rao Nali, Vidhumouli Hunsigida, Amit Acharyya:
Hardware-Aware Network Adaptation using Width and Depth Shrinking including Convolutional and Fully Connected Layer Merging. 1-6 - Aness Al-Qawlaq, Ajay Kumar M, Deepu John:
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer. 1-6 - Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Lukas Witte, Andre Scheder, Eva Waldner, Ema Shkurtaj, Tanja Harbaum, Jürgen Becker:
Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G. 1-6 - Abdur Rahman, Görschwin Fey:
Evaluating the Performance of Large Language Models for Design Validation. 1-6 - Jann Krausse, Moritz Neher, Iris Fürst-Walter, Carmen Weigelt, Tanja Harbaum, Klaus Knobloch, Jürgen Becker:
On Metric-Driven Development of Embedded Neuromorphic AI. 1-6 - Yi Chen, Jie Lou, Malte Wabnitz, Johnson Loh, Tobias Gemmeke:
EDEA: Efficient Dual-Engine Accelerator for Depthwise Separable Convolution with Direct Data Transfer. 1-6 - Mikail Yayla, Clifford Leon Dmello, Georg Ellguth, Uwe Steeb, Tim Leuchter, Marcus Pietzsch, Holger Eisenreich:
EdgeVision SoC: PPA-Impact of RTL-level Modifications. 1-2 - A. Alper Goksoy, Jiahao Lin, Ümit Y. Ogras:
Energy-Efficient and Communication-Aware Architectures for Accelerating Deep Learning Workloads. 1-6 - Ratnala Vinay, Kartik Laad, Parveen Nisha, Afreen Aijaz, Bhavya Pisipati, Pradip Sasmal, Toshihisa Haraki, Chirag Juyal, Yuki Tanimoto, Amit Acharyya:
Digital Twin Based Run Time Power Management for Edge SoC using Performance Aware Reinforcement Learning. 1-6 - Fan Yang, Zehao Wang, Haoyu Zhang, Zhenhua Zhu, Xinhao Yang, Guohao Dai, Yu Wang:
Efficient Deployment of Large Language Model across Cloud-Device Systems. 1-6 - Jiun-Kai Yang, Yao-Hua Chen, Chih-Tsun Huang:
BEACON: Block-wise Efficient Architecture Co-optimization for DNN-HW-Mapping with Zero-cost Evaluation and Progressive Distillation. 1-6 - Shuang Liu, Martin Radetzki:
Integer Linear Programming Based Design of Deadlock-Free Routing for Chiplet-Based Systems. 1-6 - Anubhab Baksi, Sumanta Chakraborty, Anupam Chattopadhyay, Matthew Chun, SK Hafizul Islam, Kyungbae Jang, Hyunji Kim, Yujin Oh, Soham Roy, Hwajeong Seo, Siyi Wang:
Quantum Implementation of Linear and Non-Linear Layers. 1-6 - Shubham Ranjan, Sheida Gohardehi, Manoj Sachdev:
A Low-voltage-Driven Single-ended Column based SRAM for Low-Power Micro-display. 1-6 - Mahati Basavaraju, Omkar Girish Ratnaparkhi, Vinay Rayapati, Madhav Rao:
Clustering-Based-Approach for Hardware Implementation of Activation Functions. 1-6 - Venkatesh G. Kadlimatti, Aniruddha Periyapatna Nagendra, M. Ankitha, Harikrishna Parthasarathy:
Continuous Conduction Mode in Digital Control Loop of DC-DC. 138-142 - Sen Wang, Yijun Cui, Shichao Yu, Chongyan Gu, Chenghua Wang, Weiqiang Liu:
GATrojan: An Efficient Gate-level Hardware Trojan Detection Approach Using Graph Attention Networks. 1-6 - Siva Satyendra Sahoo, Dawit Burusie Abdi, Julien Ryckaert, James Myers, Dwaipayan Biswas:
On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies. 1-6 - Vijayalakshmi Saravanan, Sai Karthik Navuluru, Khaled Z. Ibrahim:
A Systematic Study of Parallelization Strategies for Optimizing Scientific Computing Performance Bounds. 1-6 - Marc Neu, Christian Maximilian Karle, Patrick Schmidt, Julian Höfer, Tanja Harbaum, Jürgen Becker:
A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation. 1-6 - Ehsan Atoofian:
Hardened-TC: A Low-cost Reliability Solution for CNNs Run by Modern GPUs. 1-6 - Patrick Schmidt, Johannes Pfau, Tim Hotfilter, Matthias Stammler, Tanja Harbaum, Jürgen Becker:
RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration. 1-6 - Prashanth H. C., Madhav Rao:
Evaluating Deep Neural Network Performance on Edge Accelerators: A Roofline Model Adopted Benchmarking Approach. 1-6 - Anagha Nimbekar, Prabodh Katti, Chen Li, Bashir M. Al-Hashimi, Amit Acharyya, Bipin Rajendran:
Hardware-Software Co-optimised Fast and Accurate Deep Reconfigurable Spiking Inference Accelerator Architecture Design Methodology. 1-6 - Huapei Wang, Cheng Cai, Xuxin Chen, Fang Huo:
Analog Circuits Fault Diagnosis Based on Machine Learning. 1-6 - Aman Kumar, Deepak Narayan Gadde:
Generative AI Augmented Induction-based Formal Verification. 1-2 - Abhoy Kole, Kamalika Datta, Rolf Drechsler:
Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability. 1-5 - Infall Syafalni, Mohamad Imam Firdaus, Nana Sutisna, Trio Adiono, Tutun Juhana, Rahmat Mulyawan:
DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest Path and Coverage Area. 1-6 - Vahid Geraeinejad, Kun-Chih Jimmy Chen, Zhonghai Lu, Masoumeh Ebrahimi:
MCLB: Dynamic Load Balancing and Implications on GPU Memory Controllers. 1-6 - Yu-Guang Chen, Yi-Chen Ho, Jing-Yang Jou:
Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability. 1-6 - Ahmed Kamaleldin, Matthias Nickel, Sisi Wu, Diana Göhringer:
Seamless Cache Extension for FPGA-based Multi-Core RISC-V SoC. 1-6 - Yeongyeong Shin, Taewhan Kim:
Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design. 1-6
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last updated on 2026-03-21 22:56 CET by the dblp team
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