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ORCID5th SLIP 2003: Monterey, CA, USA
- Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha:
The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings. ACM 2003, ISBN 1-58113-627-7 - Victor N. Kravets
, Prabhakar Kudva:
Understanding metrics in logic synthesis for routability enhancement. 3-5 - Ketan N. Patel, Igor L. Markov:
Error-correction and crosstalk avoidance in DSM busses. 9-14 - Jason Helge Anderson, Farid N. Najm:
Switching activity analysis and pre-layout activity prediction for FPGAs. 15-21 - Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. 23-30 - Joachim Pistorius, Mike Hutton:
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. 31-38 - Martijn T. Bennebroek:
Validation of wire length distribution models on commercial designs. 41 - Joni Dambre, Dirk Stroobandt, Jan Van Campenhout:
Fast estimation of the partitioning rent characteristic using a recursive partitioning model. 45-52 - Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis:
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. 53-59 - Andrew B. Kahng, Xu Xu:
Accurate pseudo-constructive wirelength and congestion estimation. 61-68 - Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang:
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. 71-76 - Shankar Balachandran, Dinesh Bhatia:
A-priori wirelength and interconnect estimation based on circuit characteristics. 77-84 - Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright:
Prediction of interconnect pattern density distribution: derivation, validation, and applications. 85-91 - Eli Chiprout:
Early electrical wire projections and implications. 95 - Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska:
Wire length prediction in constraint driven placement. 99-105 - Pranav Anbalagan, Jeffrey A. Davis:
Maximum multiplicity distributions (MMD). 107-113 - Jian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen:
System level interconnect design for network-on-chip using interconnect IPs. 117-124 - Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex:
Global interconnect trade-off for technology over memory modules to application level: case study. 125-132 - Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham:
A hierarchical three-way interconnect architecture for hexagonal processors. 133-139
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