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ORCIDReConFig 2017: Cancun, Mexico
- International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017. IEEE 2017, ISBN 978-1-5386-3797-5
- Éricles Sousa, Alexandru Tanase, Frank Hannig
, Jürgen Teich:
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. 1-8 - Ahmad Salman, Ahmed Ferozpuri, Ekawat Homsirikamol, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj:
A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures. 1-8 - Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter:
A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. 1-6 - Shijie Zhou, Rajgopal Kannan, Viktor K. Prasanna:
Accelerating low rank matrix completion on FPGA. 1-7 - Claudio Rubattu, Francesca Palumbo, Maxime Pelcat:
Adaptive software-augmented hardware reconfiguration with dataflow design automation. 1-4 - Sreeja Chowdhury, Xiaolin Xu, Mark Tehranipoor, Domenic Forte:
Aging resilient RO PUF with increased reliability in FPGA. 1-7 - Paul Rogers, Rajesh Kavasseri, Scott C. Smith:
An FPGA-in-the-loop approach for HDL motor controller verification. 1-6 - Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck:
An FPGA-based prototyping framework for Networks-on-Chip. 1-7 - Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara:
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. 1-6 - Jens Rettkowski, Diana Göhringer:
Application-specific processing using high-level synthesis for networks-on-chip. 1-7 - Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic:
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp. 1-6 - Rasha Karakchi, Lothrop O. Richards, Jason D. Bakos:
A Dynamically Reconfigurable Automata Processor Overlay. 1-8 - David C. Keezer, Jingchi Yang:
Biologically inspired hierarchical structure for self-repairing FPGAs. 1-8 - Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow:
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. 1-6 - Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti:
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. 1-6 - Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck:
Continuous live-tracing as debugging approach on FPGAs. 1-8 - Tripti Jain, Klaus Schneider, Ankesh Jain:
Deriving concentrators from binary sorters using half cleaners. 1-6 - Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck:
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. 1-8 - Fredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. 1-6 - Metzli Ramirez-Martinez, Francisco Sanchez-Fernandez, Philippe Brunet, Sidi Mohammed Senouci, El-Bay Bourennane:
Dynamic management of a partial reconfigurable hardware architecture for pedestrian detection in regions of interest. 1-7 - Andreas Engel, Andreas Koch:
Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes. 1-8 - Joao Lopes, Diogo Sousa, João Canas Ferreira:
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. 1-7 - Panasayya Yalla, Jens-Peter Kaps:
Evaluation of the CAESAR hardware API for lightweight implementations. 1-6 - Lucas B. da Silva, Danilo Damião Almeida, José Augusto Miranda Nacif, Ismael Sanchez-Osorio, Carlos A. Hernandez-Martinez, Ricardo Ferreira:
Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform. 1-7 - Hanqing Zeng, Chi Zhang, Viktor K. Prasanna:
Fast generation of high throughput customized deep learning accelerators on FPGAs. 1-8 - César Torres-Huitzil, Bernard Girau:
Fault tolerance in neural networks: Neural design and hardware implementation. 1-6 - Young H. Cho, Siddharth S. Bhargav:
Fine-grained on-line power monitoring for soft microprocessor based system-on-chip. 1-6 - Diogo Parrinha, Ricardo Chaves:
Flexible and low-cost HSM based on non-volatile FPGAs. 1-8 - Michele Paolino, Sebastien Pinneterre, Daniel Raho:
FPGA virtualization with accelerators overcommitment for network function virtualization. 1-6 - Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano:
Glitch-aware variable pipeline optimization for CGRAs. 1-6 - Ian J. Barge, Cristinel Ababei:
H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip. 1-6 - Sizhuo Zhang, Hari Angepat, Derek Chiou:
HGum: Messaging framework for hardware accelerators. 1-8 - Ievgen Kabin, Zoya Dyka, Dan Kreiser, Peter Langendörfer:
Horizontal address-bit DPA against montgomery kP implementation. 1-8 - Siyuan Xu, Jianqi Chen, Benjamin Carrión Schäfer:
HW/SW co-design experimental framework using configurable SoCs. 1-6 - Pongstorn Maidee, Alireza Kaviani, Kevin Zeng:
LinkBlaze: Efficient global data movement for FPGAs. 1-8 - Girish Deshpande, Dinesh K. Bhatia:
Microchannels for thermal management in FPGAs. 1-5 - Farnoud Farahmand, Ahmed Ferozpuri, William Diehl, Kris Gaj:
Minerva: Automated hardware optimization tool. 1-8 - Bernard Girau, César Torres-Huitzil:
Optimal weight storage improves fault tolerance of SOMs. 1-6 - Muhammad Usman Tariq, Umer I. Cheema, Fahad Saeed:
Power-efficient and highly scalable parallel graph sampling using FPGAs. 1-6 - Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton:
Rapid circuit-specific inlining tuning for FPGA high-level synthesis. 1-6 - John Watson:
Keynote 1 - Education is not learning facts, but training the mind to think. 1 - Christian Plessi:
Keynote 2 - FPGA-accelerated high-performance computing - Close to breakthrough or pipedream? 1 - Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich:
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. 1-3 - William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
Side-channel resistant soft core processor for lightweight block ciphers. 1-8 - Tuncay Soylu, Oguzhan Erdem, Aydin Carus, Edip S. Güner:
Simple CART based real-time traffic classification engine on FPGAs. 1-8 - Salvador Ibarra-Delgado, Remberto Sandoval-Arechiga, María Brox, Manuel A. Ortiz:
Software defined network controller: A neat solution administration for reconfigurable multi-core NoC. 1-4 - Qianqiao Chen, Vaibhawa Mishra, José L. Núñez-Yáñez, Georgios Zervas:
Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. 1-6 - Lukas Sommer, Julian Oppermann, Jaco A. Hofmann, Andreas Koch:
Synthesis of interleaved multithreaded accelerators from OpenMP loops. 1-7 - Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku:
Thorough analysis of PCIe Gen3 communication. 1-6 - Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira, João Canas Ferreira:
Towards a type 0 hypervisor for dynamic reconfigurable systems. 1-7 - Anthony Brandon, Michael Trimarchi:
Trusted display and input using screen overlays. 1-6 - Muhammad K. A. Hamdan, Diane T. Rover:
VHDL generator for a high performance convolutional neural network FPGA-based accelerator. 1-6
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