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ORCIDFPT 2008: Taipei, Taiwan
- Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha:
2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008. IEEE 2008, ISBN 978-1-4244-2796-3
Keynotes
- Patrick Lysaght:
Re-visiting the challenges of programmable concurrent architectures. - Paul Leventis:
FPGA timing, power, signal integrity and other challenges at 65 and 45 nm. - Brent Nelson:
FPGA design productivity a discussion of the state of the art and a research agenda.
Tools I
- Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos:
Co-optimisation of datapath and memory in outer loop pipelining. 1-8 - Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined signaling for on-FPGA communication. 9-16 - Wei Zhang, Vaughn Betz, Jonathan Rose:
Portable and scalable FPGA-based acceleration of a direct linear system solver. 17-24 - Cindy Mark, Ava Shui, Steven J. E. Wilton:
A system-level stochastic circuit generator for FPGA architecture evaluation. 25-32
Arithmetic
- Florent de Dinechin, Bogdan Pasca
, Octavian Cret, Radu Tudoran:
An FPGA-specific approach to floating-point accumulation and sum-of-products. 33-40 - Haohuan Fu, Oskar Mencer, Wayne Luk:
Optimizing residue arithmetic on FPGAs. 41-48 - Mihai Sima, Michael McGuire, Scott Miller:
Reconfigurable array for transcendental functions calculation. 49-56 - Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton:
Optimizing coarse-grained units in floating point hybrid FPGA. 57-64
Applications I
- Tomás Martínek, Matej Lexa:
Hardware acceleration of approximate palindromes searching. 65-72 - Johnny Tsung Lin Ho, Guy G. F. Lemieux:
PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters. 73-80 - Xiang Tian, Khaled Benkrid:
Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputer. 81-88 - David B. Thomas, Wayne Luk:
Estimation of sample mean and variance for Monte-Carlo simulations. 89-96 - Oliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub:
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain. 97-104
Tools II
- Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
A transition probability based delay measurement method for arbitrary circuits on FPGAs. 105-112 - Daniel Nunes, Manuel Saldaña, Paul Chow:
A profiler for a heterogeneous multi-core multi-FPGA system. 113-120 - Joon Edward Sim, Tulika Mitra, Weng-Fai Wong:
Defining neighborhood relations for fast spatial-temporal partitioning of applications on reconfigurable architectures. 121-128 - Iakovos Mavroidis, Ioannis Papaefstathiou:
Accelerating hardware simulation: Testbench code emulation. 129-136
Architectures I
- Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano:
Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors. 137-144 - Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A scalable reconfiguration mechanism for fast dynamic reconfiguration. 145-152 - Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan, Kris Gaj:
Memory security management for reconfigurable embedded systems. 153-160 - Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik:
ACS: An Addressless Configuration Support for efficient partial reconfigurations. 161-168
Applications II
- Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette, Jim Tørresen:
An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration. 169-176 - Kofi Appiah, Andrew Hunter, Patrick Dickinson, Jonathan D. Owens:
A run-length based connected component algorithm for FPGA implementation. 177-184 - Ni Ma, Donald G. Bailey, Christopher T. Johnston:
Optimised single pass connected components analysis. 185-192 - Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. 193-200 - Yingxi Lu, Máire O'Neill, John V. McCanny:
FPGA implementation and analysis of random delay insertion countermeasure against DPA. 201-208
Architectures II
- Moritz Schmid, Daniel Ziener, Jürgen Teich:
Netlist-level IP protection by watermarking for LUT-based FPGAs. 209-216 - N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Modelling and compensating for clock skew variability in FPGAs. 217-224 - Philip Garcia, Katherine Compton:
Kernel sharing on reconfigurable multiprocessor systems. 225-232 - Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel:
Evaluating the impact of customized instruction set on coarse grained reconfigurable arrays. 233-240 - Wenyin Fu, Katherine Compton:
Balanced allocation of compute time in hardware-accelerated systems. 241-248
Poster Session
- Huynh Phung Huynh, Tulika Mitra:
Processor customization for wearable bio-monitoring platforms. 249-252 - Dang Ba Khac Trieu, Tsutomu Maruyama:
An implementation of a watershed algorithm based on connected components on FPGA. 253-256 - Edward Chen, Dorian Sabaz, William A. Gruver, Lesley Shannon:
A new flexible PR domain model to replace the fixed multi-PR region model for DPR systems. 257-260 - Rosemary M. Francis, Simon W. Moore:
Exploring hard and soft networks-on-chip for FPGAs. 261-264 - Yoshifumi Tanida, Tsutomu Maruyama:
An approach for downscaling images for real-time pattern detection. 265-268 - Ahmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan:
Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier. 269-272 - Kazuya Tanigawa, Tetsuo Hironaka:
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. 273-276 - Markus Rullmann, Renate Merker:
Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. 277-280 - Harold Ishebabi, Philipp Mahr, Christophe Bobda:
Makespan minimization in automatic synthesis of multiprocessor systems from parallel programs. 281-284 - Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez:
A new coarse-grained FPGA architecture exploration environment. 285-288 - Takayuki Mabuchi, Minoru Watanabe:
An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays. 289-292 - Mao Nakajima, Minoru Watanabe:
An 11, 424-gate dynamic optically reconfigurable gate array VLSI. 293-296 - Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama:
A systolic regular expression pattern matching engine and its application to network intrusion detection. 297-300 - Kentaro Sano, Takeshi Nishikawa, Takayuki Aoki, Satoru Yamamoto:
Evaluating power and energy consumption of FPGA-based custom computing machines for scientific floating-point computation. 301-304 - Samuel J. Stone, Roy Porter, Yong C. Kim, Jason V. Paul:
A dynamically reconfigurable Field Programmable Gate Array hardware foundation for security applications. 305-308 - Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng:
Quad-level bit-stream signal processing on FPGAs. 309-312 - Zong Wang, Tughrul Arslan:
A low power reconfigurable heterogeneous architecture for a mobile SDR system. 313-316 - Roel Meeuws, Kamana Sigdel, Yana Yankova, Koen Bertels:
High level quantitative interconnect estimation for Early Design Space Exploration. 317-320 - Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong:
Unrolling-based loop mapping and scheduling. 321-324 - Audip Pandit, Lakshmi Easwaran, Ali Akoglu:
Concurrent timing based and routability driven depopulation technique for FPGA packing. 325-328 - Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano:
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. 329-332 - Yosi Ben-Asher, Esti Stein:
Extending Booth algorithm to multiplications of three numbers on FPGAs. 333-336 - Markos Papadonikolakis, Christos-Savvas Bouganis:
A scalable FPGA architecture for non-linear SVM training. 337-340 - Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. 341-344 - James W. Crouch, Hiren J. Patel, Yong C. Kim, Jeffrey Todd McDonald, Tony C. Kim:
Creating digital fingerprints on commercial field programmable gate arrays. 345-348 - Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner:
An area-efficient FPGA realisation of a codebook-based image compression method. 349-352 - Antonio Roldao Lopes, George A. Constantinides, Eric C. Kerrigan:
A floating-point solver for band structured linear equations. 353-356 - Samuel Antao, Ricardo Chaves, Leonel Sousa:
Efficient FPGA elliptic curve cryptographic processor over GF(2m). 357-360 - Wayne Chen, Lesley Shannon:
An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs. 361-364 - Naoto Miyamoto, Tadahiro Ohmi:
Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulation. 365-368 - Stephan Wong, Thijs van As, Geoffrey Brown:
p-VEX: A reconfigurable and extensible softcore VLIW processor. 369-372 - Ali Irturk, Bridget Benson, Arash Arfaee, Ryan Kastner:
Automatic generation of decomposition based matrix inversion architectures. 373-376 - Shinichi Kato, Minoru Watanabe:
Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI. 377-380 - Chung-Chi Lin, Ming-Hwa Sheu, Huann-Keng Chiang, Wen-Kai Tsai, Zeng-Chuan Wu:
Real-time FPGA architecture of extended linear convolution for digital image scaling. 381-384
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