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ORCIDBi Wu 0002
Person information
- affiliation: Nanjing University of Aeronautics and Astronautics, Nanjing, China
Other persons with the same name
- Bi Wu — disambiguation page
- Bi Wu 0001
![[0000-0002-0676-8227]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-0676-8227")
— Southwest Jiaotong University, Chengdu, China - Bi Wu 0003 — Anderson School of Management, University of California, Los Angeles, CA, USA
- Bi Wu 0004 — Beijing BlueSky Innovation Center for Frontier Science, Beijing, China
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2020 – today
- 2025
[j24]Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu:
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(1): 119-129 (2025)- [j23]Bi Wu, Yang Hu, Shuo Ran, Xun Zhang, Ke Chen, Chenggang Yan, Weiqiang Liu:
SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 72(12): 7707-7718 (2025) - [c23]Ziying Cui, Ke Chen, Bi Wu, Yu Gong, Chenggang Yan, Weiqiang Liu:
PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate Computing. DAC 2025: 1-7 - [c22]Xuehui Liu, Xueyan Wang, Tianyang Yu, Chen Cheng, Shuo Ran, Bi Wu, Xiaotao Jia, Weiqiang Liu, Gang Qu, Weisheng Zhao:
MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach. DAC 2025: 1-7 - [c21]Kai Tian, Bi Wu, Ke Chen, Weiqiang Liu:
High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme. ISCAS 2025: 1-5 - [c20]Tianyang Yu, Bi Wu, Weiqiang Liu:
Learning-Based Realtime Synthetic Aperture Radar Imaging for Embedded System on Satellite. ISCAS 2025: 1-5 - 2024
- [j22]Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu:
Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications. IEEE Trans. Computers 73(2): 574-585 (2024) - [j21]Bi Wu, Tianyang Yu, Ke Chen, Weiqiang Liu:
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1285-1298 (2024) - [j20]Haonan Zhu, Bi Wu, Tianyang Yu, Ke Chen, Chenggang Yan, Weiqiang Liu:
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3165-3178 (2024) - [j19]Tianyang Yu, Bi Wu, Ke Chen, Gong Zhang, Weiqiang Liu:
AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory. IEEE Trans. Circuits Syst. II Express Briefs 71(12): 4984-4988 (2024) - [j18]Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1004-1017 (2024) - [c19]Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Yu Gong, Weiqiang Liu:
A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration. ARITH 2024: 116-123 - [c18]Xidi Ma, Weichen Zhang, Xueyan Wang, Tianyang Yu, Bi Wu, Gang Qu, Weisheng Zhao:
A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration. DAC 2024: 257:1-257:6 - [c17]Bin Gong, Ke Chen, Pengfei Huang, Bi Wu, Weiqiang Liu:
Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models. ISCAS 2024: 1-5 - 2023
- [j17]Chenggang Yan, Yuxuan Cui, Ke Chen, Bi Wu, Weiqiang Liu:
Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 189-200 (2023) - [j16]Bi Wu, Haonan Zhu, Ke Chen, Chenggang Yan, Weiqiang Liu:
MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2412-2424 (2023) - [j15]Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao:
A Survey of MRAM-Centric Computing: From Near Memory to In Memory. IEEE Trans. Emerg. Top. Comput. 11(2): 318-330 (2023) - [j14]Bi Wu, Haonan Zhu, Dayane Reis, Zhaohao Wang, Ying Wang, Ke Chen, Weiqiang Liu, Fabrizio Lombardi, Xiaobo Sharon Hu:
An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs. IEEE Trans. Emerg. Top. Comput. 11(2): 331-342 (2023) - [c16]Haonan Wang, Ke Chen, Chenggang Yan, Bi Wu, Weiqiang Liu:
Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications. MWSCAS 2023: 977-981 - [c15]Wenzhuo Xie, Chenggang Yan, Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu:
A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing. MWSCAS 2023: 982-986 - [c14]Shuo Ran, Bi Wu, Ke Chen, Weiqiang Liu:
VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning. NANOARCH 2023: 33:1-33:6 - 2022
- [j13]Shanshan Liu, Bi Wu, Ke Chen, Weiqiang Liu, Máire O'Neill, Fabrizio Lombardi:
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2653-2654 (2022) - [j12]Bi Wu, Zhengkuan Wang, Ke Chen, Chenggang Yan, Weiqiang Liu:
GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3655-3665 (2022) - [c13]Jipeng Ge, Chenggang Yan, Xuan Zhao, Ke Chen, Bi Wu, Weiqiang Liu:
An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications. APCCAS 2022: 1-5 - [c12]Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy. ACM Great Lakes Symposium on VLSI 2022: 243-248 - [c11]Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu:
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits. ACM Great Lakes Symposium on VLSI 2022: 315-318 - [c10]Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration. ICCD 2022: 762-769 - [c9]Yuan Song, Bi Wu, Tian Yuan, Weiqiang Liu:
A High-Speed CNN Hardware Accelerator with Regular Pruning. ISQED 2022: 1-5 - [c8]Kai Liu, Bi Wu, Haonan Zhu, Weiqiang Liu:
High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features. NANOARCH 2022: 2:1-2:6 - [c7]Didi Zhang, Bi Wu, Haonan Zhu, Weiqiang Liu:
Capacity-oriented High-performance NV-TCAM Leveraging Hybrid MRAM Scheme. NANOARCH 2022: 3:1-3:6 - [c6]Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi:
HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation. NANOARCH 2022: 15:1-15:6 - [c5]You Wang, Bi Wu, Hao Cai, Weiqiang Liu:
Low-cost stochastic number generator based on MRAM for stochastic computing. NANOARCH 2022: 20:1-20:5 - 2021
- [j11]Guocai Nan, Zhengkuan Wang, Chenghua Wang, Bi Wu, Zhican Wang, Weiqiang Liu, Fabrizio Lombardi:
An Energy Efficient Accelerator for Bidirectional Recurrent Neural Networks (BiRNNs) Using Hybrid-Iterative Compression With Error Sensitivity. IEEE Trans. Circuits Syst. I Regul. Pap. 68(9): 3707-3718 (2021) - [j10]Bi Wu, Zhaohao Wang, Yuxuan Li, Ying Wang, Dijun Liu, Weisheng Zhao, Xiaobo Sharon Hu:
A NAND-SPIN-Based Magnetic ADC. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 617-621 (2021) - 2020
- [j9]Wang Kang, Bi Wu, Xing Chen, Daoqian Zhu, Zhaohao Wang, Xichao Zhang, Yan Zhou, Youguang Zhang, Weisheng Zhao:
A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion. ACM J. Emerg. Technol. Comput. Syst. 16(1): 2:1-2:17 (2020) - [j8]Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang:
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. ACM J. Emerg. Technol. Comput. Syst. 16(3): 29:1-29:18 (2020) - [j7]Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao:
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 803-815 (2020) - [j6]Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang:
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 108-120 (2020) - [j5]Bi Wu, Chao Wang, Zhaohao Wang, Ying Wang, Deming Zhang, Dijun Liu, Youguang Zhang, Xiaobo Sharon Hu:
Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories. IEEE Trans. Circuits Syst. 67-I(12): 4660-4669 (2020)
2010 – 2019
- 2019
- [j4]Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 215-225 (2019) - [j3]Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang, Dijun Liu, Weisheng Zhao:
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1851-1860 (2019) - 2018
- [j2]Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung-Hyuk Kang, Yuan Xie:
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 484-495 (2018) - [c4]Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao:
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. ISVLSI 2018: 333-338 - 2017
- [c3]Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao:
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. ICCAD 2017: 474-481 - 2016
- [j1]Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao:
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. 65(4): 1755-1768 (2016) - [c2]Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao:
PDS: pseudo-differential sensing scheme for STT-MRAM. DAC 2016: 120:1-120:6 - 2015
- [c1]Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao:
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. NANOARCH 2015: 7-12
Coauthor Index
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