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ORCIDMengdi Wang 0004
Person information
- affiliation (PhD 2023): Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China
Other persons with the same name
- Mengdi Wang — disambiguation page
- Mengdi Wang 0001
![[0000-0002-2101-9507]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-2101-9507")
— Princeton University, Center for Statistics and Machine Learning, Department of Electrical and Computer Engineering, NJ, USA (and 1 more) - Mengdi Wang 0002 — Technical University of Munich, Germany
- Mengdi Wang 0003 — Georgia Institute of Technology, School of Interactive Computing, Atlanta, GA, USA (and 1 more)
- Mengdi Wang 0005 — Chongqing University of Posts and Telecommunications, College of Computer Science and Technology, China (and 1 more)
- Mengdi Wang 0006 — Tsinghua University, State Key Laboratory of Intelligent Technology and Systems, TNList, Beijing, China
- Mengdi Wang 0007 — Shandong University, School of Control Science and Engineering, China
- Mengdi Wang 0008 — East China Normal University, Software Engineering Institute, Shanghai, China
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2020 – today
- 2025
[j3]Lian Liu, Jinxin Yu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang:
DNA: A General Dynamic Neural Network Accelerator. IEEE Trans. Computers 74(9): 3210-3222 (2025)- [j2]Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang:
A data-centric chip design agent framework for Verilog code generation. ACM Trans. Design Autom. Electr. Syst. 30(6): 93:1-93:27 (2025) - [j1]Cangyuan Li, Chujie Chen, Yudong Pan, Wenjun Xu, Yiqi Liu, Kaiyan Chang, Yujie Wang, Mengdi Wang, Huawei Li, Yinhe Han, Ying Wang:
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models. ACM Trans. Design Autom. Electr. Syst. 30(6): 97:1-97:21 (2025) - [c14]Kun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han, Ying Wang:
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. ASP-DAC 2025: 808-813 - [c13]Shixin Zhao, Yuming Li, Bing Li, Yintao He, Mengdi Wang, Yinhe Han, Ying Wang:
Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators. ASPLOS (2) 2025: 63-78 - [c12]Lian Liu, Long Cheng, Haimeng Ren, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang:
COMET: Towards Practical W4A4KV4 LLMs Serving. ASPLOS (2) 2025: 131-146 - [c11]Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang:
Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. HPCA 2025: 1751-1765 - [c10]Yu Chen, Yilun Zhao, Bing Li, He Li, Mengdi Wang, Yinhe Han, Ying Wang:
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits. ICCAD 2025: 1-9 - [c9]Lian Liu, Xiandong Zhao, Guanchen Li, Dong Li, Mengdi Wang, Yinhe Han, Xiaowei Li, Ying Wang:
BaWA: Automatic Optimizing Pruning Metric for Large Language Models with Balanced Weight and Activation. ICML 2025 - [i9]Kun Wang, Kaiyan Chang, Mengdi Wang, Xinqi Zou, Haobo Xu, Yinhe Han, Ying Wang:
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. CoRR abs/2501.02446 (2025) - [i8]Lian Liu, Shixin Zhao, Bing Li, Haimeng Ren, Zhaohui Xu, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang:
Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. CoRR abs/2502.16963 (2025) - [i7]Shixin Zhao, Yuming Li, Bing Li, Yintao He, Mengdi Wang, Yinhe Han, Ying Wang:
Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators. CoRR abs/2502.17006 (2025) - [i6]Zhirong Chen, Kaiyan Chang, Zhuolin Li, Xinyang He, Chujie Chen, Cangyuan Li, Mengdi Wang, Haobo Xu, Yinhe Han, Ying Wang:
ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning. CoRR abs/2507.04736 (2025) - [i5]Yu Chen, Yilun Zhao, Bing Li, He Li, Mengdi Wang, Yinhe Han, Ying Wang:
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits. CoRR abs/2509.15742 (2025) - 2024
- [c8]Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li:
Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. ASPDAC 2024: 58-64 - [c7]Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. DAC 2024: 60:1-60:6 - [c6]Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang:
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. ICCAD 2024: 117:1-117:9 - [i4]Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR abs/2403.11202 (2024) - [i3]Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang:
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. CoRR abs/2407.08473 (2024) - [i2]Lian Liu, Haimeng Ren, Long Cheng, Zhaohui Xu, Yudong Pan, Mengdi Wang, Xiaowei Li, Yinhe Han, Ying Wang:
COMET: Towards Partical W4A4KV4 LLMs Serving. CoRR abs/2410.12168 (2024) - 2023
- [c5]Huiqing Xu, Kuang Mao, Quihong Pan, Zhaorong Tang, Mengdi Wang, Ying Wang:
Deep Learning Compiler Optimization on Multi-Chiplet Architecture. AICAS 2023: 1-5 - [c4]Chengsi Gao, Ying Wang, Cheng Liu, Mengdi Wang, Weiwei Chen, Yinhe Han, Lei Zhang:
Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. DATE 2023: 1-6 - [i1]Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
ChipGPT: How far are we from natural language hardware design. CoRR abs/2305.14019 (2023) - 2021
- [c3]Mengdi Wang, Ying Wang, Cheng Liu, Lei Zhang:
Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. DAC 2021: 49-54 - [c2]Mengdi Wang, Bing Li, Ying Wang, Cheng Liu, Xiaohan Ma, Xiandong Zhao, Lei Zhang:
MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design. ACM Great Lakes Symposium on VLSI 2021: 1-8 - 2020
- [c1]Ying Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li:
A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. ICCAD 2020: 46:1-46:7
Coauthor Index
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