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Siddharth Joshi 0005

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affiliation: Indian Institute of Technology, Department of Electrical Engineering, Bombay, Mumbai, India

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2010 – 2019

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2011
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  dblp key:
  - conf/peccs/AttardeJDPP11
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Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik, Sachin B. Patkar:
Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA. PECCS 2011: 476-484
2010
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Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. Int. J. Parallel Program. 38(3-4): 322-338 (2010)

2000 – 2009

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2009
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Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. VLSI Design 2009: 341-346

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