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ORCID58th DAC 2021: San Francisco, CA, USA
- 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021. IEEE 2021, ISBN 978-1-6654-3274-0
- Jing Cao
, Zirui Lian, Weihong Liu, Zongwei Zhu, Cheng Ji:
HADFL: Heterogeneity-aware Decentralized Federated Learning Framework. 1-6 - Harry Foster:
General Chair's Message. 1 - Alejandro Hernández-Cano, Cheng Zhuo, Xunzhao Yin, Mohsen Imani:
RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning System. 7-12 - Yonggan Fu, Yongan Zhang, Chaojian Li, Zhongzhi Yu, Yingyan Lin:
A3C-S: Automated Agent Accelerator Co-Search towards Efficient Deep Reinforcement Learning. 13-18 - Omid Aramoon, Pin-Yu Chen, Gang Qu:
AID: Attesting the Integrity of Deep Neural Networks. 19-24 - Minxuan Zhou, Yunhui Guo, Weihong Xu, Bin Li, Kevin W. Eliceiri, Tajana Rosing:
MAT: Processing In-Memory Acceleration for Long-Sequence Attention. 25-30 - Litong You, Tianxiao Gu, Shengan Zheng, Jianmei Guo, Sanhong Li, Yuting Chen, Linpeng Huang:
JPDHeap: A JVM Heap Design for PM-DRAM Memories. 31-36 - Jianqi Zhao, Yao Wen, Yuchen Luo, Zhou Jin, Weifeng Liu, Zhenya Zhou:
SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUs. 37-42 - Fan Zhang, Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang, Deliang Fan:
PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification. 43-48 - Mengdi Wang, Ying Wang, Cheng Liu, Lei Zhang:
Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. 49-54 - Yuan Zhou, Hanyu Wang, Jieming Yin, Zhiru Zhang:
Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC. 55-60 - Anup Gangwar, Ravishankar Sreedharan, Ambica Prasad, Nitin Kumar Agarwal, Sri Harsha Gade:
Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip. 61-66 - Ebadollah Taheri, Ryan Gary Kim, Mahdi Nikdast:
AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs. 67-72 - Yichen Jiang, Huifeng Zhu, Dean Sullivan, Xiaolong Guo, Xuan Zhang, Yier Jin:
Quantifying Rowhammer Vulnerability for DRAM Security. 73-78 - Md Rafid Muttaki, Roshanak Mohammadivojdan, Mark Tehranipoor, Farimah Farahmandi:
HLock: Locking IPs at the High-Level Language. 79-84 - Durba Chatterjee, Urbi Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra:
SACReD: An Attack Framework on SAC Resistant Delay-PUFs leveraging Bias and Reliability Factors. 85-90 - Nimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri:
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. 91-96 - Yuhong Liang, Ming-Chang Yang:
Move-On-Modify: An Efficient yet Crash-Consistent Update Strategy for Interlaced Magnetic Recording. 97-102 - Yungang Pan, Zhiping Jia, Zhaoyan Shen, Bingzhe Li, Wanli Chang, Zili Shao:
Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMR. 103-108 - Fei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy:
OpenMem: Hardware/Software Cooperative Management for Mobile Memory System. 109-114 - Changlong Li, Liang Shi, Chun Jason Xue:
MobileSwap: Cross-Device Memory Swapping for Mobile Devices. 115-120 - Di Gao, Qingrong Huang, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo:
Bayesian Inference Based Robust Computing on Memristor Crossbar. 121-126 - Naimul Hassan, Alexander J. Edwards, Dhritiman Bhattacharya, Mustafa M. Shihab, Varun Venkat, Peng Zhou, Xuan Hu, Shamik Kundu, Abraham Peedikayil Kuruvila, Kanad Basu, Jayasimha Atulasimha, Yiorgos Makris, Joseph S. Friedman:
Secure Logic Locking with Strain-Protected Nanomagnet Logic. 127-132 - Ghasem Pasandi, Massoud Pedram:
qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology. 133-138 - Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. 139-144 - Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
MyML: User-Driven Machine Learning. 145-150 - Shuo Huai, Lei Zhang, Di Liu, Weichen Liu, Ravi Subramaniam:
ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems. 151-156 - Sagar Verma, Supriya Agrawal, R. Venkatesh, Ulka Shrotri, Srinarayana Nagarathinam, Rajesh Jayaprakash, Aabriti Dutta:
EImprove - Optimizing Energy and Comfort in Buildings based on Formal Semantics and Reinforcement Learning. 157-162 - Zhenge Jia, Feng Hong, Lichuan Ping, Yiyu Shi, Jingtong Hu:
Enabling On-Device Model Personalization for Ventricular Arrhythmias Detection by Generative Adversarial Networks. 163-168 - Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young:
Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation. 169-174 - Bingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao-Wen Chang:
Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection. 175-180 - Sean Shang-En Tseng, Iris Hui-Ru Jiang, James P. Shiely:
Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval. 181-186 - Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng:
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. 187-192 - Liang Zhao, Chu Yan, Fan Yang, Shifan Gao, Gabriel Rosca, Dan Manea, Zhichao Lu, Yi Zhao:
A Compute-in-Memory Architecture Compatible with 3D NAND Flash that Parallelly Activates Multi-Layers. 193-198 - Orian Leitersdorf, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. 199-204 - Lei He, Cheng Liu, Ying Wang, Shengwen Liang, Huawei Li, Xiaowei Li:
GCiM: A Near-Data Processing Accelerator for Graph Construction. 205-210 - Fan Zhang, Shaahin Angizi, Deliang Fan:
Max-PIM: Fast and Efficient Max/Min Searching in DRAM. 211-216 - Rozhin Yasaei, Shih-Yuan Yu, Emad Kasaeyan Naeini, Mohammad Abdullah Al Faruque:
GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection. 217-222 - Rajat Sadhukhan, Sayandeep Saha, Debdeep Mukhopadhyay:
Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-Synthesis. 223-228 - Gaurav Kolhe, Soheil Salehi, Tyler David Sheaves, Houman Homayoun, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan:
Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks. 229-234 - Michael Zuzak, Yuntao Liu, Ankur Srivastava:
A Resource Binding Approach to Logic Obfuscation. 235-240 - Changchun Zhou, Min Liu, Siyuan Qiu, Yifan He, Hailong Jiao:
An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance. 241-246 - Jounghoo Lee, Jinwoo Choi, Jaeyeon Kim, Jinho Lee, Youngsok Kim:
Dataflow Mirroring: Architectural Support for Highly Efficient Fine-Grained Spatial Multitasking on Systolic-Array NPUs. 247-252 - Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna:
RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. 253-258 - Je Yang, Seongmin Hong, Joo-Young Kim:
FIXAR: A Fixed-Point Deep Reinforcement Learning Platform with Quantization-Aware Training and Adaptive Parallelism. 259-264 - Martin Rapp, Mohammed Bakr Sikal, Heba Khdr, Jörg Henkel:
SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core Processors. 265-270 - Vijay Kandiah, Ali Murat Gök, Georgios Tziantzioulis, Nikos Hardavellas:
ST2 GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders. 271-276 - Sandro M. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon:
Synergically Rebalancing Parallel Execution via DCT and Turbo Boosting. 277-282 - Rassul Bairamkulov, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas, Eby G. Friedman:
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping. 283-288 - Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran:
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. 289-294 - Yukui Luo, Cheng Gongye, Yunsi Fei, Xiaolin Xu:
DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA. 295-300 - Ke Xia, Yukui Luo, Xiaolin Xu, Sheng Wei:
SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture. 301-306 - Wende Tan, Yuan Li, Chao Zhang, Xingman Chen, Songtao Yang, Ying Liu, Jianping Wu:
ROLoad: Securing Sensitive Operations with Pointee Integrity. 307-312 - Ivan De Oliveira Nunes, Sashidhar Jakkamsetti, Gene Tsudik:
DIALED: Data Integrity Attestation for Low-end Embedded Devices. 313-318 - Pantea Kiaei, Cees-Bart Breunesse, Mohsen Ahmadi, Patrick Schaumont, Jasper Van Woudenberg:
Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection. 319-324 - Pramesh Pandey, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy:
UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating. 325-330 - Santosh Shetty, Benjamin Carrión Schäfer:
Enabling the Design of Behavioral Systems-on-Chip. 331-336 - Kanghyun Choi, Deokki Hong, Hojae Yoon, Joonsang Yu, Youngsok Kim, Jinho Lee:
DANCE: Differentiable Accelerator/Network Co-Exploration. 337-342 - Jackson Woodruff, Michael F. P. O'Boyle:
New Regular Expressions on Old Accelerators. 343-348 - Nathaniel Bleier, John Sartori, Rakesh Kumar:
Property-driven Automatic Generation of Reduced-ISA Hardware. 349-354 - Hebi Li, Youbiao He, Qi Xiao, Jin Tian, Forrest Sheng Bao:
BHDL: A Lucid, Expressive, and Embedded Programming Language and System for PCB Designs. 355-360 - Haowen Fang, Brady Taylor, Ziru Li, Zaidao Mei, Hai Helen Li, Qinru Qiu:
Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning. 361-366 - Amar Shrestha, Haowen Fang, Daniel Patrick Rider, Zaidao Mei, Qinru Qiu:
In-Hardware Learning of Multilayer Spiking Neural Networks on a Neuromorphic Processor. 367-372 - Seongsik Park, Dongjin Lee, Sungroh Yoon:
Noise-Robust Deep Spiking Neural Networks with Temporal Information. 373-378 - Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique:
SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM. 379-384 - Maxence Bouvier, Alexandre Valentian, Gilles Sicard:
Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers. 385-390 - Dongning Ma, Jianmin Guo, Yu Jiang, Xun Jiao:
HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing. 391-396 - Yixuan Wang, Chao Huang, Zhilu Wang, Shichao Xu, Zhaoran Wang, Qi Zhu:
Cocktail: Learn a Better Neural Network Controller from Multiple Experts via Adaptive Mixing and Robust Distillation. 397-402 - Mohanad Odema, Nafiul Rashid, Berken Utku Demirel, Mohammad Abdullah Al Faruque:
LENS: Layer Distribution Enabled Neural Architecture Search in Edge-Cloud Hierarchies. 403-408 - Min Li, Yu Li, Ye Tian, Li Jiang, Qiang Xu:
AppealNet: An Efficient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference. 409-414 - Chengsi Gao, Ying Wang, Weiwei Chen, Lei Zhang:
An Intelligent Video Processing Architecture for Edge-cloud Video Streaming. 415-420 - Ruoyang Liu, Lu Zhang, Jingyu Wang, Huazhong Yang, Yongpan Liu:
PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking. 421-426 - Guoqi Xie, Debayan Roy, Yawen Zhang, Renfa Li, Wanli Chang:
Obfuscated Priority Assignment to CAN-FD Messages with Dependencies: A Swapping-based and Affix-Matching Approach. 427-432 - Niels Gleinig, Torsten Hoefler:
An Efficient Algorithm for Sparse Quantum State Preparation. 433-438 - Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang:
Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation. 439-444 - Lei Xie, Jidong Zhai, Weimin Zheng:
Mitigating Crosstalk in Quantum Computers through Commutativity-Based Instruction Reordering. 445-450 - Yosuke Ueno, Masaaki Kondo, Masamitsu Tanaka, Yasunari Suzuki, Yutaka Tabuchi:
QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code. 451-456 - Chen-Hao Hsu, Wan-Hsuan Lin, Wei-Hsiang Tseng, Yao-Wen Chang:
A Bridge-based Compression Algorithm for Topological Quantum Circuits. 457-462 - Daniel Volya, Prabhat Mishra:
Quantum Spectral Clustering of Mixed Graphs. 463-468 - Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan:
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. 469-474 - Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems. 475-480 - Georgios Zervakis, Ourania Spantidi, Iraklis Anagnostopoulos, Hussam Amrouch, Jörg Henkel:
Control Variate Approximation for DNN Accelerators. 481-486 - Nanyang Ye, Jingbiao Mei, Zhicheng Fang, Yuwen Zhang, Ziqing Zhang, Huaying Wu, Xiaoyao Liang:
BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture. 487-492 - Tianyun Zhang, Xiaolong Ma, Zheng Zhan, Shanglin Zhou, Caiwen Ding, Makan Fardad, Yanzhi Wang:
A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods. 493-498 - Shuyuan Yu, Yibo Liu, Sheldon X.-D. Tan:
COSAIM: Counter-based Stochastic-behaving Approximate Integer Multiplier for Deep Neural Networks. 499-504 - Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen:
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. 505-510 - Zhongkai Wang, Minsoo Choi, Eric Chang, John Charles Wright, Wooham Bae, Sijun Du, Zhaokai Liu, Nathan Narevsky, Colin Schmidt, Ayan Biswas, Borivoje Nikolic, Elad Alon:
An Automated and Process-Portable Generator for Phase-Locked Loop. 511-516 - Jialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng:
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization. 517-522 - Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi:
Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs. 523-528 - Sadullah Canakci, Leila Delshadtehrani, Furkan Eris, Michael Bedford Taylor, Manuel Egele, Ajay Joshi:
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing. 529-534 - Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi:
AutoSVA: Democratizing Formal Verification of RTL Module Interactions. 535-540 - Rodrigo Otoni, Martin Blicha, Patrick Eugster, Antti E. J. Hyvärinen, Natasha Sharygina:
Theory-Specific Proof Steps Witnessing Correctness of SMT Executions. 541-546 - Kaichen Yang, Xuan-Yi Lin, Yixin Sun, Tsung-Yi Ho, Yier Jin:
3D-Adv: Black-Box Adversarial Attacks against Deep Learning Models through 3D Sensors. 547-552 - Alejandro Hernández-Cano, Rosario Cammarota, Mohsen Imani:
PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning Systems. 553-558 - Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, Mingoo Seok, Deliang Fan, Jae-sun Seo:
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. 559-564 - Deboleena Roy, Indranil Chakraborty, Timur Ibrayev, Kaushik Roy:
On the Intrinsic Robustness of NVM Crossbars Against Adversarial Attacks. 565-570 - Bosheng Liu, Zhuoshen Jiang, Jigang Wu, Xiaoming Chen, Yinhe Han, Peng Liu:
F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM. 571-576 - Yintao He, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li:
TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. 577-582 - Tao Yang, Dongyue Li, Yibo Han, Yilong Zhao, Fangxin Liu, Xiaoyao Liang, Zhezhi He, Li Jiang:
PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration. 583-588 - Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng:
RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. 589-594 - Yun-Chih Chen, Chun-Feng Wu, Yuan-Hao Chang, Tei-Wei Kuo:
Reptail: Cutting Storage Tail Latency with Inherent Redundancy. 595-600 - Lixiang Li, Yao Chen, Zacharie Zirnheld, Pan Li, Cong Hao:
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. 601-606 - Aryan Deshwal, Syrine Belakaria, Ganapati Bhat, Janardhan Rao Doppa, Partha Pratim Pande:
Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: An Information-Theoretic Approach. 607-612 - Xinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha:
Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation. 613-618 - Keerthikumara Devarajegowda, Endri Kaja, Sebastian Siegfried Prebeck, Wolfgang Ecker:
ISA Modeling with Trace Notation for Context Free Property Generation. 619-624 - Xingyu Meng, Kshitij Raj, Atul Prasad Deb Nath, Kanad Basu, Sandip Ray:
SoCCAR: Detecting System-on-Chip Security Violations Under Asynchronous Resets. 625-630 - Meng Sha, Xin Chen, Yuzhe Ji, Qingye Zhao, Zhengfeng Yang, Wang Lin, Enyi Tang, Qiguang Chen, Xuandong Li:
Synthesizing Barrier Certificates of Neural Network Controlled Continuous Systems via Approximations. 631-636 - Xin Hong, Mingsheng Ying, Yuan Feng, Xiangzhen Zhou, Sanjiang Li:
Approximate Equivalence Checking of Noisy Quantum Circuits. 637-642 - Antonio Cipolletta, Andrea Calimera:
On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage. 643-648 - Yu-Pei Liang, Yung-Han Hsu, Tseng-Yi Chen, Shuo-Han Chen, Hsin-Wen Wei, Tsan-sheng Hsu, Wei-Kuan Shih:
Eco-feller: Minimizing the Energy Consumption of Random Forest Algorithm by an Eco-pruning Strategy over MLC NVRAM. 649-654 - Yawen Wu, Zhepeng Wang, Dewen Zeng, Yiyu Shi, Jingtong Hu:
Enabling On-Device Self-Supervised Contrastive Learning with Selective Data Contrast. 655-660 - Chenyang Li, Tian Xia, Wenzhe Zhao, Nanning Zheng, Pengju Ren:
SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV. 661-666 - Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. 667-672 - Daniele Cattaneo, Michele Chiari, Nicola Fossati, Stefano Cherubin, Giovanni Agosta:
Architecture-aware Precision Tuning with Multiple Number Representation Systems. 673-678 - Menglong Cui, Mingsong Lv, Qingqiang He, Caiqi Zhang, Chuancai Gu, Tao Yang, Nan Guan:
PRUID: Practical User Interface Distribution for Multi-surface Computing. 679-684 - Francesco Lumpp, Hiren D. Patel, Nicola Bombieri:
A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms. 685-690 - Emre Karabulut, Aydin Aysu:
FALCON Down: Breaking FALCON Post-Quantum Signature Scheme through Side-Channel Attacks. 691-696 - Shuwen Deng, Jakub Szefer:
New Predictor-Based Attacks in Processors. 697-702 - Honggang Yu, Haoqi Shan, Maximillian Panoff, Yier Jin:
Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning. 703-708 - Tao Zhang, Jungmin Park, Mark Tehranipoor, Farimah Farahmandi:
PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation. 709-714 - Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. 715-720 - Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Path-based Timing Analysis. 721-726 - Zhuo Feng:
SGL: Spectral Graph Learning from Measurements. 727-732 - Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim:
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. 733-738 - Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park:
A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. 739-744 - Songyun Qu, Bing Li, Ying Wang, Lei Zhang:
ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator. 745-750 - Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin:
ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. 751-756 - Yonggan Fu, Zhongzhi Yu, Yongan Zhang, Yifan Jiang, Chaojian Li, Yongyuan Liang, Mingchao Jiang, Zhangyang Wang, Yingyan Lin:
InstantNet: Automated Generation and Deployment of Instantaneously Switchable-Precision Networks. 757-762 - Xiaofan Zhang, Dawei Wang, Pierce Chuang, Shugao Ma, Deming Chen, Yuecheng Li:
F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding. 763-768 - Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert J. Ou, Colin Schmidt, Samuel Steffl, John Charles Wright, Ion Stoica, Jonathan Ragan-Kelley, Krste Asanovic, Borivoje Nikolic, Yakun Sophia Shao:
Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. 769-774 - Yeseong Kim, Jiseung Kim, Mohsen Imani:
CascadeHD: Efficient Many-Class Learning Framework Using Hyperdimensional Computing. 775-780 - Prathyush Poduval, Zhuowen Zou, Xunzhao Yin, Elaheh Sadredini, Mohsen Imani:
Cognitive Correlative Encoding for Genome Sequence Matching in Hyperdimensional System. 781-786 - Jacob Laurel, Rem Yang, Atharva Sehgal, Shubham Ugare, Sasa Misailovic:
Statheros: Compiler for Efficient Low-Precision Probabilistic Programming. 787-792 - Nguyen-Dong Ho, Ik-Joon Chang:
TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers. 793-798 - Alberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco D. Santambrogio:
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs. 799-804 - William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza:
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. 805-810 - Yongchen Wang, Ying Wang, Huawei Li, Xiaowei Li:
PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. 811-816 - Yaswanth Yadlapalli, Husheng Zhou, Yuqun Zhang, Cong Liu:
gGuard: Enabling Leakage-Resilient Memory Isolation in GPU-accelerated Autonomous Embedded Systems. 817-822 - Feilong Zuo, Zhengxiong Luo, Junze Yu, Zhe Liu, Yu Jiang:
PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles. 823-828 - Behzad Boroujerdian, Radhika Ghosal, Jonathan J. Cruz, Brian Plancher, Vijay Janapa Reddi:
RoboRun: A Robot Runtime to Exploit Spatial Heterogeneity. 829-834 - Pu Zhao, Geng Yuan, Yuxuan Cai, Wei Niu, Qi Liu, Wujie Wen, Bin Ren, Yanzhi Wang, Xue Lin:
Neural Pruning Search for Real-Time Object Detection of Autonomous Vehicles. 835-840 - Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury:
Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. 841-846 - Yutong Ye, Wupan Zhao, Tongquan Wei, Shiyan Hu, Mingsong Chen:
FedLight: Federated Reinforcement Learning for Autonomous Multi-Intersection Traffic Signal Control. 847-852 - Rajarshi Roy, Jonathan Raiman, Neel Kant, Ilyas Elkin, Robert Kirby, Michael Y. Siu, Stuart F. Oberman, Saad Godil, Bryan Catanzaro:
PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning. 853-858 - Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. 859-864 - Liancheng Jia, Zizhang Luo, Liqiang Lu, Yun Liang:
TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. 865-870 - Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
LUT-Based Optimization For ASIC Design Flow. 871-876 - He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton:
Deep Integration of Circuit Simulator and SAT Solver. 877-882 - Shunning Jiang, Yanghui Ou, Peitian Pan, Christopher Batten:
UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling. 883-888 - Ching-Yuan Chen, Krishnendu Chakrabarty:
Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators. 889-894 - Wenfei Hu, Zhikai Wang, Sen Yin, Zuochang Ye, Yan Wang:
Sensitivity Importance Sampling Yield Analysis and Optimization for High Sigma Failure Rate Estimation. 895-900 - Myung Seok Shim, Hanbin Hu, Peng Li:
Reversible Gating Architecture for Rare Failure Detection of Analog and Mixed-Signal Circuits. 901-906 - Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, Bei Yu:
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration. 907-912 - Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar:
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. 913-918 - Wentian Jin, Liang Chen, Sheriff Sadiqbatcha, Shaoyi Peng, Sheldon X.-D. Tan:
EMGraph: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnect Using Graph Convolution Networks. 919-924 - Sai Surya Kiran Pentapati, Sung Kyu Lim:
Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs. 925-930 - Yuan Li, Ahmed Louri, Avinash Karanth:
Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects. 931-936 - Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, Deming Chen:
Skew-Oblivious Data Routing for Data Intensive Applications on FPGAs with HLS. 937-942 - Yijiang Guo, Jiarui Wang, Jiaxi Zhang, Guojie Luo:
Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping. 943-948 - Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski:
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics. 949-954 - Jacob R. Stevens, Dipankar Das, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan:
GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks. 955-960 - Harshit Kumar, Nikhil Chawla, Saibal Mukhopadhyay:
Towards Improving the Trustworthiness of Hardware based Malware Detector using Online Uncertainty Estimation. 961-966 - Sanket Shukla, Sai Manoj P. D., Gaurav Kolhe, Setareh Rafatirad:
On-device Malware Detection using Performance-Aware and Robust Collaborative Learning. 967-972 - Andrea Mondelli, Paul Gazzillo, Yan Solihin:
SeMPE: Secure Multi Path Execution Architecture for Removing Conditional Branch Side Channels. 973-978 - Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang:
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. 979-984 - Ghada Dessouky, Mihailo Isakov, Michel A. Kinsy, Pouya Mahmoody, Miguel Mark, Ahmad-Reza Sadeghi, Emmanuel Stapf, Shaza Zeitouni:
Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures. 985-990 - Johannes Müller, Mohammad Rahmani Fadiheh, Anna Lena Duque Antón, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz:
A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level. 991-996 - Zirui Xu, Fuxun Yu, Jinjun Xiong, Xiang Chen:
Helios: Heterogeneity-Aware Federated Learning with Dynamically Balanced Collaboration. 997-1002 - Yuhong Song, Weiwen Jiang, Bingbing Li, Panjie Qi, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Sakyasingha Dasgupta, Yiyu Shi, Caiwen Ding:
Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices. 1003-1008 - Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo:
BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. 1009-1014 - Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Francesco Conti, Lorenzo Lamberti, Enrico Macii, Luca Benini, Massimo Poncino:
Pruning In Time (PIT): A Lightweight Network Architecture Optimizer for Temporal Convolutional Networks. 1015-1020 - Chunyun Chen, Zhe Wang, Xiaowei Chen, Jie Lin, Mohamed M. Sabry Aly:
Efficient Tunstall Decoder for Deep Neural Network Compression. 1021-1026 - Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha:
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. 1027-1032 - Tao Song, Xiaoming Chen, Xiaoyu Zhang, Yinhe Han:
BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System. 1033-1038 - Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices. 1039-1044 - Yixin Guo, Pengcheng Li, Yingwei Luo, Xiaolin Wang, Zhenlin Wang:
GRAPHSPY: Fused Program Semantic Embedding through Graph Neural Networks for Memory Efficiency. 1045-1050 - Yujun Lin, Mengtian Yang, Song Han:
NAAS: Neural Accelerator Architecture Search. 1051-1056 - Rachmad Vidya Wicaksana Putra, Muhammad Shafique:
SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments. 1057-1062 - Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk:
High-Performance FPGA-based Accelerator for Bayesian Neural Networks. 1063-1068 - Febin Sunny, Asif Mirza, Mahdi Nikdast, Sudeep Pasricha:
CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator. 1069-1074 - Thai-Hoang Nguyen, Muhammad Imran, Jaehyuk Choi, Joon-Sung Yang:
Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks. 1075-1080 - Baogang Zhang, Rickard Ewetz:
Towards Resilient Deployment of In-Memory Neural Networks with High Throughput. 1081-1086 - HanCheon Yun, Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator. 1087-1092 - Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok:
CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. 1093-1098 - Yi Wang, Weixuan Chen, Xianhua Wang, Rui Mao:
LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM. 1099-1104 - Manoj Pravakar Saha, Adnan Maruf, Bryan S. Kim, Janki Bhimani:
KV-SSD: What Is It Good For? 1105-1110 - Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, Jian-Jia Chen:
BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory. 1111-1116 - Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen:
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. 1117-1122 - Zizheng Guo, Jing Mai, Yibo Lin:
Ultrafast CPU/GPU Kernels for Density Accumulation in Placement. 1123-1128 - Ming-Hung Chen, Yao-Wen Chang, Junjie Wang:
Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems. 1129-1134 - Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young:
REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. 1135-1140 - Shih-Ting Lin, Hung-Hsiao Wang, Chia-Yu Kuo, Yolo Chen, Yih-Lang Li:
A Complete PCB Routing Methodology with Concurrent Hierarchical Routing. 1141-1146 - Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias. 1147-1152 - Gyeongtaek Kim, Sungjin Lee, Hoon Sung Chwa:
Dynamic Chip Clustering and Task Allocation for Real-time Flash. 1153-1158 - Zhe Jiang, Kecheng Yang, Yunfeng Ma, Nathan Fisher, Neil C. Audsley, Zheng Dong:
I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time Performance. 1159-1164 - Zihao Zeng, Chubo Liu, Zhuo Tang, Wanli Chang, Kenli Li:
Training Acceleration for Deep Neural Networks: A Hybrid Parallelization Strategy. 1165-1170 - Paolo Pazzaglia, Daniel Casini, Alessandro Biondi, Marco Di Natale:
Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm. 1171-1176 - Ze-Wei Chen, Hang Lei, Maolin Yang, Yong Liao, Lei Qiao:
A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks. 1177-1182 - Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta:
Designing a 2048-Chiplet, 14336-Core Waferscale Processor. 1183-1188 - Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim:
Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options. 1189-1194 - Prathyush Poduval, Zhuowen Zou, M. Hassan Najafi, Houman Homayoun, Mohsen Imani:
StocHD: Stochastic Hyperdimensional System for Efficient and Robust Learning from Raw Data. 1195-1200 - Cen Chen, Kenli Li, Xiaofeng Zou, Yangfan Li:
DyGNN: Algorithm and Architecture Support of Dynamic Pruning for Graph Neural Networks. 1201-1206 - Jinho Lee, Trevor E. Carlson:
Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs. 1207-1212 - Yanqiang Liu, Jiacheng Ma, Zhengjun Zhang, Linsheng Li, Zhengwei Qi, Haibing Guan:
MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization. 1213-1218 - Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap:
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. 1219-1224 - Kai-En Yang, Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang, Feng-Ming Tsai, Chung-An Wang, Yiju Ting, Chia-Shun Yeh, Chin-Tang Lai:
Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration. 1225-1230 - Karthik Somayaji N. S., Hanbin Hu, Peng Li:
Prioritized Reinforcement Learning for Analog Circuit Optimization With Design Knowledge. 1231-1236 - Konstantinos Touloupas, Nikos Chouridis, Paul P. Sotiriadis:
Local Bayesian Optimization For Analog Circuit Sizing. 1237-1242 - Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. 1243-1248 - Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin:
Interactive Analog Layout Editing with Instant Placement Legalization. 1249-1254 - Pengfei Zuo, Yu Hua, Ling Liang, Xinfeng Xie, Xing Hu, Yuan Xie:
SEALing Neural Network Models in Encrypted Deep Learning Accelerators. 1255-1260 - Mustafa S. Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, Dustin Richmond:
Classifying Computations on Multi-Tenant FPGAs. 1261-1266 - Lutan Zhao, Peinan Li, Rui Hou, Michael C. Huang, Jiazhen Li, Lixin Zhang, Xuehai Qian, Dan Meng:
A Lightweight Isolation Mechanism for Secure Branch Predictors. 1267-1272 - Omais Shafi, Ismi Abidi:
CuckoOnsai: An Efficient Memory Authentication Using Amalgam of Cuckoo Filters and Integrity Trees. 1273-1278 - Jiafeng Xie, Pengzhou He, Wujie Wen:
Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method. 1279-1284 - Andrea Basso, Sujoy Sinha Roy:
Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber. 1285-1290 - Haoxing Ren, Matthew Fojtik:
Invited- NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning. 1291-1294 - Md Sami Ul Islam Sami, Fahim Rahman, Farimah Farahmandi, Adam Cron, Mike Borza, Mark Tehranipoor:
Invited: End-to-End Secure SoC Lifecycle Management. 1295-1298 - Benjamin Tan, Siddharth Garg, Ramesh Karri, Yuntao Liu, Michael Zuzak, Abhisek Chakraborty, Ankur Srivastava, Omid Aramoon, Qian Xu, Gang Qu, Adam A. Porter, Jeno Szep, Warren Savage:
Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP. 1299-1302 - Muhammad Shafique, Theocharis Theocharides, Vijay Janapa Reddi, Boris Murmann:
TinyML: Current Progress, Research Challenges, and Future Roadmap. 1303-1306 - Srinivas Bodapati, Pushkar Ranade, Ramune Nagisetty:
Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems. 1307-1310 - Daniel J. Fremont, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia:
Safety in Autonomous Driving: Can Tools Offer Guarantees? 1311-1314 - Alessandro Pinto:
Requirement Specification, Analysis and Verification for Autonomous Systems. 1315-1318 - Wanli Chang, Shuai Zhao, Simon Burton, Haitong Wang, Ting Chen, Nan Chen, Neil C. Audsley:
Invited: Hardware/Software Co-Synthesis and Co-Optimization for Autonomous Systems. 1319-1322 - Shaoshan Liu, Bo Yu, Jie Tang, Qi Zhu:
Invited: Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities. 1323-1326 - Fabrizio Ferrandi, Vito Giovanni Castellana, Serena Curzel, Pietro Fezzardi, Michele Fiorito, Marco Lattuada, Marco Minutoli, Christian Pilato, Antonino Tumeo:
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications. 1327-1330 - Scott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon:
Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. 1331-1334 - Saransh Gupta, Tajana Simunic Rosing:
Invited: Accelerating Fully Homomorphic Encryption with Processing in Memory. 1335-1338 - Dewen Zeng, Yukun Ding, Haiyun Yuan, Meiping Huang, Xiaowei Xu, Jian Zhuang, Jingtong Hu, Yiyu Shi:
Invited: Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography. 1339-1342 - Suraj Mishra, Danny Z. Chen, X. Sharon Hu:
INVITED: kCC-Net for Compression of Biomedical Image Segmentation Networks. 1343-1346 - Song Bian, Weiwen Jiang, Takashi Sato:
Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment. 1347-1350 - Kathleen E. Hamilton, Emily Lynn, Tyler Kharazi, Titus Morris, Ryan S. Bennink, Raphael C. Pooser:
Building scalable variational circuit training for machine learning tasks. 1351 - Napat Thumwanit, Chayaphol Lortaraprasert, Rudy Raymond:
Invited: Trainable Discrete Feature Embeddings for Quantum Machine Learning. 1352-1355 - Junde Li, Mahabubul Alam, Congzhou M. Sha, Jian Wang, Nikolay V. Dokholyan, Swaroop Ghosh:
Invited: Drug Discovery Approaches using Quantum Machine Learning. 1356-1359 - António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement. 1360-1361 - Zhipeng Huang, Haokai Sun, Huimin Wang, Ziran Zhu, Jun Yu, Jianli Chen:
Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints. 1362-1363 - Xiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen:
Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. 1364-1365 - Peng Zou, Zhifeng Lin, Chenyue Ma, Jun Yu, Jianli Chen:
Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement. 1366-1367 - Jianli Chen, Jiarui Chen, Xiao Shi, Lichong Sun, Jun Yu:
Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning. 1368-1369 - Ding-Hao Wang, Pei-Ju Lin, Hui-Ting Yang, Ching-An Hsu, Sin-Han Huang, Mark Po-Hung Lin:
A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths. 1370-1371 - Dmitry Utyamishev, Inna Partin-Vaisband:
Late Breaking Results: Parallelizing Net Routing with cGANs. 1372-1373 - Yingjie Li, Cunxi Yu:
Late Breaking Results: Physical Adversarial Attacks of Diffractive Deep Neural Networks. 1374-1375 - Alireza Mahzoon, Rolf Drechsler:
Late Breaking Results: Polynomial Formal Verification of Fast Adders. 1376-1377 - Xavier Timoneda, Lukas Cavigelli:
Late Breaking Results: Reinforcement Learning for Scalable Logic Optimization with Graph Neural Networks. 1378-1379 - Lejla Batina, Rosario Cammarota, Nele Mentens, Ahmad-Reza Sadeghi, Johanna Sepúlveda, Shaza Zeitouni:
Invited: Security Beyond Bulk Silicon: Opportunities and Challenges of Emerging Devices. 1-4
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