Logic optimization is a process that takes a logic circuit description (Boolean network) as an in... more Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network in a reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic synthesis and optimization processes, both academic and commercial, and suggest actions to mitigate the disturbing effects.
16th Euromicro Conference on Digital System Design (Dsd 2013), 2013
This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefi... more This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.
Abstract: Testing of digital circuits seems to be a completely mastered part of the design flow, ... more Abstract: Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefit from an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS’85, ‘89 and ITC’99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SA...
In this paper we propose several methods of generating large benchmark circuits for testing logic... more In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be advantageously used for testing logic synthesis tools; the aim is to discover whether particular synthesis processes are sensitive or immune to particular circuit transformations.
In this paper we propose several methods of generating large benchmark circuits for testing logic... more In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be advantageously used for testing logic synthesis tools; the aim is to discover whether particular synthesis processes are sensitive or immune to particular circuit transformations.
A method to find hard logic synthesis examples with known upper bound is presented. The circuits ... more A method to find hard logic synthesis examples with known upper bound is presented. The circuits can be small and yet difficult to synthesize. Any area-related metric can be used in finding the circuits and testing synthesis tools. The hardness of the examples is robust with respect to the metric used and to minor alterations in the circuit.
We present experimental evidence that logic synthesis procedure, especially those based on resynt... more We present experimental evidence that logic synthesis procedure, especially those based on resynthesis, do net perform well when the original (designer-given) structure of input description is lost. As such performance has not been observed otherwise, we must conclude that such operation is outside of the intended range, and that synthesis examples with their original structure lost are not valid for evaluation of synthesis procedures. We also outline other causes that may render an example invalid. We, however, document that such losses did occur with circuit examples circulating in the logic synthesis community. Therefore, we have to suggest what constitutes prudence in examples collection.
Recently we have observed, that behavior of many contemporary logic synthesis and optimization pr... more Recently we have observed, that behavior of many contemporary logic synthesis and optimization processes depends on variable ordering in their input; they produce different results for different variable orderings. This fact can be exploited to escape local optima in the iterative resynthesis process, where individual synthesis and optimization steps are run repeatedly, in order to gradually improve the solution quality. In this paper we show an experimental analysis of influence of variable ordering on the result quality, for different synthesis steps in ABC. Next, we present a method of using random permutations of variables in the overall iterative synthesis process, in order to improve the result quality. Experimental evaluation using both standard benchmarks and industrial circuits is presented, to show the viability of the concept.
In this paper we introduce a new set of example circuits, primarily intended for using in logic s... more In this paper we introduce a new set of example circuits, primarily intended for using in logic synthesis and optimization, mostly for testing and benchmarking purposes. Basically, the proposed set of circuits is a collection of former popular benchmark sets. By putting these circuits together, we have formed a more comprehensive, but unified and well-arranged set of example circuits, from which a user can select circuits (or the whole benchmarks) upon his wishes and needs. The collection comprises of several sets, which, even though they sometimes contain the same circuits, are customized to particular needs of the user. This paper documents the example set, together with origins of its parts, and statistics on the circuits are provided.
In this paper we investigate iterative logic synthesis processes. A well known academic logic syn... more In this paper we investigate iterative logic synthesis processes. A well known academic logic synthesis tool ABC incorporates many synthesis algorithms and scripts which may be run iteratively to possibly improve the result. When iterating the synthesis process, the whole network is considered. We propose an alternative approach to iterative synthesis – only properly selected parts of the circuit are submitted to resynthesis, which is done iteratively. We show that a significant improvement in the result quality may be achieved. This observation is rather surprising and witnesses probably a lack of efficiency of the ABC resynthesis control. The observations are documented by numerous experiments on ISCAS and IWLS’93 benchmark circuits. Keywords-logic synthesis, resynthesis, iterative processes, ABC
In this paper we propose a study of properties of SAT (satisfiability) instances produced by SAT-... more In this paper we propose a study of properties of SAT (satisfiability) instances produced by SAT-based Automatic Test Pattern Generators (ATPGs). Standard non-commercial SAT solvers are being widely used for the purpose of solving these instances. We show an analysis of properties of these special SAT instances. Even though these ATPG SAT instances have been thoroughly studied in the past, we show some newly found properties. Particularly, reasons why ATPG SAT instances are ‘easy to be solved’ are shown by analysis of the SAT instances. Then, unexpected behavior of ATPG SAT instances, in terms of their satisfiability, was observed. Next, we propose solution-preserving SAT transformations and study the properties of the reduced SAT instances.
Logic synthesis and optimization had become a well-established and matured process in late 1980’s... more Logic synthesis and optimization had become a well-established and matured process in late 1980’s. Since that time, different decomposition and optimization algorithms have been proposed [1], [2] and academic tools implementing these algorithms were released [3], [4]. Here, the internal representation of a processed circuit is typically a Boolean network, admitting arbitrary node functions. Technology library gates appear later, in the technology mapping phase [1], [2]. As a successor, algorithms based on And-InverterGraphs (AIGs) appeared [5], [6] and were implemented in the present academic state-of-the-art logic synthesis tool ABC [7]. The internal representation is a directed acyclic graph with nodes representing 2-input AND operators, while the edges may be negated. Such a representation is simple and scalable, and leads to simple algorithms. Despite of unquestionable advantages of AIG-based algorithms, there appeared hints recently, that contemporary logic synthesis does not p...
Normal Basis Multipliers of General Digit Width Applicable in ECC
2006 IEEE Design and Diagnostics of Electronic Circuits and systems
ABSTRACT We present two architectures of digit-serial normal basis multiplier over GF(2m). The mu... more ABSTRACT We present two architectures of digit-serial normal basis multiplier over GF(2m). The multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in public-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA
2017 Euromicro Conference on Digital System Design (DSD)
This paper presents a method for generating optimum multi-level implementations of Boolean functi... more This paper presents a method for generating optimum multi-level implementations of Boolean functions. It is based on Satisfiability (SAT) problem solving, while different SAT techniques are employed to reach different targets. The method is able to generate one, or enumerate all optimum implementations, while any technology constraints can be applied. Results for 4-input functions implemented by XOR-AND-Inverter-Graphs (XAIGs) with different XOR nodes costs are presented. Scalability and feasibility of the method is presented. Finally, an experimental evaluation of XAIG-based rewriting algorithm with optimum replacement circuits is presented and compared with the previous solution.
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2003
The design of a scalable arithmetic unit for operations over elements of GF(2 m) represented in n... more The design of a scalable arithmetic unit for operations over elements of GF(2 m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in a single arithmetic unit. We discuss optimum design of the shifter with respect to the inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D = 15.
Implicit Representations in Test Patterns Compression for Scan-Based Digital Circuits
Current test generation and compression processes still have a room for improvement. One importan... more Current test generation and compression processes still have a room for improvement. One important factor is the representation of test vector sets that a tool uses internally. We overview known approaches to this problem, and present our results obtained by using an implicit representation by instances of the satisfiability problem. With the growing complexity of designs, the amount of test patterns needed to be stored and applied to the tested circuit grows up significantly. That is why the compression of test patterns is needed to decrease memory requirements and time consumption of the test. ATPG (Automatic Test Pattern Generation) and compression of test patterns is based on manipulation of sets of binary vectors. The sets express the possibilities of choice (at least one vector from the set is needed) or summary (the whole set of vectors is needed). Such sets can be expressed explicitly, as an enumeration of vectors, or implicitly, by describing the required characteristic pro...
A design of a scalable arithmetic unit for operations over elements of GF(2m) represented in norm... more A design of a scalable arithmetic unit for operations over elements of GF(2m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in one arithmetic unit. We discuss optimum design of the shifter with respect to inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D=15.
The causal connection between input circuit representation and the quality of the synthesis resul... more The causal connection between input circuit representation and the quality of the synthesis result is investigated, with special attention to the LEKU examples of Cong and Minkovich. It is shown that transformations totally obscuring the original circuit structure can enlarge the input to a great degree, that the LEKU circuits are nothing special in this respect, and that contemporary tools invariably produce poor results. On the other hand, such descriptions do not occur in practice.
Logic optimization is a process that takes a logic circuit description (Boolean network) as an in... more Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network in a reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic synthesis and optimization processes, both academic and commercial, and suggest actions to mitigate the disturbing effects.
16th Euromicro Conference on Digital System Design (Dsd 2013), 2013
This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefi... more This paper presents a novel ATPG algorithm directly producing compressed test patterns. It benefits both from the features of satisfiability-based techniques and symbolic simulation. The ATPG is targeted to architectures comprised of interconnected embedded cores, particularly to the RESPIN architecture. We show experimentally that the proposed ATPG significantly outperforms the state-of-the-art approaches in terms of the test compression ratio.
Abstract: Testing of digital circuits seems to be a completely mastered part of the design flow, ... more Abstract: Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefit from an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS’85, ‘89 and ITC’99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SA...
In this paper we propose several methods of generating large benchmark circuits for testing logic... more In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be advantageously used for testing logic synthesis tools; the aim is to discover whether particular synthesis processes are sensitive or immune to particular circuit transformations.
In this paper we propose several methods of generating large benchmark circuits for testing logic... more In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be advantageously used for testing logic synthesis tools; the aim is to discover whether particular synthesis processes are sensitive or immune to particular circuit transformations.
A method to find hard logic synthesis examples with known upper bound is presented. The circuits ... more A method to find hard logic synthesis examples with known upper bound is presented. The circuits can be small and yet difficult to synthesize. Any area-related metric can be used in finding the circuits and testing synthesis tools. The hardness of the examples is robust with respect to the metric used and to minor alterations in the circuit.
We present experimental evidence that logic synthesis procedure, especially those based on resynt... more We present experimental evidence that logic synthesis procedure, especially those based on resynthesis, do net perform well when the original (designer-given) structure of input description is lost. As such performance has not been observed otherwise, we must conclude that such operation is outside of the intended range, and that synthesis examples with their original structure lost are not valid for evaluation of synthesis procedures. We also outline other causes that may render an example invalid. We, however, document that such losses did occur with circuit examples circulating in the logic synthesis community. Therefore, we have to suggest what constitutes prudence in examples collection.
Recently we have observed, that behavior of many contemporary logic synthesis and optimization pr... more Recently we have observed, that behavior of many contemporary logic synthesis and optimization processes depends on variable ordering in their input; they produce different results for different variable orderings. This fact can be exploited to escape local optima in the iterative resynthesis process, where individual synthesis and optimization steps are run repeatedly, in order to gradually improve the solution quality. In this paper we show an experimental analysis of influence of variable ordering on the result quality, for different synthesis steps in ABC. Next, we present a method of using random permutations of variables in the overall iterative synthesis process, in order to improve the result quality. Experimental evaluation using both standard benchmarks and industrial circuits is presented, to show the viability of the concept.
In this paper we introduce a new set of example circuits, primarily intended for using in logic s... more In this paper we introduce a new set of example circuits, primarily intended for using in logic synthesis and optimization, mostly for testing and benchmarking purposes. Basically, the proposed set of circuits is a collection of former popular benchmark sets. By putting these circuits together, we have formed a more comprehensive, but unified and well-arranged set of example circuits, from which a user can select circuits (or the whole benchmarks) upon his wishes and needs. The collection comprises of several sets, which, even though they sometimes contain the same circuits, are customized to particular needs of the user. This paper documents the example set, together with origins of its parts, and statistics on the circuits are provided.
In this paper we investigate iterative logic synthesis processes. A well known academic logic syn... more In this paper we investigate iterative logic synthesis processes. A well known academic logic synthesis tool ABC incorporates many synthesis algorithms and scripts which may be run iteratively to possibly improve the result. When iterating the synthesis process, the whole network is considered. We propose an alternative approach to iterative synthesis – only properly selected parts of the circuit are submitted to resynthesis, which is done iteratively. We show that a significant improvement in the result quality may be achieved. This observation is rather surprising and witnesses probably a lack of efficiency of the ABC resynthesis control. The observations are documented by numerous experiments on ISCAS and IWLS’93 benchmark circuits. Keywords-logic synthesis, resynthesis, iterative processes, ABC
In this paper we propose a study of properties of SAT (satisfiability) instances produced by SAT-... more In this paper we propose a study of properties of SAT (satisfiability) instances produced by SAT-based Automatic Test Pattern Generators (ATPGs). Standard non-commercial SAT solvers are being widely used for the purpose of solving these instances. We show an analysis of properties of these special SAT instances. Even though these ATPG SAT instances have been thoroughly studied in the past, we show some newly found properties. Particularly, reasons why ATPG SAT instances are ‘easy to be solved’ are shown by analysis of the SAT instances. Then, unexpected behavior of ATPG SAT instances, in terms of their satisfiability, was observed. Next, we propose solution-preserving SAT transformations and study the properties of the reduced SAT instances.
Logic synthesis and optimization had become a well-established and matured process in late 1980’s... more Logic synthesis and optimization had become a well-established and matured process in late 1980’s. Since that time, different decomposition and optimization algorithms have been proposed [1], [2] and academic tools implementing these algorithms were released [3], [4]. Here, the internal representation of a processed circuit is typically a Boolean network, admitting arbitrary node functions. Technology library gates appear later, in the technology mapping phase [1], [2]. As a successor, algorithms based on And-InverterGraphs (AIGs) appeared [5], [6] and were implemented in the present academic state-of-the-art logic synthesis tool ABC [7]. The internal representation is a directed acyclic graph with nodes representing 2-input AND operators, while the edges may be negated. Such a representation is simple and scalable, and leads to simple algorithms. Despite of unquestionable advantages of AIG-based algorithms, there appeared hints recently, that contemporary logic synthesis does not p...
Normal Basis Multipliers of General Digit Width Applicable in ECC
2006 IEEE Design and Diagnostics of Electronic Circuits and systems
ABSTRACT We present two architectures of digit-serial normal basis multiplier over GF(2m). The mu... more ABSTRACT We present two architectures of digit-serial normal basis multiplier over GF(2m). The multipliers were derived from the multiplier of Agnew et al. Proposed multipliers are scalable by the digit width of general value in difference of the multiplier of Agnew et al. that may be scaled only by digit width that divides the degree m. This helps designers to trade area for speed e.g. in public-key cryptographic systems based on elliptic-curves, where m should be a prime number. Functionality of multipliers has been tested by simulation and implemented in Xilinx Virtex 4 FPGA
2017 Euromicro Conference on Digital System Design (DSD)
This paper presents a method for generating optimum multi-level implementations of Boolean functi... more This paper presents a method for generating optimum multi-level implementations of Boolean functions. It is based on Satisfiability (SAT) problem solving, while different SAT techniques are employed to reach different targets. The method is able to generate one, or enumerate all optimum implementations, while any technology constraints can be applied. Results for 4-input functions implemented by XOR-AND-Inverter-Graphs (XAIGs) with different XOR nodes costs are presented. Scalability and feasibility of the method is presented. Finally, an experimental evaluation of XAIG-based rewriting algorithm with optimum replacement circuits is presented and compared with the previous solution.
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2003
The design of a scalable arithmetic unit for operations over elements of GF(2 m) represented in n... more The design of a scalable arithmetic unit for operations over elements of GF(2 m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in a single arithmetic unit. We discuss optimum design of the shifter with respect to the inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D = 15.
Implicit Representations in Test Patterns Compression for Scan-Based Digital Circuits
Current test generation and compression processes still have a room for improvement. One importan... more Current test generation and compression processes still have a room for improvement. One important factor is the representation of test vector sets that a tool uses internally. We overview known approaches to this problem, and present our results obtained by using an implicit representation by instances of the satisfiability problem. With the growing complexity of designs, the amount of test patterns needed to be stored and applied to the tested circuit grows up significantly. That is why the compression of test patterns is needed to decrease memory requirements and time consumption of the test. ATPG (Automatic Test Pattern Generation) and compression of test patterns is based on manipulation of sets of binary vectors. The sets express the possibilities of choice (at least one vector from the set is needed) or summary (the whole set of vectors is needed). Such sets can be expressed explicitly, as an enumeration of vectors, or implicitly, by describing the required characteristic pro...
A design of a scalable arithmetic unit for operations over elements of GF(2m) represented in norm... more A design of a scalable arithmetic unit for operations over elements of GF(2m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in one arithmetic unit. We discuss optimum design of the shifter with respect to inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA. We present implementation data for various digit widths which exhibit a time minimum for digit width D=15.
The causal connection between input circuit representation and the quality of the synthesis resul... more The causal connection between input circuit representation and the quality of the synthesis result is investigated, with special attention to the LEKU examples of Cong and Minkovich. It is shown that transformations totally obscuring the original circuit structure can enlarge the input to a great degree, that the LEKU circuits are nothing special in this respect, and that contemporary tools invariably produce poor results. On the other hand, such descriptions do not occur in practice.
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Papers by Jan Schmidt