Raheel Malik
I'm a Computer Engineer. A Computer and Digital Hardware designer, VHDL coder, Hardware verification & tester. Expert in application development on C and VHDL Platforms. I have plenty of experience in working in IT security and Network solution providing, i also have experience of working in Telecom sector.
My Area of interest and expertise are : Programming languages: XML coding, C++, C, VHDL for Hardware description and Designing.
Database systems like MS Access.
Circuit and Network simulators NS2, Packet Tracer, OptSim, Multisim, PSPICE, MATLAB.
Hardware description languages: Verilog HDL.
Word processing, Spreadsheet, graphics and web design, and animation software like MS Word, Excel, PowerPoint, Adobe Photoshop, Adobe Flash, Adobe Dreamweaver, etc.
Phone: +1 514-432-3439
My Area of interest and expertise are : Programming languages: XML coding, C++, C, VHDL for Hardware description and Designing.
Database systems like MS Access.
Circuit and Network simulators NS2, Packet Tracer, OptSim, Multisim, PSPICE, MATLAB.
Hardware description languages: Verilog HDL.
Word processing, Spreadsheet, graphics and web design, and animation software like MS Word, Excel, PowerPoint, Adobe Photoshop, Adobe Flash, Adobe Dreamweaver, etc.
Phone: +1 514-432-3439
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Transform (DCT) computation engine based on Single Instruction
stream and Multiple Data stream (SIMD) - Array Processors.
Each pixel of an input matrix is distributed across a 4-way
connected Processing Element (PE); and a frame comprises
several such PEs making it possible to compute as many pixels as
the number of PEs in a frame. Tripling such frames allows us to
compress a colored image as efficiently as any gray-scale image.
We specifically target least possible computations by completely
replacing a floating-point unit by Look-up-Tables (LUTs) and an
efficient implementation of an 8-bit multiplier is presented. By
making use of nine processors, arranged in a matrix of the order
3x3, we manage to compute nine coefficients in less than nine
clock cycles resulting in a tremendous Data-Rate (DR) of
1.4Gbps at the cost of 967 slices. Performance is analyzed using
SPARTAN III FPGA (Field Programmable Gate Array) and a
comparison with a previously proposed systolic architecture is
presented.
Transform (DCT) computation engine based on Single Instruction
stream and Multiple Data stream (SIMD) - Array Processors.
Each pixel of an input matrix is distributed across a 4-way
connected Processing Element (PE); and a frame comprises
several such PEs making it possible to compute as many pixels as
the number of PEs in a frame. Tripling such frames allows us to
compress a colored image as efficiently as any gray-scale image.
We specifically target least possible computations by completely
replacing a floating-point unit by Look-up-Tables (LUTs) and an
efficient implementation of an 8-bit multiplier is presented. By
making use of nine processors, arranged in a matrix of the order
3x3, we manage to compute nine coefficients in less than nine
clock cycles resulting in a tremendous Data-Rate (DR) of
1.4Gbps at the cost of 967 slices. Performance is analyzed using
SPARTAN III FPGA (Field Programmable Gate Array) and a
comparison with a previously proposed systolic architecture is
presented.