JaWone Kennedy

Clemson University, Electrical Engineering, Alumnus

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Julita Vassileva

University of Saskatchewan

B. Harun Küçük

University of Pennsylvania

Kostas Zafiropoulos

University of Macedonia

Marisol de la Cadena

University of California, Davis

David Seamon

Kansas State University

Christopher Witmore

Texas Tech University

Armando Marques-Guedes

UNL - New University of Lisbon

Elisa Bonacini

Università degli Studi di Bari

Fatiha Djemili Tolba

Badji Mokhtar - Annaba University

Laszlo Ropolyi

Eötvös Loránd University

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Papers by JaWone Kennedy

A technique to improve the performance of fixed-point TDMP decoding of QC-LDPC codes in the presence of SNR estimation error

2011 - MILCOM 2011 Military Communications Conference, 2011

Most high-throughput, fixed-point processors offer at least two options for arithmetic operations... more Most high-throughput, fixed-point processors offer at least two options for arithmetic operations: 8-bit arithmetic, and 16-bit arithmetic. The lower resolution provides higher computational throughput at the cost of poorer performance in many applications. We investigate the effect of the resolution of saturating, fixed-point arithmetic on the performance of the turbo-decoding message-passing algorithm with quasi-cyclic low-density parity-check codes. We consider limits on the magnitude of extrinsic updates as a means to mitigate the effect of posterior-value saturation on the decoder's performance. We show that a fixed limit on updates only partially overcomes the greater effect of saturation in 8-bit operations, whereas a limit that depends on the degree of the variable node results in performance almost as good as what is possible with 16-bit operations.

Performance under delay constraints on iterative decoding of LDPC codes

MILCOM 2008 - 2008 IEEE Military Communications Conference, 2008

The performance of a system with a quasi-cyclic low-density parity-check code is examined under v... more The performance of a system with a quasi-cyclic low-density parity-check code is examined under various constraints on the decoding delay. Two alternatives are considered for the message-passing decoding algorithm: the sum-product algorithm and the turbo-decoding message-passing algorithm. It is shown that their relative performance depends heavily on the stringency of the delay constraint; the TDMP algorithm results in substantially better performance than the SPA if the constraint is stringent.

New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors

Most digital signal processors contain one or more functional units with a single-instruction, mu... more Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arithmetic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such functional units connected through an on-chip network. The selection of the arithmetic precision provides a trade-off between the task-level throughput and the quality of the output of many signal-processing algorithms, and utilization of the interconnection network during execution of the algorithm introduces a latency that can also limit the algorithm’s throughput. In this dissertation, we consider the turbo-decoding message-passing algorithm for iterative decoding of low-density parity-check codes and investigate its performance in parallel execution on a processor of interconnected functional units employing fast, low-precision fixed-point arithmetic. It is shown that the frequent occurren...

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A technique to improve the performance of fixed-point TDMP decoding of QC-LDPC codes in the presence of SNR estimation error

… CONFERENCE, 2011-MILCOM …, 2011

Decoding of a quasi-cyclic LDPC code on a stream processor

… CONFERENCE, 2010-MILCOM …, 2010

The TDMP layered belief-propagation algorithm is investigated for decoding a quasi-cyclic low-den... more The TDMP layered belief-propagation algorithm is investigated for decoding a quasi-cyclic low-density parity-check code on a stream processor using fixed-point arithmetic. The effect of the processor's fixed-point resolution on the decoder performance is determined, and a simple technique is described for minimizing the performance penalty incurred when using the (highest throughput) lowest-resolution arithmetic mode of the processor. A reordering of the decoder schedule and a modification of the parity checks are also considered which permit increased software pipelining and improved latency hiding, with a corresponding increase in the data throughput. The fixed-point Storm-1 stream processor is used for comparative throughput results.

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Scheduling parity checks for increased throughput in early-termination, layered decoding of QC-LDPC codes on a stream processor

EURASIP Journal on Wireless …, 2012

A stream processor is a power-efficient, high-level-language programmable option for embedded app... more A stream processor is a power-efficient, high-level-language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism. Many signal-processing algorithms for communications are well matched to stream-processor architectures, including partially parallel implementations of layered decoding algorithms such as the turbo-decoding message-passing (TDMP) algorithm. Communication among clusters of functional units in the stream processor impose a latency cost during both the message-passing phase and the parity-check phase of the TDMP algorithm with early termination; the inter-cluster communications latency is a significant factor in limiting the throughput of the decoder. We consider two modifications of the schedule for the TDMP algorithm with early termination; each halves the communication required between functional-unit clusters of the stream processor in each iteration. We show that these can provide a substantial increase in the information throughput of the decoder without increasing the probability of error.

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New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors

Performance under delay constraints on iterative decoding of LDPC codes

… Communications Conference, 2008 …, 2008

The performance of a system with a quasi-cyclic lowdensity parity-check code is examined under va... more The performance of a system with a quasi-cyclic lowdensity parity-check code is examined under various constraints on the decoding delay. Two alternatives are considered for the message-passing decoding algorithm: the sumproduct algorithm and the turbo-decoding message-passing algorithm. It is shown that their relative performance depends heavily on the stringency of the delay constraint; the TDMP algorithm results in substantially better performance than the SPA if the constraint is stringent.