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Kevin Jones

City, University of London, Centre for Software Reliability, Faculty Member

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UNL - New University of Lisbon

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Vanderbilt University

Dublin Institute of Technology

Sharif University of Technology

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Nepal College of Information Technology

Praxis Business School

Viacheslav Kuleshov

Stockholm University

Oliver A. Gubler

University of Applied Sciences Western Switzerland (HES-SO) Valais Wallis

Ciprian Teodorov

Ecole nationale supérieure d'ingénieurs (ENSTA-Bretagne)

King's College London

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Papers by Kevin Jones

Mural: A Formal Development Support System

Invited Tutorial: Analog and Mixed Signal Verification

Abstract—More and more electronic systems have components that are not purely digital. Verificati... more Abstract—More and more electronic systems have components that are not purely digital. Verification of such systems is a much less developed discipline than the digital equivalents and the application of formal (mathematically complete) techniques is a nascent area. In this paper, we will discuss the nature of analog circuit design and describe the way verification is done in practice today. We will describe some “formal” approaches coming from the analog design community.

Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch

Abstract This paper describes an efficient way of simulating the effects of device random mismatc... more Abstract This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators.

LM3: A Larch Interface Language for Modula-3; a Definition and Introduction

Abstract This report describes a Larch interface language (LM3) for the Modula-3 programming lang... more Abstract This report describes a Larch interface language (LM3) for the Modula-3 programming language. LM3 is a complete example of a Larch interface language and addresses areas previously ignored in interface language denition, such as the speci cation of non-atomic procedures and object types. We give a complete de nition of the syntax and illustrate it with some straightforward examples.

Analog and Mixed Signal Verification

More and more electronic systems have components that are not purely digital. Verification of suc... more More and more electronic systems have components that are not purely digital. Verification of such systems is a much less developed discipline than the digital equivalents and the application of formal (mathematically complete) techniques is a nascent area. In this paper, we will discuss the nature of analog circuit design and describe the way verification is done in practice today. We will describe some “formal” approaches coming from the analog design community.

The automatic generation of functional test vectors for Rambus designs

Abstract We present a method for the automatic generation of test vectors for functional verifica... more Abstract We present a method for the automatic generation of test vectors for functional verification, giving the advantages of random and directed testing. We show the use of a formal specification as input to a test generator. We present techniques for the efficient implementation of the generator. We discuss our experience with this method applied to commercial designs. We show how our approach is a stepping stone towards practical formal verification

PHY Verification–What’s Missing

Abstract—PHYs are devices composed of digital and analog circuits that transmit data over a physi... more Abstract—PHYs are devices composed of digital and analog circuits that transmit data over a physical medium. These devices present unique verification challenges. While a PHY contains significant amounts of digital logic, the representation of analog blocks used for verification can make real bugs invisible in simulation. Special modes whose sole purpose is to allow manufacturing test and characterization of analog components add complexity to a device whose normal-mode operation is straightforward.

Efficient simulation based verification by reordering

Abstract—With the increasing complexity of systems, the current simulation based circuit verifica... more Abstract—With the increasing complexity of systems, the current simulation based circuit verification used in industry are becoming more expensive while providing low coverage. The paper presents a systematic way to reduce the verification time by optimizing the execution order of test cases. Compared with the default order maintained by engineers, the optimal order can achieve a high coverage in a short time as it guarantees running the important test case first.

Analog property checkers: a DDR2 case study

Abstract The formal specification component of verification can be exported to simulation through... more Abstract The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors.

Analog/mixed-signal circuit verification using models generated from simulation traces

Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining ... more Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining circuit models at suitable levels of abstraction. We propose a method to automatically generate abstract models suitable for formal verification and system-level simulation from transistor-level simulation traces. This paper discusses the application of the proposed methodology to a switched capacitor integrator and PLL phase detector.

Some “real world” problems in the analog and mixed signal domains

DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones Jaeha Kim,... more DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones Jaeha Kim, Victor Konrad Slide 2 DCC 08 Abstract • Design and verification problems in the digital circuit space are well studied and there are many approaches to establishing correctness, both academic and industrial. However, the analog and mixed signal space is much less developed. • More and more systems are being designed with “mixed mode” functionality.

Larch: languages and tools for formal specification

Texts and Monographs …, Jan 1, 1993

Abstract Preface Building software often seems harder than it ought to be. It takes longerthan ex... more Abstract Preface Building software often seems harder than it ought to be. It takes longerthan expected, the software&amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;#x27;s functionality and performance are not as wonderful as hoped, and the software is not particularly malleable or easyto maintain. It does not have to be that way. This book is about programming, and the role that formal specificationscan play in making programming easier and programs better. The intended audience is practicing programmers and students in undergraduate or basicgraduate courses in software engineering or ...

Mural: A Formal Development Support System

Invited Tutorial: Analog and Mixed Signal Verification

Abstract—More and more electronic systems have components that are not purely digital. Verificati... more Abstract—More and more electronic systems have components that are not purely digital. Verification of such systems is a much less developed discipline than the digital equivalents and the application of formal (mathematically complete) techniques is a nascent area. In this paper, we will discuss the nature of analog circuit design and describe the way verification is done in practice today. We will describe some “formal” approaches coming from the analog design community.

Fast, non-Monte-Carlo estimation of transient performance variation due to device mismatch

Abstract This paper describes an efficient way of simulating the effects of device random mismatc... more Abstract This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators.

LM3: A Larch Interface Language for Modula-3; a Definition and Introduction

Abstract This report describes a Larch interface language (LM3) for the Modula-3 programming lang... more Abstract This report describes a Larch interface language (LM3) for the Modula-3 programming language. LM3 is a complete example of a Larch interface language and addresses areas previously ignored in interface language denition, such as the speci cation of non-atomic procedures and object types. We give a complete de nition of the syntax and illustrate it with some straightforward examples.

Analog and Mixed Signal Verification

More and more electronic systems have components that are not purely digital. Verification of suc... more More and more electronic systems have components that are not purely digital. Verification of such systems is a much less developed discipline than the digital equivalents and the application of formal (mathematically complete) techniques is a nascent area. In this paper, we will discuss the nature of analog circuit design and describe the way verification is done in practice today. We will describe some “formal” approaches coming from the analog design community.

The automatic generation of functional test vectors for Rambus designs

Abstract We present a method for the automatic generation of test vectors for functional verifica... more Abstract We present a method for the automatic generation of test vectors for functional verification, giving the advantages of random and directed testing. We show the use of a formal specification as input to a test generator. We present techniques for the efficient implementation of the generator. We discuss our experience with this method applied to commercial designs. We show how our approach is a stepping stone towards practical formal verification

PHY Verification–What’s Missing

Abstract—PHYs are devices composed of digital and analog circuits that transmit data over a physi... more Abstract—PHYs are devices composed of digital and analog circuits that transmit data over a physical medium. These devices present unique verification challenges. While a PHY contains significant amounts of digital logic, the representation of analog blocks used for verification can make real bugs invisible in simulation. Special modes whose sole purpose is to allow manufacturing test and characterization of analog components add complexity to a device whose normal-mode operation is straightforward.

Efficient simulation based verification by reordering

Abstract—With the increasing complexity of systems, the current simulation based circuit verifica... more Abstract—With the increasing complexity of systems, the current simulation based circuit verification used in industry are becoming more expensive while providing low coverage. The paper presents a systematic way to reduce the verification time by optimizing the execution order of test cases. Compared with the default order maintained by engineers, the optimal order can achieve a high coverage in a short time as it guarantees running the important test case first.

Analog property checkers: a DDR2 case study

Abstract The formal specification component of verification can be exported to simulation through... more Abstract The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors.

Analog/mixed-signal circuit verification using models generated from simulation traces

Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining ... more Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining circuit models at suitable levels of abstraction. We propose a method to automatically generate abstract models suitable for formal verification and system-level simulation from transistor-level simulation traces. This paper discusses the application of the proposed methodology to a switched capacitor integrator and PLL phase detector.

Some “real world” problems in the analog and mixed signal domains

DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones Jaeha Kim,... more DCC 08 Some" Real World" Problems in the Analog and Mixed Signal Domains Kevin D Jones Jaeha Kim, Victor Konrad Slide 2 DCC 08 Abstract • Design and verification problems in the digital circuit space are well studied and there are many approaches to establishing correctness, both academic and industrial. However, the analog and mixed signal space is much less developed. • More and more systems are being designed with “mixed mode” functionality.

Larch: languages and tools for formal specification

Texts and Monographs …, Jan 1, 1993

Abstract Preface Building software often seems harder than it ought to be. It takes longerthan ex... more Abstract Preface Building software often seems harder than it ought to be. It takes longerthan expected, the software&amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;amp;#x27;s functionality and performance are not as wonderful as hoped, and the software is not particularly malleable or easyto maintain. It does not have to be that way. This book is about programming, and the role that formal specificationscan play in making programming easier and programs better. The intended audience is practicing programmers and students in undergraduate or basicgraduate courses in software engineering or ...