Papers by Christos Vagionas
WDM-enabled optical RAM architectures for ultra-fast, low-power optical cache memories
2013 15th International Conference on Transparent Optical Networks (ICTON), 2013
ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owe... more ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work on optical RAM cell configurations exploiting silicon-based integrated switching and latching elements with SOAs serving as the active devices. We review both their experimental and underlying theoretical framework and proceed with the demonstration of new optical cache architectural paradigms enabled by the introduction of WDM principles in the storage area. The higher than 40GHz optical RAM cell operational speeds and the WDM-enabled cache architectures comprise two major factors towards realizing ultra-fast and low-power CPU-memory communication.
Frequency and time domain analysis of all optical memories based on SOA and SOA-MZI switches
2014 Optical Interconnects Conference, 2014
ABSTRACT We investigate theoretically the maximum speed of high-speed optical RAM cell layouts re... more ABSTRACT We investigate theoretically the maximum speed of high-speed optical RAM cell layouts relying on SOA and SOA-MZI elements, based on a qualitative frequency and a quantitative time domain analysis.
All Optical Flip Flop with two Coupled Travelling Waveguide SOA-XGM Switches
Conference on Lasers and Electro-Optics 2012, 2012
ABSTRACT We demonstrate a novel optical SR-flip flop with simple architecture, employing only two... more ABSTRACT We demonstrate a novel optical SR-flip flop with simple architecture, employing only two SOA XGM switches. Proof-of-principle operation is experimentally demonstrated at 8 Mb/s and numerically evaluated at 10 Gb/s.
Multi-wavelength access gate for WDM-formatted words in optical RAM row architectures
Optical Components and Materials X, 2013
ABSTRACT Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of elec... more ABSTRACT Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOA-based multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multi-wavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bitchannels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.
Optical RAM and Flip-Flops Using Bit-Input Wavelength Diversity and SOA-XGM Switches
Journal of Lightwave Technology, 2000
ABSTRACT In this paper, we demonstrate a novel RAM cell based only on three traveling waveguide s... more ABSTRACT In this paper, we demonstrate a novel RAM cell based only on three traveling waveguide semiconductor optical amplifier-cross gain modulation (SOA-XGM) switches. The RAM cell features wavelength diversity in the incoming bit signals and provides Read/Write operation capability with true random access exclusively in the optical domain. Two of the SOA-XGM switches are coupled together through an 70/30 coupler to form an asynchronous flip-flop, which serves as the memory unit. Random access to the memory unit is granted by a third SOA-ON/OFF switch and all three SOAs together form the proposed RAM cell. Proof-of-principle operation is experimentally demonstrated at 8 Mb/s using commercial fiber-pigtailed components. The distinctive simplicity of the proposed RAM cell architecture suggests reduced footprint. The proposed flip-flop layout holds all the credentials for reaching multi-Gb/s operational speeds, if photonic integration technologies are employed to obtain wavelength-scale waveguides and ultrashort coupling lengths. This is numerically confirmed for 10 Gb/s using a simulation model based on the transfermatrix method and a wideband steady-state material gain coefficient.
Dual-Wavelength Bit Input Optical RAM With Three SOA-XGM Switches
IEEE Photonics Technology Letters, 2000
ABSTRACT We demonstrate a novel all-optical static RAM cell that exploits wavelength diversity in... more ABSTRACT We demonstrate a novel all-optical static RAM cell that exploits wavelength diversity in the incoming optical streams towards reducing the number of active elements. The circuit requires only three semiconductor optical amplifiers-cross gain modulation gates for successful read/write operation, yielding a 25% reduction in power consumption compared to state-of-the-art configurations. Proof-of-concept experimental verification is presented at 8 Mb/s using fiber-interconnected off-the-shelf bulk components.
Optical RAM cell with Dual-Wavelength Bit Input and three SOA XGM switches
National Fiber Optic Engineers Conference, 2012
ABSTRACT We experimentally demonstrate a novel optical static RAM cell that exploits wavelength d... more ABSTRACT We experimentally demonstrate a novel optical static RAM cell that exploits wavelength diversity in the incoming optical streams towards reducing the number of active elements, requiring only three SOA XGM gates for successful Read/Write operation.
XPM- and XGM-Based Optical RAM Memories: Frequency and Time Domain Theoretical Analysis
IEEE Journal of Quantum Electronics, 2014
ABSTRACT We demonstrate a frequency and time domain analysis for optical random access memory (RA... more ABSTRACT We demonstrate a frequency and time domain analysis for optical random access memory (RAM) cells that rely on semiconductor optical amplifier (SOA)-based switches but employ different switching mechanisms. The first RAM cell utilizes SOA cross gain modulation (XGM) switches both for the access gate as well as latching mechanism, whereas the second RAM cell configuration utilizes SOA-Mach-Zehnder interferometer cross phase modulation (XPM) switches. The frequency domain analysis exploits first-order perturbation theory approximations towards deriving the RAM cell frequency response, which is shown to exhibit in both RAM cell layouts a comb like resonant behavior. The free spectral range is dictated by the coupling length between the coupled switches that form the latching element, whereas the finesse depends on the temporal response of the switching mechanism employed. The qualitative speed and signal quality results obtained in the frequency domain are confirmed by a respective time-domain analysis carried out for both RAM cell layouts, using an experimentally validated time-domain SOA simulation model that relies on the transfer matrix method. Performance analysis in the time domain reveals in addition important quantitative RAM output signal measures like the extinction ratio and its dependence on the coupling length and the operational speed, as well as the input power dynamic range for successful RAM operation. Our holistic frequency- and time-domain analysis framework provides an in-depth understanding of performance-critical design parameters and their relationship to expected RAM cell performance characteristics. This is then utilized for a one-by-one system level comparison between the two RAM cell layouts in terms of readout extinction ratio, maximum speed, footprint, and power consumption concluding that the SOA-XGM-based RAM cell offers certain advantages when operational speeds not higher than 10 Gb/s are targeted, and the SOA-XPM-based RAM cell setup d- minating when higher RAM serial speeds even up to 40 GHz are targeted.
System level evaluation of optical RAM circuits based on cross coupled SOAs and SOA-MZIs in the time and frequency domain
2014 16th International Conference on Transparent Optical Networks (ICTON), 2014
ABSTRACT One of the key issues in Central Processing Unit (CPU) chips is the “Memory Wall” proble... more ABSTRACT One of the key issues in Central Processing Unit (CPU) chips is the “Memory Wall” problem, where the clock frequency of RAM circuits cannot keep up in pace with the clock of the multiple cores. The current approach by chip architects to tackle this obstacle is to increase constantly the size of the cache memories on the dye in order to prevent the cores standing in idle state, while expecting data from the RAM circuit. However, this solution is totally inefficient considering that the dye area of the chip is very precious and could be used alternative for the integration of additional cores, transceivers etc. that would radically enhance the performance of current CPUs. A disruptive solution for data storage within the chip is the introduction of optics in the processor layout by embedding photonic RAM circuits operating at multiple tens of GHz frequencies that would unleash the processing performance of CPU cores at high clock rates. In this direction we present a system level tool for the calculation of maximum obtainable speed from optical RAM cell layouts comprising of three cross coupled switches based on Semiconductor Optical Amplifiers (SOAs) or SOA based Mach-Zehnder interferometers. The investigation is based on a qualitative frequency and a quantitative time domain analysis.
Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures
Optical Interconnects XIV, 2014
ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owe... more ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
IEEE Photonics Journal, 2013
An optical RAM row access gate followed by a column address selector for wavelength-division-mult... more An optical RAM row access gate followed by a column address selector for wavelength-division-multiplexing (WDM)-formatted words employing a single semiconductor optical amplifierVMach-Zehnder interferometer (SOA-MZI) is presented. RAM row access is performed by the SOA-MZI that grants random access to a 4-bit WDM-formatted optical word employing multiwavelength cross-phase-modulation (XPM) phenomena, whereas column decoding is carried out in a completely passive way using arrayed waveguide grating. Proof-of-concept experimental verification for both positive and negative logic access is demonstrated for 4 Â 10 Gb/s optical words, showing error-free operation with only 0.4-dBpeak-power penalty and requiring a power value of 25 mW/Gb/s.
Compact and efficient silicon 2×2 switches based on a reverse biased vertical pn junction
11th International Conference on Group IV Photonics (GFP), 2014
ABSTRACT This paper focuses on the design and preliminary characterization of 2x2 Si-photonic swi... more ABSTRACT This paper focuses on the design and preliminary characterization of 2x2 Si-photonic switches embedded in a vertical pn junction. The device is optimized to achieve a full-π phase shift together with low insertion loss.
IEEE Photonics Journal, 2013
An optical RAM row access gate followed by a column address selector for wavelength-division-mult... more An optical RAM row access gate followed by a column address selector for wavelength-division-multiplexing (WDM)-formatted words employing a single semiconductor optical amplifierVMach-Zehnder interferometer (SOA-MZI) is presented. RAM row access is performed by the SOA-MZI that grants random access to a 4-bit WDM-formatted optical word employing multiwavelength cross-phase-modulation (XPM) phenomena, whereas column decoding is carried out in a completely passive way using arrayed waveguide grating. Proof-of-concept experimental verification for both positive and negative logic access is demonstrated for 4 Â 10 Gb/s optical words, showing error-free operation with only 0.4-dBpeak-power penalty and requiring a power value of 25 mW/Gb/s.
Optical RAM Row Access and Column Decoding for WDM-formatted optical words
Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2013, 2013
ABSTRACT We present a multi-wavelength SOA-MZI-based access gate and an AWG-based column decoder ... more ABSTRACT We present a multi-wavelength SOA-MZI-based access gate and an AWG-based column decoder that control random access of 4x10Gb/s WDM-formatted words into a 4-bit optical RAM row. Error-free decoding with 0.4dB peak power penalty is presented.
Fabrication of modulators and 2×2 switches in SOI based on the carrier depletion mechanism for optical interconnects
Optical Interconnects XIV, 2014
ABSTRACT Silicon-photonic 2×2 electro-optical switching elements and modulators based on the carr... more ABSTRACT Silicon-photonic 2×2 electro-optical switching elements and modulators based on the carrier depletion mechanism using both dual-resonator and MZI layout configurations have been developed. The passive photonic structures were developed and optimized using a fast design-fabrication-characterization cycle. The main objective is to deliver smallfootprint, low-loss and low-energy silicon photonic electro-optical switching elements and modulators equipped with standard input-output grating couplers and radio-frequency electrical contact tips to allow their characterization in highspeed probe-station setups. The insertion losses, crosstalk, power consumption and BER performance will be addressed for each electro-optical structure. The fabrication steps, including low loss waveguide patterning, pn junction and low resistive ohmic contact formation have been optimized to produce high performance devices with relaxed fabrication tolerances, employing both optical and electron-beam lithography.
Dual-Wavelength Bit Input Optical RAM With Three SOA-XGM Switches
IEEE Photonics Technology Letters, 2012
We demonstrate a novel all-optical static RAM cell that exploits wavelength diversity in the inco... more We demonstrate a novel all-optical static RAM cell that exploits wavelength diversity in the incoming optical streams towards reducing the number of active elements. The circuit requires only three semiconductor optical amplifiers-cross gain modulation gates for successful read/write operation, yielding a 25% reduction in power consumption compared to state-of-the-art configurations. Proof-of-concept experimental verification is presented at 8 Mb/s using fiber-interconnected off-the-shelf bulk components.
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Papers by Christos Vagionas