This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce... more This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 d...
This manuscript presents the design of a low phase noise, high figure of merit (FoM) single-ended... more This manuscript presents the design of a low phase noise, high figure of merit (FoM) single-ended octagonal ring oscillator (RO). The proposed RO employs the pulse injection (PI) technique for performance enhancement. The PI technique is used for suppression of phase noise and spurious harmonics. Besides, a novel voltage dependent phase shifter is employed. The proposed RO has an output signal with voltage controlled phase. Different output signal phases can be obtained employing different selected voltages to control the output signal phase. The proposed injection locked ring oscillator (ILRO) represents a suitable implementation for phase shift keying. The proposed ILRO has a measured oscillation frequency of 4.9 GHz with a fine tuning range of 500 MHz. It has a measured phase noise of 2126.17 dBc/Hz @ 1MHz offset while consuming only 4.8 mW of DC power. The proposed ILRO has a FoM of 2193.17 dBc/Hz. This RO has been designed and implemented in 0.18 mm CMOS technology. V
ABSTRACT This paper presents a novel design of a ring oscillator (RO) producing eight phases outp... more ABSTRACT This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of -131.5 dBc/Hz @1MHz offset and FoM of -199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
2019 International Conference on Innovative Trends in Computer Engineering (ITCE), 2019
This paper presents a proposed design procedure of a Wireless Power Transfer (WPT) system based o... more This paper presents a proposed design procedure of a Wireless Power Transfer (WPT) system based on high efficiency offset reflector antennas fed by conical horns. The system’s performance evaluation is also demonstrated. The antennas in the transmitter and receiver sides of the proposed WPT system are symmetric. The performance of the system is optimized by calibrating the feeding horns and the offset reflector’s dimensions to minimize the path and reflection losses of the proposed WPT system. The results show that correct line of sight alignment of the transmitter and receiver enhances the efficiency of the system. With an operating frequency of 6 GHz and 1 W of power transfer over a distance of 12 m between the transmitter and receiver, the system attains a total transfer efficiency of 62.9 %.
2013 Second International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC), 2013
ABSTRACT This paper presents the design of an ultra wideband low noise amplifier (UWB LNA). The p... more ABSTRACT This paper presents the design of an ultra wideband low noise amplifier (UWB LNA). The proposed UWB LNA employs common gate and common source stages configured as a current reuse topology. The UWB LNA has a maximum gain of 14 dB with minimum NF of 3.0 dB. Good input and output impedance matching are achieved over the operating frequency band. The proposed UWB LNA consumes only 2.0 mW from a 0.9V power supply. This UWB LNA is designed and simulated in the standard 0.18 μm CMOS technology.
2019 7th International Japan-Africa Conference on Electronics, Communications, and Computations, (JAC-ECC)
This paper presents a CMOS mixer with excellent input matching and high conversion gain @ 2.4 GHz... more This paper presents a CMOS mixer with excellent input matching and high conversion gain @ 2.4 GHz. Inductive source degeneration is used for RF port input matching. This mixer utilizes inductive shunt peaking for conversion gain boosting. Active loads having drain-gate AC resistive blocking devices are employed for further enhancement of IF output power. The proposed mixer is designed, simulated and implemented in TSMC 0.18 μm CMOS process. This mixer layout occupies an active area of 0.293 mm2. Its input matching network is tuned to 2.4 GHz. It achieves a conversion gain of 31.88 dB while driving a 3.43 mA from a 1.8V supply. It has a FoM of 13.321.
2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC), 2017
This paper presents the design of low phase noise, high figure of merit (FoM), and low power inje... more This paper presents the design of low phase noise, high figure of merit (FoM), and low power injection locked ring oscillator (ILRO) in 0.18 μm CMOS technology. Edge injection technique has been adopted for ring oscillator (RO) phase noise suppression and performance enhancement. Edge injection helps improving the oscillator jitter performance while maintaining spurious harmonics minimized. In addition, implementing the proposed RO using identical NAND delay stages simplifies the design and improves frequency oscillation adjustment. The proposed injection locked oscillator (ILO) has an oscillation frequency of 3.3 GHz with fine tuning range of 400 MHz. This ILO achieves a phase noise of −120.2 dBc/Hz at 1 MHz offset. It consumes only 4.4 mW from a 1.8 V DC power source. The proposed ILRO can achieve a FoM of −184.1 dBc/Hz.
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
A CMOS mixer with wideband input impedance matching and high conversion gain is presented in this... more A CMOS mixer with wideband input impedance matching and high conversion gain is presented in this paper. Dual RLC circuits are utilized with Gilbert mixer for wideband input matching. Capacitive feedback, and inductive series and shunt peaking techniques, are used to implement the RF port matching network. Inductive peaking is also adopted to widen the 3-dB conversion gain bandwidth. Active load with AC resistive blocking is employed to boost the mixer conversion gain. The proposed circuit is designed, simulated and implemented in XFAB XH018 process with VDD of 1.8V. It achieves a very good RF matching over a band of 5.6–14.6GHz, with a conversion gain of 25.0–28.2dB over the desired band of frequency.
IEEE Transactions on Circuits and Systems II: Express Briefs
This brief presents the design of an ultra-low power level-crossing analog-to-digital converter (... more This brief presents the design of an ultra-low power level-crossing analog-to-digital converter (LC-ADC) for IoT and biomedical applications. The proposed LC-ADC utilizes only one multi-level comparator instead of multiple comparators as in conventional LC-ADC, leading to simplified implementation and significant reduction in power. Implemented in 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu}\text{m}$ </tex-math></inline-formula> CMOS process, the LC-ADC achieves 7.9 equivalent number of bits with a 49 dB signal-to-noise and distortion ratio at the input frequency up to 1 kHz. The measured minimum power is only 4.2 nW at the supply voltage of 0.55 V.
IEEE Transactions on Circuits and Systems II: Express Briefs
An ultra-low-power level-crossing analog-to-digital converter (LC-ADC) with on-chip adaptive samp... more An ultra-low-power level-crossing analog-to-digital converter (LC-ADC) with on-chip adaptive sampling is presented. Different from conventional ADCs based on Nyquist sampling, LC-ADC utilizes sparsity of signals for low power data acquisition. To save power, the proposed adaptive sampling scheme is implemented with only one scaler and one high-precision comparator, which is in sharp contrast to conventional LC-ADCs that require an n-bit digital-to-analog converter and two comparators. Implemented in 0.18- $\mu {\mathrm{ m}}$ CMOS process, the proposed ADC consumes only 61 nW under 0.5V supply, and achieves 5.6 bits equivalent numbers of bits and 35 dB signal-to-noise and distortion ratio with an operating frequency up to 1 kHz.
IEEE Transactions on Circuits and Systems II: Express Briefs
The proposed digital phase locked loop uses a time-to-digital converter with associated simple al... more The proposed digital phase locked loop uses a time-to-digital converter with associated simple algorithm to improve jitter performance. The wide frequency tuning is achieved through three different loop delay control schemes of the digital controlled oscillator (DCO). Verified in GLOBALFOUNDRIES 55 nm LPX process, the chip occupies 0.0129 mm2, achieves a wide range of 250 MHz to 2.7 GHz, and consumes only 1.1 mW when DCO’s frequency is 500 MHz. The phase locked loop output clock jitter is around 1.6–2.0 ps.
This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay var... more This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay variations and optimized noise performance for ultra-wideband (UWB) applications. The proposed LNA employs a common source based current reuse topology. Through this configuration gain flatness of 12.25± 0.25 with noise figure (NF) less than 3.8 dB are achieved. This LNA achieves group delay variation of ±25 ps using the standard 0.18 µm CMOS technology. Weak Capacitive-Resistive shunt feedback technique is implemented across the input stage for wideband input matching. Series peaking with output resistive termination are adopted for group delay variations optimization. This UWB LNA has a measured 1dB compression point (P1dB) and an input third-order intermodulation point (IIP3) of -7.0 dBm and 2.5 dBm respectively at 5.5 GHz. The implemented UWB LNA chip area is only 560 µm x 590 µm.
This paper presents the design of a 2-16 GHz ultra wideband low noise amplifier (UWB LNA). The pr... more This paper presents the design of a 2-16 GHz ultra wideband low noise amplifier (UWB LNA). The proposed UWB LNA employs a symmetric 3D RF integrated inductor. The UWB LNA has a gain of 11 ± 1.0 dB with NF less than 3.25 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8V supply. This UWB LNA is designed and simulated in the standard 0.18 μm CMOS technology.
2014 IEEE International Conference on Ultra-WideBand (ICUWB), 2014
This paper presents the design of a low DC power, low phase noise single-ended ring oscillator (R... more This paper presents the design of a low DC power, low phase noise single-ended ring oscillator (RO) in 0.18 µm CMOS technology. It introduces a new RO output phase control technique. This RO uses a voltage pull-down circuit to produce different output signal phases. The proposed RO employs the pulse injection (PI) technique for phase noise and spurious signals suppression. The proposed injection locked ring oscillator (ILRO) can be used for phase shift keying (PSK) implementation. The proposed ILRO has an oscillation frequency of 4.5 GHz with a fine tuning range of 540 MHz. It consumes only a 4.25 mW of power while having a phase noise of -130.9 dBc/Hz @ 1MHz offset. Through this ILRO design, a figure of merit (FoM) of -197.68 dBc/Hz has been achieved.
2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014
This paper presents the design of a simple multiphase ring oscillator (RO). It represents a new t... more This paper presents the design of a simple multiphase ring oscillator (RO). It represents a new technique for RO output signal phase control. This RO uses a voltage injection principle to produce different phases output signal. The proposed RO consumes only 3.6 mW from a 1.8V power supply while having an oscillation frequency of 5.5 GHz with a 330 MHz fine tuning range. This RO is employing the pulse injection technique for phase noise enhancement. It has a phase noise less than -133.5 dBc/Hz @ 1 MHz offset. It achieves a figure of merit (FoM) of -182.75 dBc/Hz .This RO is designed and simulated in the standard 0.18 μm CMOS technology.
International Journal of Microwave Science and Technology, 2013
This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB ... more This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.
ABSTRACT This paper discusses the design of 3D monolithic integrated inductors. The proposed 3D r... more ABSTRACT This paper discusses the design of 3D monolithic integrated inductors. The proposed 3D radio frequency (RF) integrated inductors have high inductance (L) values with an enhanced quality factors (Q). A new proposed method for 3D integrated inductors design is presented. A wide range of inductances and quality factor values can be realized. The proposed 3D inductors were designed in TSMC 0.18 µm technology and simulated using momentum.
This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The p... more This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The proposed LNA has a gain of 11.5 ± 0.85 dB with NF less than 2.82 dB. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The proposed UWB LNA consumes 18.14 mW of power from 1.8V supply. This UWB LNA is designed and simulated in 0.18 µm CMOS process.
This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce... more This paper presents an injection locked digitally controlled ring oscillator (IL-DCRO). To reduce jitter variations, minimize oscillator spurious signals, and eliminate periodical phase error, a double edge-injection (window injection) scheme with synchronized edge directions is proposed. A combinational edge generator is utilized to substitute the sequential edge generators for injection timing requirements relaxation. By biasing devices in deep triode, digitally controlled delay cells currents are adopted for frequency tuning. This helps reducing the devices flicker (1/f) noise and minimize the DCRO overall phase noise. At 1 MHz offset of frequency, the proposed oscillator has a measured phase noise of −125.95 dBc/Hz and −115.6 dBc/Hz at oscillation frequencies of 913.4 MHz and 432.6 MHz, respectively. Fabricated in 350 nm CMOS process, with a maximum power consumption of 3.3 mW, and oscillating at 913.4 MHz, this DCRO achieves a tuned oscillator figure of merit (FoM) of −197.35 d...
This manuscript presents the design of a low phase noise, high figure of merit (FoM) single-ended... more This manuscript presents the design of a low phase noise, high figure of merit (FoM) single-ended octagonal ring oscillator (RO). The proposed RO employs the pulse injection (PI) technique for performance enhancement. The PI technique is used for suppression of phase noise and spurious harmonics. Besides, a novel voltage dependent phase shifter is employed. The proposed RO has an output signal with voltage controlled phase. Different output signal phases can be obtained employing different selected voltages to control the output signal phase. The proposed injection locked ring oscillator (ILRO) represents a suitable implementation for phase shift keying. The proposed ILRO has a measured oscillation frequency of 4.9 GHz with a fine tuning range of 500 MHz. It has a measured phase noise of 2126.17 dBc/Hz @ 1MHz offset while consuming only 4.8 mW of DC power. The proposed ILRO has a FoM of 2193.17 dBc/Hz. This RO has been designed and implemented in 0.18 mm CMOS technology. V
ABSTRACT This paper presents a novel design of a ring oscillator (RO) producing eight phases outp... more ABSTRACT This paper presents a novel design of a ring oscillator (RO) producing eight phases output with accurate signal phase adjustment. By using the pulse injection technique, the RO phase noise has been strongly suppressed. In addition, a novel phase control technique is proposed for the implementation of the phase modulation. The proposed RO achieves a phase noise of -131.5 dBc/Hz @1MHz offset and FoM of -199.25 dBc/Hz. This RO consumes a 3.4 mW of power from a 1.8V power supply while having an oscillation frequency of 4.5 GHz and a locking range of 540 MHz in CMOS 0.18 um technology.
2019 International Conference on Innovative Trends in Computer Engineering (ITCE), 2019
This paper presents a proposed design procedure of a Wireless Power Transfer (WPT) system based o... more This paper presents a proposed design procedure of a Wireless Power Transfer (WPT) system based on high efficiency offset reflector antennas fed by conical horns. The system’s performance evaluation is also demonstrated. The antennas in the transmitter and receiver sides of the proposed WPT system are symmetric. The performance of the system is optimized by calibrating the feeding horns and the offset reflector’s dimensions to minimize the path and reflection losses of the proposed WPT system. The results show that correct line of sight alignment of the transmitter and receiver enhances the efficiency of the system. With an operating frequency of 6 GHz and 1 W of power transfer over a distance of 12 m between the transmitter and receiver, the system attains a total transfer efficiency of 62.9 %.
2013 Second International Japan-Egypt Conference on Electronics, Communications and Computers (JEC-ECC), 2013
ABSTRACT This paper presents the design of an ultra wideband low noise amplifier (UWB LNA). The p... more ABSTRACT This paper presents the design of an ultra wideband low noise amplifier (UWB LNA). The proposed UWB LNA employs common gate and common source stages configured as a current reuse topology. The UWB LNA has a maximum gain of 14 dB with minimum NF of 3.0 dB. Good input and output impedance matching are achieved over the operating frequency band. The proposed UWB LNA consumes only 2.0 mW from a 0.9V power supply. This UWB LNA is designed and simulated in the standard 0.18 μm CMOS technology.
2019 7th International Japan-Africa Conference on Electronics, Communications, and Computations, (JAC-ECC)
This paper presents a CMOS mixer with excellent input matching and high conversion gain @ 2.4 GHz... more This paper presents a CMOS mixer with excellent input matching and high conversion gain @ 2.4 GHz. Inductive source degeneration is used for RF port input matching. This mixer utilizes inductive shunt peaking for conversion gain boosting. Active loads having drain-gate AC resistive blocking devices are employed for further enhancement of IF output power. The proposed mixer is designed, simulated and implemented in TSMC 0.18 μm CMOS process. This mixer layout occupies an active area of 0.293 mm2. Its input matching network is tuned to 2.4 GHz. It achieves a conversion gain of 31.88 dB while driving a 3.43 mA from a 1.8V supply. It has a FoM of 13.321.
2017 Japan-Africa Conference on Electronics, Communications and Computers (JAC-ECC), 2017
This paper presents the design of low phase noise, high figure of merit (FoM), and low power inje... more This paper presents the design of low phase noise, high figure of merit (FoM), and low power injection locked ring oscillator (ILRO) in 0.18 μm CMOS technology. Edge injection technique has been adopted for ring oscillator (RO) phase noise suppression and performance enhancement. Edge injection helps improving the oscillator jitter performance while maintaining spurious harmonics minimized. In addition, implementing the proposed RO using identical NAND delay stages simplifies the design and improves frequency oscillation adjustment. The proposed injection locked oscillator (ILO) has an oscillation frequency of 3.3 GHz with fine tuning range of 400 MHz. This ILO achieves a phase noise of −120.2 dBc/Hz at 1 MHz offset. It consumes only 4.4 mW from a 1.8 V DC power source. The proposed ILRO can achieve a FoM of −184.1 dBc/Hz.
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
A CMOS mixer with wideband input impedance matching and high conversion gain is presented in this... more A CMOS mixer with wideband input impedance matching and high conversion gain is presented in this paper. Dual RLC circuits are utilized with Gilbert mixer for wideband input matching. Capacitive feedback, and inductive series and shunt peaking techniques, are used to implement the RF port matching network. Inductive peaking is also adopted to widen the 3-dB conversion gain bandwidth. Active load with AC resistive blocking is employed to boost the mixer conversion gain. The proposed circuit is designed, simulated and implemented in XFAB XH018 process with VDD of 1.8V. It achieves a very good RF matching over a band of 5.6–14.6GHz, with a conversion gain of 25.0–28.2dB over the desired band of frequency.
IEEE Transactions on Circuits and Systems II: Express Briefs
This brief presents the design of an ultra-low power level-crossing analog-to-digital converter (... more This brief presents the design of an ultra-low power level-crossing analog-to-digital converter (LC-ADC) for IoT and biomedical applications. The proposed LC-ADC utilizes only one multi-level comparator instead of multiple comparators as in conventional LC-ADC, leading to simplified implementation and significant reduction in power. Implemented in 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu}\text{m}$ </tex-math></inline-formula> CMOS process, the LC-ADC achieves 7.9 equivalent number of bits with a 49 dB signal-to-noise and distortion ratio at the input frequency up to 1 kHz. The measured minimum power is only 4.2 nW at the supply voltage of 0.55 V.
IEEE Transactions on Circuits and Systems II: Express Briefs
An ultra-low-power level-crossing analog-to-digital converter (LC-ADC) with on-chip adaptive samp... more An ultra-low-power level-crossing analog-to-digital converter (LC-ADC) with on-chip adaptive sampling is presented. Different from conventional ADCs based on Nyquist sampling, LC-ADC utilizes sparsity of signals for low power data acquisition. To save power, the proposed adaptive sampling scheme is implemented with only one scaler and one high-precision comparator, which is in sharp contrast to conventional LC-ADCs that require an n-bit digital-to-analog converter and two comparators. Implemented in 0.18- $\mu {\mathrm{ m}}$ CMOS process, the proposed ADC consumes only 61 nW under 0.5V supply, and achieves 5.6 bits equivalent numbers of bits and 35 dB signal-to-noise and distortion ratio with an operating frequency up to 1 kHz.
IEEE Transactions on Circuits and Systems II: Express Briefs
The proposed digital phase locked loop uses a time-to-digital converter with associated simple al... more The proposed digital phase locked loop uses a time-to-digital converter with associated simple algorithm to improve jitter performance. The wide frequency tuning is achieved through three different loop delay control schemes of the digital controlled oscillator (DCO). Verified in GLOBALFOUNDRIES 55 nm LPX process, the chip occupies 0.0129 mm2, achieves a wide range of 250 MHz to 2.7 GHz, and consumes only 1.1 mW when DCO’s frequency is 500 MHz. The phase locked loop output clock jitter is around 1.6–2.0 ps.
This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay var... more This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay variations and optimized noise performance for ultra-wideband (UWB) applications. The proposed LNA employs a common source based current reuse topology. Through this configuration gain flatness of 12.25± 0.25 with noise figure (NF) less than 3.8 dB are achieved. This LNA achieves group delay variation of ±25 ps using the standard 0.18 µm CMOS technology. Weak Capacitive-Resistive shunt feedback technique is implemented across the input stage for wideband input matching. Series peaking with output resistive termination are adopted for group delay variations optimization. This UWB LNA has a measured 1dB compression point (P1dB) and an input third-order intermodulation point (IIP3) of -7.0 dBm and 2.5 dBm respectively at 5.5 GHz. The implemented UWB LNA chip area is only 560 µm x 590 µm.
This paper presents the design of a 2-16 GHz ultra wideband low noise amplifier (UWB LNA). The pr... more This paper presents the design of a 2-16 GHz ultra wideband low noise amplifier (UWB LNA). The proposed UWB LNA employs a symmetric 3D RF integrated inductor. The UWB LNA has a gain of 11 ± 1.0 dB with NF less than 3.25 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8V supply. This UWB LNA is designed and simulated in the standard 0.18 μm CMOS technology.
2014 IEEE International Conference on Ultra-WideBand (ICUWB), 2014
This paper presents the design of a low DC power, low phase noise single-ended ring oscillator (R... more This paper presents the design of a low DC power, low phase noise single-ended ring oscillator (RO) in 0.18 µm CMOS technology. It introduces a new RO output phase control technique. This RO uses a voltage pull-down circuit to produce different output signal phases. The proposed RO employs the pulse injection (PI) technique for phase noise and spurious signals suppression. The proposed injection locked ring oscillator (ILRO) can be used for phase shift keying (PSK) implementation. The proposed ILRO has an oscillation frequency of 4.5 GHz with a fine tuning range of 540 MHz. It consumes only a 4.25 mW of power while having a phase noise of -130.9 dBc/Hz @ 1MHz offset. Through this ILRO design, a figure of merit (FoM) of -197.68 dBc/Hz has been achieved.
2014 International Conference on Information Science, Electronics and Electrical Engineering, 2014
This paper presents the design of a simple multiphase ring oscillator (RO). It represents a new t... more This paper presents the design of a simple multiphase ring oscillator (RO). It represents a new technique for RO output signal phase control. This RO uses a voltage injection principle to produce different phases output signal. The proposed RO consumes only 3.6 mW from a 1.8V power supply while having an oscillation frequency of 5.5 GHz with a 330 MHz fine tuning range. This RO is employing the pulse injection technique for phase noise enhancement. It has a phase noise less than -133.5 dBc/Hz @ 1 MHz offset. It achieves a figure of merit (FoM) of -182.75 dBc/Hz .This RO is designed and simulated in the standard 0.18 μm CMOS technology.
International Journal of Microwave Science and Technology, 2013
This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB ... more This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.
ABSTRACT This paper discusses the design of 3D monolithic integrated inductors. The proposed 3D r... more ABSTRACT This paper discusses the design of 3D monolithic integrated inductors. The proposed 3D radio frequency (RF) integrated inductors have high inductance (L) values with an enhanced quality factors (Q). A new proposed method for 3D integrated inductors design is presented. A wide range of inductances and quality factor values can be realized. The proposed 3D inductors were designed in TSMC 0.18 µm technology and simulated using momentum.
This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The p... more This paper presents the design of a 2-16 GHz ultra wide band low noise amplifier (UWB LNA). The proposed LNA has a gain of 11.5 ± 0.85 dB with NF less than 2.82 dB. Good input and output impedance matching, good isolation and linearity are achieved over the operating frequency band. The proposed UWB LNA consumes 18.14 mW of power from 1.8V supply. This UWB LNA is designed and simulated in 0.18 µm CMOS process.
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Papers by Khalil Yousef