{"id":"https:\/\/openalex.org\/W4386765302","doi":"https:\/\/doi.org\/10.1109\/dac56929.2023.10247681","title":"PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration","display_name":"PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration","publication_year":2023,"publication_date":"2023-07-09","ids":{"openalex":"https:\/\/openalex.org\/W4386765302","doi":"https:\/\/doi.org\/10.1109\/dac56929.2023.10247681"},"language":"en","primary_location":{"id":"doi:10.1109\/dac56929.2023.10247681","is_oa":false,"landing_page_url":"https:\/\/doi.org\/10.1109\/dac56929.2023.10247681","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 60th ACM\/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https:\/\/openalex.org\/A5087812675","display_name":"Zhijie Cai","orcid":"https:\/\/orcid.org\/0009-0001-9035-9599"},"institutions":[{"id":"https:\/\/openalex.org\/I24943067","display_name":"Fudan University","ror":"https:\/\/ror.org\/013q1eq08","country_code":"CN","type":"education","lineage":["https:\/\/openalex.org\/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhijie Cai","raw_affiliation_strings":["Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433","institution_ids":["https:\/\/openalex.org\/I24943067"]}]},{"author_position":"middle","author":{"id":"https:\/\/openalex.org\/A5002478857","display_name":"Peng Zou","orcid":"https:\/\/orcid.org\/0000-0002-8345-0976"},"institutions":[{"id":"https:\/\/openalex.org\/I24943067","display_name":"Fudan University","ror":"https:\/\/ror.org\/013q1eq08","country_code":"CN","type":"education","lineage":["https:\/\/openalex.org\/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Zou","raw_affiliation_strings":["Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433","institution_ids":["https:\/\/openalex.org\/I24943067"]}]},{"author_position":"middle","author":{"id":"https:\/\/openalex.org\/A5055076603","display_name":"Zhengtao Wu","orcid":"https:\/\/orcid.org\/0000-0001-8199-7225"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zhengtao Wu","raw_affiliation_strings":["Shanghai LEDA Technology Co., Ltd,Shanghai,China,201203"],"affiliations":[{"raw_affiliation_string":"Shanghai LEDA Technology Co., Ltd,Shanghai,China,201203","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https:\/\/openalex.org\/A5066750673","display_name":"Xingyu Tong","orcid":"https:\/\/orcid.org\/0000-0001-9057-9172"},"institutions":[{"id":"https:\/\/openalex.org\/I24943067","display_name":"Fudan University","ror":"https:\/\/ror.org\/013q1eq08","country_code":"CN","type":"education","lineage":["https:\/\/openalex.org\/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xingyu Tong","raw_affiliation_strings":["Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433","institution_ids":["https:\/\/openalex.org\/I24943067"]}]},{"author_position":"middle","author":{"id":"https:\/\/openalex.org\/A5103098516","display_name":"Jun Yu","orcid":"https:\/\/orcid.org\/0000-0003-4286-9292"},"institutions":[{"id":"https:\/\/openalex.org\/I24943067","display_name":"Fudan University","ror":"https:\/\/ror.org\/013q1eq08","country_code":"CN","type":"education","lineage":["https:\/\/openalex.org\/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Yu","raw_affiliation_strings":["Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433","institution_ids":["https:\/\/openalex.org\/I24943067"]}]},{"author_position":"middle","author":{"id":"https:\/\/openalex.org\/A5101854580","display_name":"Jianli Chen","orcid":"https:\/\/orcid.org\/0000-0002-1391-2696"},"institutions":[{"id":"https:\/\/openalex.org\/I24943067","display_name":"Fudan University","ror":"https:\/\/ror.org\/013q1eq08","country_code":"CN","type":"education","lineage":["https:\/\/openalex.org\/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianli Chen","raw_affiliation_strings":["Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433"],"affiliations":[{"raw_affiliation_string":"Fudan University,State Key Lab of ASIC &#x0026; System,Shanghai,China,200433","institution_ids":["https:\/\/openalex.org\/I24943067"]}]},{"author_position":"last","author":{"id":"https:\/\/openalex.org\/A5018371636","display_name":"Yao\u2010Wen Chang","orcid":"https:\/\/orcid.org\/0000-0002-0564-5719"},"institutions":[{"id":"https:\/\/openalex.org\/I16733864","display_name":"National Taiwan University","ror":"https:\/\/ror.org\/05bqach95","country_code":"TW","type":"education","lineage":["https:\/\/openalex.org\/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yao-Wen Chang","raw_affiliation_strings":["National Taiwan University,Graduate Institute of Electronics Engineering,Taipei,Taiwan,10617","Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"affiliations":[{"raw_affiliation_string":"National Taiwan University,Graduate Institute of Electronics Engineering,Taipei,Taiwan,10617","institution_ids":["https:\/\/openalex.org\/I16733864"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https:\/\/openalex.org\/I16733864"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":7,"corresponding_author_ids":["https:\/\/openalex.org\/A5087812675"],"corresponding_institution_ids":["https:\/\/openalex.org\/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.6521,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68564973,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https:\/\/openalex.org\/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998999834060669,"subfield":{"id":"https:\/\/openalex.org\/subfields\/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https:\/\/openalex.org\/fields\/22","display_name":"Engineering"},"domain":{"id":"https:\/\/openalex.org\/domains\/3","display_name":"Physical Sciences"}},"topics":[{"id":"https:\/\/openalex.org\/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9998999834060669,"subfield":{"id":"https:\/\/openalex.org\/subfields\/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https:\/\/openalex.org\/fields\/22","display_name":"Engineering"},"domain":{"id":"https:\/\/openalex.org\/domains\/3","display_name":"Physical Sciences"}},{"id":"https:\/\/openalex.org\/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https:\/\/openalex.org\/subfields\/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https:\/\/openalex.org\/fields\/22","display_name":"Engineering"},"domain":{"id":"https:\/\/openalex.org\/domains\/3","display_name":"Physical Sciences"}},{"id":"https:\/\/openalex.org\/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9986000061035156,"subfield":{"id":"https:\/\/openalex.org\/subfields\/1708","display_name":"Hardware and Architecture"},"field":{"id":"https:\/\/openalex.org\/fields\/17","display_name":"Computer Science"},"domain":{"id":"https:\/\/openalex.org\/domains\/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https:\/\/openalex.org\/keywords\/padding","display_name":"Padding","score":0.8518736362457275},{"id":"https:\/\/openalex.org\/keywords\/computer-science","display_name":"Computer science","score":0.6927394270896912},{"id":"https:\/\/openalex.org\/keywords\/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.65086829662323},{"id":"https:\/\/openalex.org\/keywords\/routing","display_name":"Routing (electronic design automation)","score":0.6475461721420288},{"id":"https:\/\/openalex.org\/keywords\/speedup","display_name":"Speedup","score":0.6115292310714722},{"id":"https:\/\/openalex.org\/keywords\/placement","display_name":"Placement","score":0.5252686738967896},{"id":"https:\/\/openalex.org\/keywords\/process","display_name":"Process (computing)","score":0.4812602698802948},{"id":"https:\/\/openalex.org\/keywords\/physical-design","display_name":"Physical design","score":0.4539754390716553},{"id":"https:\/\/openalex.org\/keywords\/convolutional-neural-network","display_name":"Convolutional neural network","score":0.43728041648864746},{"id":"https:\/\/openalex.org\/keywords\/prioritization","display_name":"Prioritization","score":0.43624719977378845},{"id":"https:\/\/openalex.org\/keywords\/parallel-computing","display_name":"Parallel computing","score":0.3616500496864319},{"id":"https:\/\/openalex.org\/keywords\/computer-architecture","display_name":"Computer architecture","score":0.360588014125824},{"id":"https:\/\/openalex.org\/keywords\/computer-engineering","display_name":"Computer engineering","score":0.35298898816108704},{"id":"https:\/\/openalex.org\/keywords\/artificial-intelligence","display_name":"Artificial intelligence","score":0.2654733657836914},{"id":"https:\/\/openalex.org\/keywords\/embedded-system","display_name":"Embedded system","score":0.2279377281665802},{"id":"https:\/\/openalex.org\/keywords\/engineering","display_name":"Engineering","score":0.178335040807724},{"id":"https:\/\/openalex.org\/keywords\/circuit-design","display_name":"Circuit design","score":0.08696487545967102}],"concepts":[{"id":"https:\/\/openalex.org\/C165435473","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q1509884","display_name":"Padding","level":2,"score":0.8518736362457275},{"id":"https:\/\/openalex.org\/C41008148","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q21198","display_name":"Computer science","level":0,"score":0.6927394270896912},{"id":"https:\/\/openalex.org\/C14580979","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.65086829662323},{"id":"https:\/\/openalex.org\/C74172769","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6475461721420288},{"id":"https:\/\/openalex.org\/C68339613","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q1549489","display_name":"Speedup","level":2,"score":0.6115292310714722},{"id":"https:\/\/openalex.org\/C117690923","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q1484784","display_name":"Placement","level":4,"score":0.5252686738967896},{"id":"https:\/\/openalex.org\/C98045186","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q205663","display_name":"Process (computing)","level":2,"score":0.4812602698802948},{"id":"https:\/\/openalex.org\/C188817802","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q13426855","display_name":"Physical design","level":3,"score":0.4539754390716553},{"id":"https:\/\/openalex.org\/C81363708","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q17084460","display_name":"Convolutional neural network","level":2,"score":0.43728041648864746},{"id":"https:\/\/openalex.org\/C2777615720","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q11888847","display_name":"Prioritization","level":2,"score":0.43624719977378845},{"id":"https:\/\/openalex.org\/C173608175","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q232661","display_name":"Parallel computing","level":1,"score":0.3616500496864319},{"id":"https:\/\/openalex.org\/C118524514","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q173212","display_name":"Computer architecture","level":1,"score":0.360588014125824},{"id":"https:\/\/openalex.org\/C113775141","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q428691","display_name":"Computer engineering","level":1,"score":0.35298898816108704},{"id":"https:\/\/openalex.org\/C154945302","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q11660","display_name":"Artificial intelligence","level":1,"score":0.2654733657836914},{"id":"https:\/\/openalex.org\/C149635348","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q193040","display_name":"Embedded system","level":1,"score":0.2279377281665802},{"id":"https:\/\/openalex.org\/C127413603","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q11023","display_name":"Engineering","level":0,"score":0.178335040807724},{"id":"https:\/\/openalex.org\/C190560348","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q3245116","display_name":"Circuit design","level":2,"score":0.08696487545967102},{"id":"https:\/\/openalex.org\/C539667460","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q2414942","display_name":"Management science","level":1,"score":0},{"id":"https:\/\/openalex.org\/C38652104","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q3510521","display_name":"Computer security","level":1,"score":0},{"id":"https:\/\/openalex.org\/C111919701","wikidata":"https:\/\/www.wikidata.org\/wiki\/Q9135","display_name":"Operating system","level":1,"score":0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109\/dac56929.2023.10247681","is_oa":false,"landing_page_url":"https:\/\/doi.org\/10.1109\/dac56929.2023.10247681","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 60th ACM\/IEEE Design Automation Conference (DAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https:\/\/metadata.un.org\/sdg\/9","score":0.6600000262260437}],"awards":[],"funders":[{"id":"https:\/\/openalex.org\/F4320307110","display_name":"Delta","ror":"https:\/\/ror.org\/03g9c1e75"},{"id":"https:\/\/openalex.org\/F4320317160","display_name":"AnaGlobe","ror":null},{"id":"https:\/\/openalex.org\/F4320337504","display_name":"Research and Development","ror":"https:\/\/ror.org\/027s68j25"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https:\/\/openalex.org\/W1967661769","https:\/\/openalex.org\/W1985292881","https:\/\/openalex.org\/W2020461489","https:\/\/openalex.org\/W2031974129","https:\/\/openalex.org\/W2033570891","https:\/\/openalex.org\/W2106411961","https:\/\/openalex.org\/W2117278010","https:\/\/openalex.org\/W2119354760","https:\/\/openalex.org\/W2125831674","https:\/\/openalex.org\/W2293148314","https:\/\/openalex.org\/W2516707792","https:\/\/openalex.org\/W2604486584","https:\/\/openalex.org\/W2624122313","https:\/\/openalex.org\/W2884307971","https:\/\/openalex.org\/W3110869743","https:\/\/openalex.org\/W3140720939","https:\/\/openalex.org\/W3160984420","https:\/\/openalex.org\/W3186888684","https:\/\/openalex.org\/W4200557822","https:\/\/openalex.org\/W4234749407","https:\/\/openalex.org\/W6676179485","https:\/\/openalex.org\/W6677438662","https:\/\/openalex.org\/W6832735128"],"related_works":["https:\/\/openalex.org\/W2132668926","https:\/\/openalex.org\/W2156550631","https:\/\/openalex.org\/W1875577501","https:\/\/openalex.org\/W2042759115","https:\/\/openalex.org\/W1973505932","https:\/\/openalex.org\/W2547355295","https:\/\/openalex.org\/W2914442136","https:\/\/openalex.org\/W2098851424","https:\/\/openalex.org\/W2159053194","https:\/\/openalex.org\/W81532778"],"abstract_inverted_index":{"Placement":[0],"is":[1],"a":[2,30,49,101,106,112,136],"critical":[3],"stage":[4],"in":[5,33,35],"VLSI":[6],"physical":[7],"design,":[8],"especially":[9],"for":[10],"routability":[11,34,56,132],"optimization.":[12],"Due":[13],"to":[14,54,104],"the":[15,23,36,42,70,90,116,130,140],"large":[16],"scale":[17],"and":[18,60,75,94,115],"high":[19],"integration":[20],"introduced":[21],"by":[22,57,68,89],"advanced":[24],"semiconductor":[25],"manufacturing":[26],"technology,":[27],"there":[28],"remains":[29],"significant":[31],"challenge":[32],"placement":[37,50,108],"stage,":[38],"which":[39],"will":[40],"affect":[41],"subsequent":[43],"routing":[44,73],"process.":[45],"This":[46],"paper":[47],"proposes":[48],"framework,":[51],"called":[52],"PUFFER,":[53],"optimize":[55],"cell":[58,77,82],"padding":[59,83],"strategy":[61],"exploration.":[62],"The":[63],"framework":[64,128],"first":[65],"estimates":[66],"congestion":[67],"imitating":[69],"behaviors":[71],"of":[72,92],"detours":[74],"clustered":[76],"spreading.":[78],"Then":[79],"it":[80,99],"calculates":[81],"based":[84],"on":[85,122,133],"multiple":[86],"features":[87],"inspired":[88],"characteristics":[91],"convolutional":[93],"graph":[95],"neural":[96],"networks.":[97],"Besides,":[98],"applies":[100],"Bayesian-based":[102],"method":[103],"explore":[105],"better":[107],"strategy.":[109],"Compared":[110],"with":[111,135],"commercial":[113,141],"tool":[114],"state-of-the-art":[117],"academic":[118],"RePlAce":[119],"placer,":[120],"experiments":[121],"industrial":[123],"benchmarks":[124],"show":[125],"that":[126],"our":[127],"achieves":[129],"best":[131],"average,":[134],"2.7\u00d7":[137],"speedup":[138],"over":[139],"tool.":[142]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}