{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T11:22:30Z","timestamp":1730287350902,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/parelec.2006.40","type":"proceedings-article","created":{"date-parts":[[2006,10,24]],"date-time":"2006-10-24T13:07:05Z","timestamp":1161695225000},"page":"89-94","source":"Crossref","is-referenced-by-count":1,"title":["Generalised Resource Model for Parallel Instruction Scheduling"],"prefix":"10.1109","author":[{"given":"J.","family":"Muller","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196114"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/INTERA.2004.1299506"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISPAN.2004.1300478"},{"key":"ref13","first-page":"34","author":"m\u00fcller","year":"2005","journal-title":"Technical Report"},{"journal-title":"VLSI Digital Signal Processing Systems Design and Implementation","year":"1999","author":"parhi","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/2.820037"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/40.877947"},{"key":"ref3","first-page":"1560","article-title":"Resource-Optimal Software Pipelining Using Flow Graphs","volume":"e86 d","author":"fimmel","year":"2003","journal-title":"Institute of Electronics Information and Communication Engineers (IEICE) Transactions on Information and Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1225972"},{"key":"ref8","first-page":"2","article-title":"Retrospective: Software Pipelining: An Effective Scheduling Technique for VLIW Machines","author":"lam","year":"2003","journal-title":"20 Years of the ACM SIGPLAN Conference on Programming Language Design and Implementation PLDI (1979–1999) A Selection"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/40.888704"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1142\/S0129054101000825"},{"key":"ref1","first-page":"15","article-title":"An Overview of the Intel IA-64 Compiler","author":"dulong","year":"1999","journal-title":"Intel Technology Journal"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1018133"}],"event":{"name":"International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)","location":"Bialystok, Poland"},"container-title":["International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11156\/35814\/01698642.pdf?arnumber=1698642","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T19:09:47Z","timestamp":1489604987000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1698642\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/parelec.2006.40","relation":{},"subject":[]}}