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It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre\u2010computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state\u2010of\u2010the\u2010art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)\u2010only common Z coordinate (co\u2010Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V\u20106 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6\u00a0ms which is up to 9 times speed\u2010up over the state\u2010of\u2010the\u2010art.<\/jats:p>","DOI":"10.1002\/cta.2504","type":"journal-article","created":{"date-parts":[[2018,6,19]],"date-time":"2018-06-19T21:06:13Z","timestamp":1529442373000},"page":"1858-1878","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":31,"title":["A high\u2010speed RSD\u2010based flexible ECC processor for arbitrary curves over general prime field"],"prefix":"10.1002","volume":"46","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5156-5840","authenticated-orcid":false,"given":"Yasir Ali","family":"Shah","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering COMSATS Institute of Information Technology Abbottabad Khyber Pakhtunkhwa Pakistan"}]},{"given":"Khalid","family":"Javeed","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering Bahria University Islamabad Pakistan"}]},{"given":"Shoaib","family":"Azmat","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering COMSATS Institute of Information Technology Abbottabad Khyber Pakhtunkhwa Pakistan"}]},{"given":"Xiaojun","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering Dublin City University Dublin Ireland"}]}],"member":"311","published-online":{"date-parts":[[2018,6,19]]},"reference":[{"key":"e_1_2_7_2_1","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1987-0866109-5"},{"key":"e_1_2_7_3_1","first-page":"417","volume-title":"Conference on the Theory and Application of Cryptographic Techniques","author":"Miller VS","year":"1985"},{"key":"e_1_2_7_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/359340.359342"},{"key":"e_1_2_7_5_1","unstructured":"IEEE standard specifications for public\u2010key cryptography\u2014amendment 1: additional techniques IEEE Std 1363a\u20102004 (Amendment to IEEE Std 1363\u20102000) 2004; 1\u2010167."},{"key":"e_1_2_7_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.08.001"},{"key":"e_1_2_7_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2391274"},{"key":"e_1_2_7_8_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2016.0033"},{"key":"e_1_2_7_9_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85053-3_5"},{"key":"e_1_2_7_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019415"},{"key":"e_1_2_7_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294649"},{"key":"e_1_2_7_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2375640"},{"key":"e_1_2_7_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008507"},{"key":"e_1_2_7_14_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2295"},{"key":"e_1_2_7_15_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2016.12.005"},{"key":"e_1_2_7_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2103190"},{"key":"e_1_2_7_17_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2008.06.009"},{"key":"e_1_2_7_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-012-0042-2"},{"key":"e_1_2_7_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.880184"},{"key":"e_1_2_7_20_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ifs.2009.0038"},{"key":"e_1_2_7_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.889459"},{"key":"e_1_2_7_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2574620"},{"key":"e_1_2_7_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2455992"},{"key":"e_1_2_7_24_1","doi-asserted-by":"crossref","unstructured":"LiuS JuL CaiX JiaZ ZhangZ.High performance FPGA implementation of elliptic curve cryptography over binary fields. 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